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74f552
DATASHEETS (Philips)
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Datasheet 74f552 DATASHEETS (Philips)

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Page 1
74F552
Octal registered transceiver with parity and flags (3-State)
Product specification IC15 Data Handbook
 
1991 Jan 02
Page 2
Philips Semiconductors Product specification
74F552Octal registered transceiver with parity and flags (3-State)

FEA TURES

•8-bit bidirectional I/O port with handshake
•Register status flag flip-flops
•Separate clock enable and output enable
•Parity generation and parity check
•B outputs and parity output sink 64mA

DESCRIPTION

The 74F522 Octal Registered Transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock (CPR, CPS) and Clock Enable (CER
, CES) inputs, as well as a flag flip-flop that is set automatically as the register is loaded. The flag output will be reset when the Output Enable returns to High after reading the output port. Each register has a separate Output Enable (OEAS buffer . The separate Clocks, Flags and Enables provide considerable flexibility as I/O ports for demand-response data transfer. When data is transferred from the A port to the B port, a parity bit is generated. On the other hand, when data is transferred from the B port to the A port, the parity of input data on B0–B7 is checked.
TYPE
TYPICAL f
MAX
74F552 85MHz 120mA

ORDERING INFORMATION

COMMERCIAL RANGE
DESCRIPTION
28-Pin Plastic DIP
VCC = 5V ±10%,
T
= 0°C to +70°C
amb
N74F552N SOT117-2
(600mil) 28-Pin Plastic SOL N74F552D SOT136-1

LOGIC SYMBOL

18 17 16 15 14 13 12
, OEBR) for its 3-State
TYPICAL SUPPL Y
CURRENT
(TOTAL)
PKG DWG #
11

PIN CONFIGURATION

1
B4
2
B5
3
B6
4
B7
5
OEBR
6
CPR
7
CER
8
V
CC
9
ERROR
10
FS
11
A7
12 17
A6
13 16
A5
14 15
A4

LOGIC SYMBOL (IEEE/IEC)

6
7 5
20 21 19
18 17 16 15 14 13 12 11
XCVR 1C2 EN1’ EN6 6C4 EN3 EN6
3,4,6
Z7
28 27 26 25 24 23 22 21 20 19 18
SF01039
5,6 5,6
6,7
1,2,6
B3
B2 B1 B0 FR PARITY GND CES CPS
OEAS A0 A1 A2 A3
6
5
23
9 10 14
25 26 27 28 1 2 3 4
A0 A1 A4 A5 A6 A7 CPR CER
CES CPS
OEAS OEBR
B0 B1 B4 B5 B6 B7
= Pin 8
V
CC
GND = Pin 22
6 7
21 20 19
5
1991 Jan 02 853–1098 01347
A3A2
B2 B3
26 27 28
SF01040
FS
FR
23 10
24 9
SF01041
PARITY
ERROR
123425
2
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Philips Semiconductors Product specification
PARITY
74F552Octal registered transceiver with parity and flags (3-State)

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION
A0–A7 A Data inputs 3.5/1.0 70µA/0.6mA B0–B7 B Data inputs 3.5/1.0 70µA/0.6mA CPR R registers clock input (active rising edge) 1.0/1.0 20µA/0.6mA CPS S registers clock input (active rising edge) 1.0/1.0 20 µA/0.6mA CER R registers clock Enable input (active Low) 1.0/1.0 20µA/0.6mA CES S registers clock Enable input (active Low) 1.0/1.0 20µA/0.6mA
OEBR
OEAS
ERROR Parity check output (active Low) 50/33.3 1.0mA/20mA A0–A7 A Data outputs 150/40 3.0mA/24mA B0–B7 B Data outputs 750/106.7 15mA/64mA FR A-to-B Status Flag output (active High) 50/33.3 1.0mA/20mA FS B-to-A Status Flag output (active High) 50/33.3 1.0mA/20mA
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
A-to-B Output Enable input (active Low) and clear FS output (active Low)
B-to-A Output Enable input (active Low) and clear FR output (active Low)
Parity bit transceiver input 3.5/1.0 70µA/0.6mA Parity bit transceiver output 750/106.7 15mA/64mA
74F(U.L.)
HIGH/LOW
1.0/2.0 20µA/1.2mA
1.0/2.0 20µA/1.2mA
LOAD VALUE
HIGH/LOW

FUNCTIONAL DESCRIPTION

Data applied to the A inputs are entered and stored on the rising edge of the CPR clock pulse, provided that the CER simultaneously, the status flip-flop is set and the A-to-B flag (FR) output goes High. As the CER in R register. This data entered from the A inputs will appear at the B port I/O pins after the OEBR has gone Low. When OEBR is Low, a parity bit appears at the PARITY pin, which will be set High when there is an even number of 1s or all 0s at the Q outputs of the R register. After the data is assimilated, the receiving system clears the flag FR, by changing the signal at the OEBR High. Data flow from B-to-A proceeds in the same manner described for A-to-B flow. A Low at the CES the CPS pin enters the B input data and the parity input data into the S register and the parity register respectively and set the flag output FS to High. A Low signal at the OEAS pins and a Low-to-High transition of the OEAS flag. When OEAS High if there is an odd number of 1s at the Q outputs of the S register and the parity register.
is Low, the parity check output ERROR will be
returns to High, the data will be held
pin and a Low-to-High transition at
pin enables the A port I/O
is Low;
pin from Low to
signal clears the FS

R or S REGISTER FUNCTION TABLE

INPUTS OUTPUTS
An or Bn CPX CEX INTERNAL Q
X X H NC Hold data L
H X ↑ L NC Keep old data
H = High voltage level L = Low voltage level NC= No change X = Don’t care X = R or S for CPX and CEX
↑ = Low-to-High transition ↑
= Not Low-to-High transition
↑ ↑
L L
L
H
OPERATING

OUTPUT CONTROL TABLE

INPUT OUTPUTS
OEXX INTERNAL Q An or Bn
H X Z Disable outputs L
L
H = High voltage level L = Low voltage level X = Don’t care XX= AS or BR Z = High impedance “off” state
L
H
L
H
OPERATING
Enable outpus
MODE
Load data
MODE
1991 Jan 02
3
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Philips Semiconductors Product specification
74F552Octal registered transceiver with parity and flags (3-State)

R or S FLAG FUNCTION TABLE

INPUTS OUTPUTS
CEX CPX OEXX FR or FS
H X ↑ NC Hold flag
L ↑ ↑ H Set flag
X X ↑ L Clear flag
H = High voltage level L = Low voltage level NC= No change X = Don’t care
X = R or S for CPX and CEX XX= AS or BR
↑ = Low-to-High transition ↑
= Not Low-to-High transition
OPERATING

PARITY CHECK FUNCTION TABLE

INPUTS OUTPUTS
OEAS CPS PARITY
H
L L L L
H = High voltage level L = Low voltage level X = Don’t care ↑ = Low-to-High transition
X
↑ ↑ ↑ ↑
X L L H H

PARITY GENERATION FUNCTION TABLE

INPUTS OUTPUTS
MODE
OEBR CPR
H X X Z Hold flag
L L
H = High voltage level L = Low voltage level X = Don’t care Z = High impedance “off” state ↑ = Low-to-High transition
Number of Highs in the Q outputs
of the R register
X
0,2,4,6,8
1,3,5,7
0,2,4,6,8
1,3,5,7
↑ ↑
Number of Highs
in the Q outputs of the R register
0,2,4,6,8
1,3,5,7
ERROR
H
L H H
L
OPERATING
PARITY
H L
OPERATING MODE
Parity check
MODE
Load data
1991 Jan 02
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Philips Semiconductors Product specification
74F552Octal registered transceiver with parity and flags (3-State)

LOGIC DIAGRAM

21
CES
20
CPS
DETAIL A
DETAIL B
7
CER
CPR
6
18
A0
DQ
CP Q
D
Q
SEL SEL
Q
CP
DETAIL B
23
PARITY
25
B0
DETAIL A
D SEL SEL
CP
DETAIL B
O
Q
DETAIL B
DETAIL B
17
A1
DETAIL A
16
A2
DETAIL A
15
A3
DETAIL A
14
A4
DETAIL A
13
A5
DETAIL A
12
A6
DETAIL A
26
27
28
1
2
9
3
4
B1
B2
B3
B4
B5
ERROR
B6
B7
11
A7
5
OEBR
19
OEAS
VCC= Pin 8 GND = Pin 22
1991 Jan 02
CP CLR
QD
Q
QD
CP
Q
CLR
24
10
SF01042
FR
FS
5
Page 6
Philips Semiconductors Product specification
SYMBOL
PARAMETER
UNIT
74F552Octal registered transceiver with parity and flags (3-State)

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V V I
IN
V
I
OUT
T T
CC IN
OUT
amb stg
Supply voltage –0.5 to +7.0 V Input voltage –0.5 to +7.0 V Input current –30 to +V Voltage applied to output in High output state –0.5 to +V
Current applied to output in Low output state
Operating free-air temperature range 0 to +70 °C Storage temperature –65 to +150 °C

RECOMMENDED OPERATING CONDITIONS

V V V I
I
I
T
CC IH IL
IK
OH
OL
amb
Supply voltage 4.5 5.0 5.5 V High-level input voltage 2.0 V Low-level input voltage 0.8 V Input clamp current –18 mA
High-level output current
Low-level output current
Operating free-air temperature range 0 70 °C
PARAMETER RATING UNIT
CC
CC
mA
V
FR, FS, ERROR 40 mA
A0–A7 48 mA
B0–B7, PARITY 128 mA
LIMITS
MIN NOM MAX
FR, FS, ERROR –1 mA
A0–A7 –3 mA
B0–B7, PARITY –15 mA
FR, FS, ERROR 20 mA
A0–A7 24 mA
B0–B7, PARITY 64 mA
1991 Jan 02
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Philips Semiconductors Product specification
NO TAG
FR, FS, ERROR
I
1mA
V
g
A0–A7
V
MAX
I
3mA
B0–B7, PARITY
I
15mA
FR. FS. ERROR
I
20mA
V
A0–A7
V
MAX
I
24mA
B0–B7, PARITY
I
V
MAX, V
5V
B0–B7
OS
OS
CC
(
)
(total)
74F552Octal registered transceiver with parity and flags (3-State)

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
SYMBOL PARAMETER TEST CONDITIONS
MIN
TYP
NO TAG
MAX
UNIT
OH
OL
V
IK
I
I
I
IH
IL
I
OZH+IIH
I
OZL+IIL
I
I
CC
= –
OH
High-level output voltage
Low-level output voltage
VCC = MIN,
=
IL
VIH = MIN
VCC = MIN,
=
IL
VIH = MIN
,
= –
OH
= –
OH
=
OL
,
=
OL
I
= 48mA ±10%V
OL
I
= 64mA ±5%V
OL
Input clamp voltage VCC = MIN, II = I Input current at
maximum input voltage
High-level input current
Low-level input current
Off-state output current High-level voltage applied
Off-state output current Low-level voltage applied
Short-circuit output
NO TAG
current
Supply current
total
others VCC = MAX, VI = 7.0V 100 µA A0–A7, B0–B7,
PARITY
VCC = 5.5V, VI = 5.5V 1 mA
others except
A0–A7, B0–B7,
VCC = MAX, VI = 2.7V 20 µA
PARITY
others
OEAS, OEBA
A0–A7,
CC
=
= 0.
I
VCC = MAX, VO = 2.7V 70 µA
,
PARITY
V
= MAX, VO = 0.5V –600 µA
CC
A0–A7, FS, FR, ERROR
VCC = MAX
B0–B7, PARITY
I
CCH
I
CCL
I
CCZ
VCC = MAX
IK
±10%V
±5%V
±10%V
±5%V
±10%V
±5%V
±10%V
±5%V
±10%V
±5%V
CC
CC
CC
CC
CC
CC
2.5 V
CC
2.7 3.4 V
2.4 V
CC
2.7 3.3 V
2.0 V
CC
2.0 V
CC
0.30 0.50 V
0.30 0.50 V
CC
0.35 0.50 V
0.35 0.50 V
CC
0.38 0.55 V
0.42 0.55 V
–0.73 –1.2 V
–60 –150 mA
–100 –225 mA
115 170 mA 125 185 mA 120 180 mA
–0.6 mA –1.2 mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value under the recommended operating conditions for the applicable type.
2. All typical values are at V
3. Not more than one output should be shorted at a time. For testing I
= 5V, T
CC
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
amb
= 25°C.
, the use of high-speed test apparatus and/or sample-and-hold
OS
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I
should be performed last.
OS
1991 Jan 02
7
Page 8
Philips Semiconductors Product specification
TEST
CONDITIONS
TEST
CONDITIONS
74F552Octal registered transceiver with parity and flags (3-State)

AC ELECTRICAL CHARACTERISTICS

LIMITS
T
SYMBOL PARAMETER
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum Clock Frequency Waveform 1 70 85 60 MHz Propagation delay
CPS to An or CPR to Bn Propagation delay
CPS to FS or CPR to FR Propagation delay
OEAS to FS or OEBR to FR Propagation delay
CPS to ERROR Propagation delay
CPR to PARITY Propagation delay
OEAS to ERROR
Output Enable time OEAS to An or OEBR to Bn
Output Disable time OEAS to An or OEBR to Bn
Output Enable time OEBR to PARITY
Output Disable time OEBR to PARITY
= +25°C T
amb
VCC = +5.0V VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
Waveform 1
3.5
4.0
5.0
6.0
8.0
9.0
Waveform 1 3.0 5.0 7.5 2.5 8.5 ns
Waveform 2 4.0 6.0 8.5 3.5 9.0 ns
Waveform 4
Waveform 4
Waveform
NO TAG
6.5
7.5
6.5
10.5
3.5
3.0
13.0
11.5
8.5
13.5
5.5
5.0
16.5
15.0
11.0
17.0
8.0
7.0
Waveform
NO TAG
Waveform
2.5
4.0
4.0
6.5
7.0
9.5
NO TAG
Waveform
NO TAG
Waveform
2.0
2.0
4.0
3.5
7.0
7.0
NO TAG
Waveform
NO TAG
Waveform
2.0
4.0
4.0
5.5
7.0
8.0
NO TAG
Waveform
NO TAG
Waveform
2.0
2.0
4.0
4.0
7.0
7.5
NO TAG
= 0°C to +70°C
amb
3.0
3.5
6.0
7.0
5.5
10.0
3.0
2.5
2.0
4.0
1.5
1.5
2.0
3.0
2.0
2.0
8.5
9.0
18.0
16.0
12.5
18.0
8.5
8.0
8.0
10.5
8.5
7.5
7.5
9.0
7.5
8.0
UNIT
ns ns
ns ns
ns ns
ns ns
ns ns
ns ns
ns ns
ns ns
AC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
ts(H) ts(L)
th(H) th(L)
ts(H) t
(L)
s
th(H) th(L)
tw(H) tw(L)
t
REC
1991 Jan 02
Setup time, High or Low An or Bn or PARITY to CPS or CPR
Hold time, High or Low An or Bn or PARITY to CPS or CPR
Setup time, High or Low CES
to CPS or CER to CPR
Hold time, High or Low CES to CPS or CER to CPR
CPS or CPR Pulse width, High or Low
Recovery time OEBR to CPR or OEAS to CPS
LIMITS
T
= +25°C T
amb
VCC = +5.0V VCC = +5.0V ± 10%
= 0°C to +70°C
amb
UNIT
CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
Waveform 5
Waveform 5
Waveform 5
Waveform 5
Waveform 1
7.5
4.5 0
0
7.0
7.0 0
0
5.0
6.5
8.5
5.5 0
0
7.5
7.5 0
0
6.5
7.5
ns
ns
ns
ns
ns
Waveform 6 14.5 16.5 ns
8
Page 9
Philips Semiconductors Product specification
74F552Octal registered transceiver with parity and flags (3-State)

AC WAVEFORMS

For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted ot change for predictable output.
1/f
MAX
t
(H)
CPS,
CPR
An, Bn
FS, FR
V
M
t
(L)
W
t
PHL
V
M
V
M
t
PLH
V
M
OEAS, OEBR
FS, FR
W
V
M
t
PHL
V
M
SF01043
Waveform 1. Propagation Delay, Clock Input to Output and
Maximum Clock Frequency
OEAS
ERROR
V
M
t
PHL
V
M
t
PLH
V
M
V
M
SF01045
Waveform 3. Propagation Delay, Output Enable to ERROR
An, Bn
, CER
CES
PARITY
CPS, CPR
V
V
M
ts(L) ts(H) th(L)th(H)
V
M
M
V
MVM
V
M
SF01047
Waveform 5. Data Setup and Hold Times
SF01044
Waveform 2. Propagation Delay, Output Enable to Flag Output
CPS,
CPR
PARITY
ERROR
V
M
t
PLH
t
PHL
V
M
V
M
V
M
V
t
t
PHL
PLH
M
V
M
SF01046
Waveform 4. Propagation Delay, Clock to PARITY and ERROR
OEAS, OEBR
CPS,
CPR
V
M
t
REC
V
M
SF01048
Waveform 6. Recovery Time from Output Enable to Clock
OEAS, OEBR
An, Bn
PARITY
V
M
t
PZH
V
M
t
PHZ
V
M
Waveform 7. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
1991 Jan 02
VOH -0.3V
SF01049
OEAS, OEBR
An, Bn
0V
PARITY
V
M
t
PZL
V
V
M
t
PLZ
M
+0.3V
V
OL
SF01050
Waveform 8. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
9
Page 10
Philips Semiconductors Product specification
74F552Octal registered transceiver with parity and flags (3-State)

TEST CIRCUIT AND WAVEFORM

V
V
PULSE
GENERATOR
IN
R
Test Circuit for 3-State Outputs
SWITCH POSITION
TEST SWITCH
t t
PLZ PZL
closed closed
All other open
T
D.U.T.
CC
V
OUT
7.0V
R
L
C
R
L
L
NEGATIVE PULSE
POSITIVE PULSE
90%
10%
V
M
10%
t
THL (tf
t
TLH (tr
90%
V
M
Input Pulse Definition
t
w
V
M
10%
)
)
t
)
TLH (tr
t
)
THL (tf
90%
V
M
t
w
90%
10%
AMP (V)
0V
AMP (V)
0V
DEFINITIONS:
= Load resistor;
R
L
see AC electrical characteristics for value.
C
= Load capacitance includes jig and probe capacitance;
L
see AC electrical characteristics for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
OUT
of
family
74F
INPUT PULSE REQUIREMENTS
V
amplitude
3.0V
M
1.5V
rep. rate
1MHz 500ns
t
w
t
TLHtTHL
2.5ns 2.5ns
SF00777
1991 Jan 02
10
Page 11
Philips Semiconductors Product specification
Octal registered transceiver with parity and flags (3-State)

DIP28: plastic dual in-line package; 28 leads (600 mil); long body SOT117-2

74F552
1991 Jan 02
11
Page 12
Philips Semiconductors Product specification
Octal registered transceiver with parity and flags (3-State)

SO28: plastic small outline package; 28 leads; body width 7.5mm SOT136-1

74F552
1991 Jan 02
12
Page 13
Philips Semiconductors Product specification
Octal registered transceiver with parity and flags (3-State)
NOTES
74F552
1991 Jan 02
13
Page 14
Philips Semiconductors Product specification
Octal registered transceiver with parity and flags (3-State)

Data sheet status

Data sheet status
Objective specification
Preliminary specification
Product specification
Product status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
[1]
74F552
[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 10-98 Document order number: 9397-750-05137
 
yyyy mmm dd
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