Datasheet 74F541SC, 74F541PCQR, 74F541PC, 74F541SJX, 74F541SJ Datasheet (Fairchild Semiconductor)

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April 1988 Revised August 1999

74F540 • 74F541 Octal Buffer/Line Driver with 3-STATE Outputs

General Description

The 74F540 and 74F541 are similar in function to the 74F240 and 74F244 respectively, except that the inputs and outputs are on opposite sides of the package (see Connection Diagrams). This pinout arrangement makes these devices especially use ful as output ports for micr oprocessors, allowing ease of layou t and grea ter PC board density.

Features

■ 3-STATE outputs drive bus lines

■ Inputs and outputs opposite side of package, allowing

easier interface to microprocessors

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbols

IEEE/IEC

74F540

IEEE/IEC

74F541

Connection Diagrams

74F540

74F541

Order Number Package Number Package Description

74F540SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F540SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F540PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74F541SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F541SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F541PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F540 • 74F541

Unit Loading/Fan Out

Truth Table

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

OE1, OE

3-STATE Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA

Inputs 1.0/1.0 20 µA/−0.6 mA

, O

Outputs 600/106.6 (80) −12 mA/64 mA (48 mA)

Inputs Outputs

I 74F540 74F541 LLHLH HXXZZ XHXZZ LLLHL

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74F540 • 74F541

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyon d which the device

may be damaged or have its useful life impaired . Functional operation under these condit ions is not implied.

Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.

DC Electrical Characteristics

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V

Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output

in HIGH State (with V

= 0V)

Standard Output −0.5V to V

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

(mA)

Free Air Ambi ent Temperat ure 0°C to +70°C Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

Conditions

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

Output HIGH 10% V

2.4 VMin

IOH = −3 mA

Voltage 10% V

2.0 IOH = −15 mA

5% V

2.7 IOH = −3 mA

Output LOW

10% V

0.55 V Min IOL = 64 mA

Voltage

Input HIGH

5.0 µAMaxVIN = 2.7V

Current

BVI

Input HIGH Current

7.0 µAMaxVIN = 7.0V

Breakdown Test

CEX

Output HIGH

50 µAMaxV

OUT

= V

Leakage Current

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All Other Pins Grounded

Output Leakage

3.75 µA0.0

IOD

= 150 mV

Circuit Current All Other Pins Grounded

Input LOW Current −0.6 mA Max VIN = 0.5V

OZH

Output Leakage Current 50 µAMaxV

OUT

= 2.7V

OZL

Output Leakage Current −50 µAMaxV

OUT

= 0.5V

Output Short-Circuit Current −100 −225 mA Max V

OUT

= 0V

Bus Drainage Test 500 µA0.0VV

OUT

= 5.25V

CCH

Power Supply Current (’74F540) 11 20 mA Max VO = HIGH

CCL

Power Supply Current (74F540) 53 75 mA Max VO = LOW

CCZ

Power Supply Current (74F540) 31 45 mA Max VO = HIGH Z

CCH

Power Supply Current (74F541) 26 35 mA Max VO = HIGH

CCL

Power Supply Current (74F541) 55 75 mA Max VO = LOW

CCZ

Power Supply Current (74F541) 31 55 mA Max VO = HIGH Z

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74F540 • 74F541

AC Electrical Characteristics

Symbol Parameter

TA = +25°CT

= −55°C to +125°CTA = 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF CL = 50 pF

Min T yp Max Min Max Min Max

PLH

Propagation Delay 1.5 3.0 5.0 1.0 6.0 1.0 5.5

PHL

Data to Output (74F540) 1.0 2.0 4.0 1.0 4.5 1.0 4.0

PZH

Output Enable Time (74F540) 2.5 4.9 8.0 2.5 9.0 2.5 8.5

PZL

3.5 5.8 10.0 3.5 11.0 3.5 10.5

PHZ

Output Disable Time (74F540) 1.5 3.4 6.0 1.5 7.0 1.5 6.5

PLZ

1.0 2.5 5.5 1.0 7.5 1.0 6.0

PLH

Propagation Delay 1.5 3.3 5.5 1.5 6.0

PHL

Data to Output (74F541) 1.5 2.7 5.5 1.5 6.0

PZH

Output Enable Time (74F541) 3.0 5.8 8.0 2.5 9.5

PZL

3.5 6.1 8.5 3.0 9.5

PHZ

Output Disable Time (74F541) 1.5 3.4 6.0 1.5 6.5

PLZ

1.5 2.9 5.5 1.5 6.0

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74F540 • 74F541

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M20B

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74F540 • 74F541 Octal Buffer/Line Driver with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N20A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the user.

2. A critical component in any componen t of a life su pport device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort device or system, or to affect its safety or effectiveness.

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