Page 1
FAST PRODUCTS
74F373
Octal transparent latch (3-State)
74F374
Octal D flip-flop (3-State)
Product specification 1994 Dec 05
IC15 Data Handbook
Philips Semiconductors
Page 2
Philips Semiconductors Product specification
74F373/74F374Latch/flip-flop
74F373 Octal transparent latch (3-State)
74F374 Octal D-type flip-flop (3-State)
FEA TURES
•8-bit transparent latch — 74F373
•8-bit positive edge triggered register — 74F374
•3-State outputs glitch free during power-up and power-down
•Common 3-State output register
•Independent register and 3-State buffer operation
•SSOP Type II Package
DESCRIPTION
The 74F373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is high. The latch remains transparent to the data
input while E is high, and stores the data that is present one setup
time before the high-to-low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active low output enable (OE
independent of the latch operation. When OE
transparent data appears at the output.
When OE
which means they will neither drive nor load the bus.
is high, the outputs are in high impedance “off” state,
) controls all eight 3-State buffers
) control gates.
is low, latched or
The 74F374 is an 8-bit edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by clock (CP) and output enable (OE
The register is fully edge triggered. The state of the D input, one
setup time before the low-to-high clock transition is transferred to the
corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active low output enable (OE
independent of the register operation. When OE
the register appears at the outputs. When OE
are in high impedance “off” state, which means they will neither drive
nor load the bus.
TYPE
74F373 4.5ns 35mA
TYPE TYPICAL f
74F374 165MHz 55mA
PROPAGATION
) controls all eight 3-State buffers
TYPICAL
DELA Y
max
) control gates.
is low, the data in
is high, the outputs
TYPICAL SUPPL Y
CURRENT
(TOTAL)
TYPICAL SUPPL Y
CURRENT
(TOTAL)
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE PKG DWG #
VCC = 5V ±10%, T
20-pin plastic DIP N74F373N, N74F374N SOT146-1
20-pin plastic SOL N74F373D, N74F374D SOT163-1
20-pin plastic SSOP type II N74F373DB, N74374DB SOT399-1
= 0°C to +70°C
amb
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION
D0 - D7 Data inputs 1.0/1.0
E (74F373) Enable input (active high) 1.0/1.0
OE Output enable inputs (active low) 1.0/1.0
CP (74F374) Clock pulse input (active rising edge) 1.0/1.0
Q0 - Q7 3-State outputs 150/40 3.0mA/24mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
December 5, 1994 853-0369 14383
2
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Philips Semiconductors Product specification
74F373/74F374Latch/flip-flop
PIN CONFIGURATION – 74F373
OE
1
Q0
2
D0
3
D1
4
Q1
5
Q2
6
D2
7
D3
8
Q3
9
GND
10 11
LOGIC SYMBOL – 74F373
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
11
E
OE
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
PIN CONFIGURATION – 74F374
OE
V
20
CC
19
Q7
18
D7
17
D6
16
Q6
15
Q5
14
D5
13
D4
12
Q4
E
SF00250
1
Q0
2
D0
3
D1
4
Q1
5
Q2
6
D2
7
D3
8
Q3
9
GND
10 11
V
20
Q7
19
D7
18
D6
17
Q6
16
Q5
15
D5
14
D4
13
Q4
12
CP
SF00253
CC
IEC/IEE SYMBOL – 74F374
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
11
CP
OE
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
= Pin 20
V
CC
GND = Pin 10
IEC/IEEE SYMBOL – 74F373
1
11
3
4
7
8
13
14
17
18
EN1
EN2
2D
2 5 6 9 12 15 16 19
V
= Pin 20
CC
SF00251
GND = Pin 10
SF00254
IEC/IEEE SYMBOL – 74F374
1
11
SF00252
2
5
6
9
12
15
16
19
13
14
17
18
1
EN1
C2
3
4
7
8
2D
1
2
5
6
9
12
15
16
19
SF00255
December 5, 1994
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Philips Semiconductors Product specification
OPERATING MODE
Enable and read register
Latch and read register
Disable outputs
74F373/74F374Latch/flip-flop
LOGIC DIAGRAM FOR 74F373
D0
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
V
= Pin 20
CC
GND = Pin 10
E
OE
Q0
D
Q
E
2
D
Q
E
11
1
Q1
D
Q
E
5
Q2
D
Q
E
6
Q3
D
Q
E
9
Q4
LOGIC DIAGRAM FOR 74F374
VCC = Pin 20
GND = Pin 10
CP
OE
D0
3
D
CP
11
1
D1
4
Q0
D
CP
2
Q
D2
7
Q1
D
CP
5
Q
D3
8
Q2
D
CP
6
Q
D4
13
Q
9
Q3
D
CP
D5
Q
Q4
FUNCTION TABLE FOR 74F373
INPUTS
OE E Dn
INTERNAL
REGISTER
L H L L L
L H H H H
L ↓ l L L
L ↓ h H H
L L X NC NC Hold
H L X NC Z
H H Dn Dn Z
NOTES:
H = High-voltage level
h = High state must be present one setup time before the high-to-low enable transition
L = Low-voltage level
l = Low state must be present one setup time before the high-to-low enable transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↓ = High-to-low enable transition
OUTPUTS
Q0 - Q7
D
Q
E
12
14
D
Q
CP
12
Q5
Q5
D
E
15
D6
17
D
CP
15
D
Q
Q
Q6
Q6
Q
E
16
D7
18
D
CP
16
19
Q7
SF00256
Q
19
Q7
SF00257
p
December 5, 1994
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Philips Semiconductors Product specification
OPERATING MODE
Load and read register
Disable outputs
SYMBOL
PARAMETER
UNIT
74F373/74F374Latch/flip-flop
FUNCTION TABLE FOR 74F374
INPUTS INTERNAL OUTPUTS
OE CP Dn REGISTER Q0 - Q7
L ↑ l L L
L ↑ h H H
L ↑ X NC NC Hold
H ↑ X NC Z
H ↑ Dn Dn Z
NOTES:
H = High-voltage level
h = High state must be present one setup time before the low-to-high clock transition
L = Low-voltage level
l = Low state must be present one setup time before the low-to-high clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low-to-high clock transition
= Not low-to-high clock transition
↑
p
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage -0.5 to +7.0 V
Input voltage -0.5 to +7.0 V
Input current -30 to +5 mA
Voltage applied to output in high output state -0.5 to V
Current applied to output in low output state
Operating free air temperature range 0 to +70 °C
Storage temperature range -65 to +150 °C
PARAMETER RATING UNIT
CC
48 mA
RECOMMENDED OPERATING CONDITIONS
LIMITS
MIN NOM MAX
V
V
V
I
I
I
T
CC
IH
IL
Ik
OH
OL
amb
Supply voltage
High-level input voltage 2.0 V
Low-level input voltage 0.8 V
Input clamp current -18 mA
High-level output current -3 mA
Low-level output current
Operating free air temperature range 0 +70
4.5 5.0 5.5 V
24 mA
V
°C
December 5, 1994
5
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Philips Semiconductors Product specification
SYMBOL
PARAMETER
UNIT
VOHHigh-l
VOLLow-level output voltage
3
ICCSupply current (total)
V
MAX
74F373/74F374Latch/flip-flop
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
MIN TYP2MAX
2.4 V
2.7 3.4 V
0.35 0.50 V
0.35 0.50 V
-0.73 -1.2 V
µA
µA
35 60 mA
57 86 mA
V
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
TEST
CONDITIONS
VCC = MIN, VIL = MAX,
evel output voltage
VIH = MIN, IOH = MAX
p
IK
Input clamp voltage VCC = MIN, II = I
VCC = MIN, VIL = MAX, ±10%V
VIH = MIN, IOL = MAX
IK
Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA
High-level input current VCC = MAX, VI = 2.7V 20 µA
Low-level input current VCC = MAX, VI = 0.5V -0.6 mA
Off-state output current, high-level voltage applied VCC = MAX, V
= 2.7V 50
O
Off-state output current, low-level voltage applied VCC = MAX, VO = 0.5V -50
Short-circuit output current
pp
74F373
74F374
VCC = MAX -60 -150 mA
=
CC
1
±10%V
±5%V
±5%V
CC
CC
CC
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
= 5V, T
CC
amb
= 25°C.
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
tests should be performed last.
OS
AC ELECTRICAL CHARACTERISTICS
T
= +25°C T
amb
SYMBOL PARAMETER TEST VCC = +5.0V
CONDITION CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
Dn to Qn
Propagation delay
E to Qn
Output enable time
to high or low level
Output disable time
from high or low level
Waveform 3
74F373
Waveform 2
Waveform 6
Waveform 7
Waveform 6
Waveform 7
3.0
2.0
5.0
3.0
2.0
2.0
2.0
2.0
5.3
3.7
9.0
4.0
5.0
5.6
4.5
3.8
Maximum clock frequency Waveform 1 150 165 140 ns
Propagation delay
CP to Qn
Output enable time
to high or low level
Output disable time
from high or low level
74F374
Waveform 1
Waveform 6
Waveform 7
Waveform 6
Waveform 7
3.5
3.5
2.0
2.0
2.0
2.0
5.0
5.0
9.0
5.3
5.3
4.3
LIMITS
7.0
5.0
11.5
7.0
11.0
7.5
6.5
5.0
7.5
7.5
11.0
7.5
6.0
5.5
= 0°C to +70°C
amb
VCC = +5.0V ± 10%
3.0
2.0
5.0
3.0
2.0
2.0
2.0
2.0
3.0
3.0
2.0
2.0
2.0
2.0
8.0
6.0
12.0
8.0
11.5
8.5
7.0
6.0
8.5
8.5
12.0
8.5
7.0
6.5
UNIT
ns
ns
ns
ns
ns
ns
ns
December 5, 1994
6
Page 7
Philips Semiconductors Product specification
74F373/74F374Latch/flip-flop
AC SETUP REQUIREMENTS
LIMITS
T
= +25°C T
amb
SYMBOL PARAMETER TEST VCC = +5.0V
CONDITION CL = 50pF, RL = 500Ω CL= 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
t
(H)
su
t
(L)
su
t
(H)
h
t
(L)
h
t
(H) E Pulse width, high Waveform 1 3.5 4.0 ns
w
t
(H)
su
t
(L)
su
t
(H)
h
t
(L)
h
t
(H)
w
t
(L)
w
Setup time, high or low level
Dn to E
Hold time, high or low level
Dn to E
Setup time, high or low level
Dn to CP
Hold time, high or low level
Dn to CP
CP Pulse width,
high or low
74F373
74F374
Waveform 4
Waveform 4
Waveform 5
Waveform 5
Waveform 5
0
1.0
3.0
3.0
2.0
2.0
0
0
3.5
4.0
= 0°C to +70°C
amb
VCC = +5.0V ± 10%
0
1.0
3.0
3.0
2.0
2.0
0
0
3.5
4.0
UNIT
ns
ns
ns
ns
ns
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for
predictable output performance.
1/f
max
CP
V
M
Qn
tw(H)
PLH
Waveform 1. Propagation delay for clock input to output,
clock pulse widths, and maximum clock frequency
tw(H)
EV
M
t
PHL
Qn
Waveform 2. Propagation delay for enable to output
V
M
tw(L)t
V
M
V
M
V
M
and enable pulse width
V
V
t
M
t
PHL
M
PLH
V
M
SF00258
V
M
SF00259
Dn
Qn
V
M
t
PLH
V
M
t
PHL
V
V
M
M
Waveform 3. Propagation delay for data to output
Dn
E
V
M
t
(H) th(H)
su
V
M
V
M
V
M
tsu(L) th(L)
Waveform 4. Data setup time and hold times
SF00260
V
V
M
M
SF00261
December 5, 1994
7
Page 8
Philips Semiconductors Product specification
74F373/74F374Latch/flip-flop
AC WAVEFORMS (Continued)
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for
predictable output performance.
Dn
CP
V
M
t
(H) th(H)
su
V
M
V
M
V
M
tsu(L) th(L)
Waveform 5. Data setup time and hold times
OEn
Qn, Qn
V
t
PZH
M
V
M
t
PHZ
V
M
Waveform 6. 3-State output enable time to high level
and output disable time from high level
TEST CIRCUIT AND WAVEFORMS
SWITCH POSITION
TEST SWITCH
, t
t
PLZ
PZL
closed
openAll other
V
PULSE
GENERATOR
IN
Test circuit for 3-state outputs
DEFINITIONS:
R
Load resistor; see AC electrical characteristics for value.
L =
C
Load capacitance includes jig and probe capacitance;
L =
see AC electrical characteristics for value.
Termination resistance should be equal to Z
R
T =
generators.
V
CC
V
D.U.T.
R
T
OUT
C
L
R
R
OUT
V
L
L
V
M
M
VOH -0.3V
SF00263
of pulse
SF00262
0V
7.0V
NEGATIVE
PULSE
POSITIVE
PULSE
family
74F
OEn
Qn, Q
n
V
t
PZL
M
V
V
M
t
PLZ
M
Waveform 7. 3-State output enable time to low level
and output disable time from low level
t
90%
10%
V
M
10%
t
THL (tf
t
TLH (tr
90%
V
M
w
10%
)
)
t
w
t
TLH (tr
t
THL (tf
)
)
90%
90%
V
M
V
M
10%
Input pulse definition
INPUT PULSE REQUIREMENTS
V
amplitude
3.0V
1.5V
rep. rate
M
1MHz 500ns 2.5ns
t
w
t
TLHtTHL
VOL +0.3V
SF00264
AMP (V)
0V
AMP (V)
0V
2.5ns
December 5, 1994
SF00265
8
Page 9
Philips Semiconductors Product specification
74F373, 74F374Latch/flip-flop
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
1994 Dec 05
9
Page 10
Philips Semiconductors Product specification
74F373, 74F374Latch/flip-flop
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
1994 Dec 05
10
Page 11
Philips Semiconductors Product specification
74F373, 74F374Latch/flip-flop
NOTES
1994 Dec 05
11
Page 12
Philips Semiconductors FAST Products Product specification
74F373, 74F374Latch/flip-flop
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1994
All rights reserved. Printed in U.S.A.
(print code) Date of release: July 1994
Document order number: 9397-750-051 19
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