Datasheet 74f373_374_3 Datasheet

INTEGRATED CIRCUITS

74F373

Octal transparent latch (3-State)

74F374

Octal D flip-flop (3-State)

Product data
Supersedes data of 1994 Dec 05

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Philips Semiconductors Product data

74F373/74F374Latch/flip-flop

74F373 Octal transparent latch (3-State)
74F374 Octal D-type flip-flop (3-State)

FEATURES

•8-bit transparent latch — 74F373

•8-bit positive edge triggered register — 74F374

•3-State outputs glitch free during power-up and power-down

•Common 3-State output register

•Independent register and 3-State buffer operation

•SSOP Type II Package

DESCRIPTION

The 74F373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE

The data on the D inputs is transferred to the latch outputs when the
enable (E) input is HIGH. The latch remains transparent to the data
input while E is HIGH, and stores the data that is present one set-up
time before the HIGH-to-LOW enable transition.

The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.

The active-LOW output enable (OE
independent of the latch operation. When OE
transparent data appears at the output.

When OE
which means they will neither drive nor load the bus.

is HIGH, the outputs are in high impedance “off” state,

) controls all eight 3-State buffers

) control gates.

is LOW, latched or

The 74F374 is an 8-bit edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by clock (CP) and output enable (OE

The register is fully edge triggered. The state of the D input, one
set-up time before the LOW-to-HIGH clock transition is transferred
to the corresponding flip-flop’s Q output.

The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.

The active-LOW output enable (OE
independent of the register operation. When OE
the register appears at the outputs. When OE

are in high impedance “off” state, which means they will neither drive

nor load the bus.

TYPE

74F373 4.5 ns 35 mA

TYPE TYPICAL f

74F374 165 MHz 55 mA

PROPAGATION

) controls all eight 3-State buffers

TYPICAL

DELA Y

max

) control gates.

is LOW, the data in

is HIGH, the outputs

TYPICAL SUPPL Y

CURRENT

(TOTAL)

TYPICAL SUPPL Y

CURRENT

(TOTAL)

ORDERING INFORMATION

ORDER CODE

DESCRIPTION COMMERCIAL RANGE PKG DWG #

VCC = 5 V ±10%, T

20-pin plastic DIP N74F373N, N74F374N SOT146-1

20-pin plastic SOL N74F373D, N74F374D SOT163-1

20-pin plastic SSOP type II N74F373DB, N74F374DB SOT339-1

= 0 °C to +70 °C

amb

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS DESCRIPTION

D0 - D7 Data inputs 1.0 / 1.0 20 µA / 0.6 mA

E (74F373) Enable input (active-HIGH) 1.0 / 1.0 20 µA / 0.6 mA

OE Output enable inputs (active-LOW) 1.0 / 1.0 20 µA / 0.6 mA

CP (74F374) Clock pulse input (active rising edge) 1.0 / 1.0 20 µA / 0.6 mA

Q0 - Q7 3-State outputs 150 / 40 3.0 mA / 24 mA

NOTE: One (1.0) FAST unit load is defined as: 20 µA in the HIGH state and 0.6 mA in the LOW state.

74F (U.L.)

HIGH / LOW

LOAD VALUE

HIGH/LOW

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Philips Semiconductors Product data

74F373/74F374Latch/flip-flop

PIN CONFIGURATION – 74F373

OE

1

Q0

2

D0

3

D1

4

Q1

5

Q2

6

D2

7

D3

8

Q3

9

GND

10 11

SF00250

LOGIC SYMBOL – 74F373

3 4 7 8 13 14 17 18

D0 D1 D2 D3 D4 D5 D6 D7

11

E
OE

1

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

PIN CONFIGURATION – 74F374

V

20

CC

19

Q7

18

D7

17

D6

16

Q6

15

Q5

14

D5

13

D4

12

Q4
E

OE

1

Q0

2

D0

3

D1

4

Q1

5

Q2

6

D2

7

D3

8

Q3

9

GND

10 11

V

20

Q7

19

D7

18

D6

17

Q6

16

Q5

15

D5

14

D4

13

Q4

12

CP

SF00253

CC

IEC/IEE SYMBOL – 74F374

3 4 7 8 13 14 17 18

D0 D1 D2 D3 D4 D5 D6 D7

11

CP
OE

1

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

= Pin 20

V

CC

GND = Pin 10

IEC/IEEE SYMBOL – 74F373

1
11

3
4
7
8
13
14
17
18

EN1
EN2

2D

2 5 6 9 12 15 16 19

V

= Pin 20

CC

SF00251

GND = Pin 10

SF00254

IEC/IEEE SYMBOL – 74F374

1

11

SF00252

2
5

6
9

12
15
16
19

13
14
17

18

1

EN1

C2

3
4
7
8

2D

1

2
5

6
9
12
15
16
19

SF00255

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Philips Semiconductors Product data

OPERATING MODE

Enable and read register

Latch and read register

Disable outputs

74F373/74F374Latch/flip-flop

LOGIC DIAGRAM FOR 74F373

D0

3

D1

4

D2

7

D3

8

D4

13

D5

14

D6

17

D7

18

V

= Pin 20

CC

GND = Pin 10

OE

Q0

D

Q

E

2

D

Q

E

11

E

1

Q1

D

Q

E

5

Q2

D

Q

E

6

Q3

D

E

9

D

Q

E

12

Q4

LOGIC DIAGRAM FOR 74F374

VCC = Pin 20
GND = Pin 10

CP

OE

D0

3

D
CP

11

1

D1

4

Q0

D
CP

2

Q

D2

7

Q1

D
CP

5

Q

D3

8

Q2

D
CP

6

Q

D4

13

Q

9

Q3

D
CP

D5

14

D

Q

CP

12

Q4

FUNCTION TABLE FOR 74F373

INPUTS

OE E Dn

INTERNAL

REGISTER

L H L L L
L H H H H
L ↓ l L L
L ↓ h H H

L L X NC NC Hold
H L X NC Z
H H Dn Dn Z

NOTES:

H = High-voltage level
h = HIGH state must be present one set-up time before the HIGH-to-LOW enable transition
L = Low-voltage level
l = LOW state must be present one set-up time before the HIGH-to-LOW enable transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↓ = HIGH-to-LOW enable transition

OUTPUTS

Q0 - Q7

Q5

Q5

D

E

15

D6

17

D
CP

15

Q

Q

D

Q

Q

Q6

Q6

Q

E

16

D7

18

D
CP

16

19

Q7

SF00256

Q

19

Q7

SF00257

p

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Philips Semiconductors Product data

OPERATING MODE

Load and read register

Disable outputs

SYMBOL

PARAMETER

UNIT

74F373/74F374Latch/flip-flop

FUNCTION TABLE FOR 74F374

INPUTS INTERNAL OUTPUTS

OE CP Dn REGISTER Q0 – Q7

L ↑ l L L

L ↑ h H H

L ↑ X NC NC Hold
H ↑ X NC Z
H ↑ Dn Dn Z

NOTES:

H = High-voltage level
h = HIGH state must be present one set-up time before the LOW-to-HIGH clock transition
L = Low-voltage level
l = LOW state must be present one set-up time before the LOW-to-HIGH clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = LOW-to-HIGH clock transition

= Not LOW-to-HIGH clock transition

↑

p

ABSOLUTE MAXIMUM RATINGS

Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.

SYMBOL

V

CC

V

IN

I

IN

V

OUT

I

OUT

T

amb

T

stg

Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5 mA
Voltage applied to output in HIGH output state –0.5 to V
Current applied to output in LOW output state 48 mA
Operating free air temperature range 0 to +70 °C
Storage temperature range –65 to +150 °C

PARAMETER RATING UNIT

RECOMMENDED OPERATING CONDITIONS

V
V
V
I
I
I
T

CC
IH

IL
Ik
OH
OL

amb

Supply voltage
HIGH-level input voltage 2.0 – – V
LOW-level input voltage – – 0.8 V
Input clamp current – – –18 mA
HIGH-level output current – – –3 mA
LOW-level output current – – 24 mA
Operating free air temperature range 0 – +70 °C

CC

LIMITS

MIN NOM MAX

4.5 5.0 5.5 V

V

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Philips Semiconductors Product data

SYMBOL

PARAMETER

UNIT

VOHHIGH-level output voltage

CC

,

IL

,

VOLLOW-level output voltage

CC

,

IL

,

74F373/74F374Latch/flip-flop

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

LIMITS

MIN TYP2MAX

2.4 V

2.7 3.4 V

0.35 0.50 V

0.35 0.50 V

–0.73 –1.2 V

35 60 mA

V
I

I

I

IH

I

IL

I

OZH

I

OZL

I

OS

I

CC

TEST

CONDITIONS

p

p

IK

Input clamp voltage VCC = MIN, II = I

VCC = MIN, VIL = MAX,
VIH = MIN, IOH = MAX

VCC = MIN, VIL = MAX,
VIH = MIN, IOL = MAX

IK

Input current at maximum input voltage VCC = MAX, VI = 7.0 V 100 µA
High-level input current VCC = MAX, VI = 2.7 V 20 µA
Low-level input current VCC = MAX, VI = 0.5 V –0.6 mA
Off-state output current, high-level voltage applied VCC = MAX, V

= 2.7 V 50 µA

O

Off-state output current, low-level voltage applied VCC = MAX, VO = 0.5 V –50 µA
Short-circuit output current
Supply current (total)

3

74F373

VCC = MAX –60 –150 mA
VCC = MAX

1

±10%V

±5%V

±10%V

±5%V

CC

CC

CC

CC

74F374 57 86 mA

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

3. Not more than one output should be shorted at a time. For testing I

= 5 V, T

CC

techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting

amb

= 25 °C.

, the use of high-speed test apparatus and/or sample-and-hold

OS

of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.

AC ELECTRICAL CHARACTERISTICS

LIMITS

T

= +25 °C T

amb

SYMBOL PARAMETER TEST VCC = +5.0 V VCC = +5.0 V ± 10% UNIT

CONDITION CL = 50 pF; RL = 500 Ω CL = 50 pF; RL = 500 Ω

MIN TYP MAX MIN MAX

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

f

max

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

Propagation delay
Dn to Qn

Propagation delay
E to Qn

Output enable time
to HIGH or LOW level

Output disable time
from HIGH or LOW level

Maximum clock frequency
Propagation delay

CP to Qn
Output enable time

to HIGH or LOW level
Output disable time

from HIGH or LOW level

Waveform 3

74F373

Waveform 2
Waveform 6

Waveform 7
Waveform 6

Waveform 7

74F374

Waveform 1 150 165 140 ns

Waveform 1

Waveform 6

Waveform 7

Waveform 6

Waveform 7

3.0

2.0

5.0

3.0

2.0

2.0

2.0

2.0

3.5

3.5

2.0

2.0

2.0

2.0

5.3

3.7

9.0

4.0

5.0

5.6

4.5

3.8

5.0

5.0

9.0

5.3

5.3

4.3

7.0

5.0

11.5

7.0

11.0

7.5

6.5

5.0

7.5

7.5

11.0

7.5

6.0

5.5

= 0 °C to +70 °C

amb

3.0

2.0

5.0

3.0

2.0

2.0

2.0

2.0

3.0

3.0

2.0

2.0

2.0

2.0

8.0

6.0

12.0

8.0

11.5

8.5

7.0

6.0

8.5

8.5

12.0

8.5

7.0

6.5

ns

ns

ns

ns

ns

ns

ns

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Philips Semiconductors Product data

74F373/74F374Latch/flip-flop

AC SET-UP REQUIREMENTS

LIMITS

T

= +25 °C T

amb

SYMBOL PARAMETER TEST VCC = +5.0 V

CONDITION CL = 50 pF, RL = 500 Ω CL = 50 pF, RL = 500 Ω

MIN TYP MAX MIN MAX

t

(H)

su

t

(L)

su

t

(H)

h

t

(L)

h

t

(H) E Pulse width, HIGH Waveform 1 3.5 4.0 ns

w

t

(H)

su

t

(L)

su

t

(H)

h

t

(L)

h

t

(H)

w

t

(L)

w

Set-up time, HIGH or LOW level
Dn to E

Hold time, HIGH or LOW level
Dn to E

Set-up time, HIGH or LOW level

Dn to CP
Hold time, HIGH or LOW level

Dn to CP
CP Pulse width,

HIGH or LOW

74F373

74F374

Waveform 4

Waveform 4

Waveform 5

Waveform 5

Waveform 5

0

1.0

3.0

3.0

2.0

2.0
0

0

3.5

4.0

= 0 °C to +70 °C

amb

VCC = +5.0 V ± 10%

0

1.0

3.0

3.0

2.0

2.0
0

0

3.5

4.0

UNIT

ns

ns

ns

ns

ns

AC WAVEFORMS

For all waveforms, VM = 1.5 V.
The shaded areas indicate when the input is permitted to change for
predictable output performance.

1/f

max

CP

V

M

Qn

tw(H)

PLH

Waveform 1. Propagation delay for clock input to output,

clock pulse widths, and maximum clock frequency

tw(H)

EV

M

t

PHL

Qn

Waveform 2. Propagation delay for enable to output

V

M

tw(L)t

V

M

V

M

V

M

and enable pulse width

V

V

t

M

t

PHL

M

PLH

V

M

SF00258

V

M

SF00259

Dn

Qn

V

M

t

PLH

V

M

t

PHL

V

V

M

M

Waveform 3. Propagation delay for data to output

Dn

E

V

M

(H) th(H)

t

su

V

M

V

M

V

M

tsu(L) th(L)

Waveform 4. Data set-up time and hold times

SF00260

V

V

M

M

SF00261

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Philips Semiconductors Product data

74F373/74F374Latch/flip-flop

AC WAVEFORMS

(continued)

For all waveforms, VM = 1.5 V.
The shaded areas indicate when the input is permitted to change for
predictable output performance.

Dn

CP

V

M

t

(H) th(H)

su

V

M

V

M

V

tsu(L) th(L)

V

M

V

M

M

SF00262

Waveform 5. Data set-up time and hold times

OEn

Qn, Qn

V

t

PZH

M

V

M

t

PHZ

V

M

VOH -0.3V

0V

SF00263

Waveform 6. 3-State output enable time to HIGH level

and output disable time from HIGH level

OEn

Qn, Q

n

V

t

PZL

M

V

V

M

t

PLZ

M

VOL +0.3V

SF00264

Waveform 7. 3-State output enable time to LOW level

and output disable time from LOW level

TEST CIRCUIT AND WAVEFORMS

SWITCH POSITION

TEST SWITCH

, t

t

PLZ

PZL

closed

openAll other

V

PULSE

GENERATOR

IN

Test circuit for 3-state outputs

DEFINITIONS:

R

Load resistor; see AC electrical characteristics for value.

L =

C

Load capacitance includes jig and probe capacitance;

L =

see AC electrical characteristics for value.
Termination resistance should be equal to Z

R

T =

generators.

V

CC

V

D.U.T.

R

T

OUT

t

7.0V

NEGATIVE
PULSE

R

L

R

C

L

L

POSITIVE
PULSE

90%

10%

V

M

10%

t

THL (tf

t

TLH (tr

90%

V

M

w

V

M

10%

)

)

t

w

t

TLH (tr

t

THL (tf

)

)

90%

V

M

90%

10%

AMP (V)

0V

AMP (V)

0V

Input pulse definition

INPUT PULSE REQUIREMENTS

V

1.5V

rep. rate

M

1MHz 500ns 2.5ns

amplitude

3.0V

t

w

t

TLHtTHL

2.5ns

SF00265

OUT

of pulse

family

74F

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Philips Semiconductors Product data

74F373/74F374Latch/flip-flop

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

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Philips Semiconductors Product data

74F373/74F374Latch/flip-flop

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

2002 Nov 20

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Philips Semiconductors Product data

74F373/74F374Latch/flip-flop

SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1

2002 Nov 20

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Philips Semiconductors Product data

74F373/74F374Latch/flip-flop

REVISION HISTORY

Rev Date Description

_3 20021 120 Product data; third version (9397 750 10758). Supersedes 74F373_374_2 dated 1994 Dec 05

_2 19941205 Product data; second version (9397 750 05119).

(9397 750 05119).

Engineering Change Notice 853–0369 29206 (date: 20021115).

Modifications:

•Corrected ordering information table (from ‘N74374DB’ to ‘74F374DB’).

•Add SSOP20 (SOT339-1) package outline drawing.

Engineering Change Notice 853–0369 14383 (date: 19941205).

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Philips Semiconductors Product data

74F373/74F374Latch/flip-flop

Data sheet status

Level

I

Data sheet status

Objective data

[1]

Product

[2] [3]

status

Development

Definitions

This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.

II

III

[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Preliminary data

Product data

http://www.semiconductors.philips.com.

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notification (CPCN).

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see

the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be

expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.

Contact information

For additional information please visit
http://www.semiconductors.philips.com . Fax: [phone]

For sales offices addresses send e-mail to:
[email protected].

Document order number: 9397 750 10758

 Koninklijke Philips Electronics N.V. 2002

All rights reserved. Printed in U.S.A.

Date of release: 11-02

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