Datasheet 74f350 DATASHEETS (Philips)

Philips Semiconductors FAST Products Product specification

74F3504-bit shifter

1

March 20, 1989 853–0368 96093

FEATURES

•Shifts 4 bits of data to 0, 1, 2, 3 places under control of two

select lines

•3-State outputs for bus organized systems

DESCRIPTION

The 74F350 is a combination logic circuit that shifts a 4-bit word from 0 to 3 places. No clocking is required as with shift registers. The 74F350 can be used to shift any number of bits any number of places up or down by suitable interconnection. Shifting can be:

1. Logical — with logic zeros filled in at either end of the shifting field.

2. Arithmetic — where the sign bit is extended during a shift down.

3. End around — where the data word forms a continuous loop.

The 3-State outputs are useful for bus interface applications or expansion to a larger number of shift positions in end around shifting. The active Low Output Enable (OE

) controls the state of the outputs. The outputs are in the high impedance “off” state when OE is High, and they are active when OE is Low.

PIN CONFIGURATION

16 15 14 13 12 11 107

6

5

4

3

2

1

I3

V

CC

Y2 Y3 S0

OE

Y0 Y1

I–3 I–2

I2

I–1

I0 I1

98GND S1

SF00205

ORDERING INFORMA TION

DESCRIPTION

COMMERCIAL RANGE

V

CC

= 5V ±10%, T

amb

= 0°C to +70°C

16-pin plastic DIP N74F350N

16-pin plastic SO N74F350D

TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL)

74F350 5.2ns 24mA

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW

I–n, In Data inputs 1.0/2.0 20µA/1.2mA

S0, S1 Select inputs (active Low) 1.0/2.0 20µA/1.2mA

OE Output Enable input (active Low) 1.0/2.0 20µA/1.2mA

Y0 – Y3 Data outputs 150/40 3.0mA/24mA

NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

LOGIC SYMBOL

VCC = Pin 16 GND = Pin 8

SF00206

9 10 13

S1 S0 OE

1 2 3 4 5 6 7

I–3 I–2 I–1 I0 I1 I2 I3

Y0 Y1 Y2 Y3

15 14 12 11

IEC/IEEE SYMBOL

SF00207

0

9

10

D MUX

13

G

0 3

[

SHIFTER

]

1 EN

≥1

15

10 3 11 2 12 1 13 0

≥1

14

11 3 12 2 13 1 14 0

≥1

12

12 3 13 2 14 1 15 0

≥1

11

13 3 14 2 15 1 16 0

Z10

1

Z11

2

Z12

3

Z13

4

Z14

5

Z15

6

Z16

7

Philips Semiconductors FAST Products Product specification

74F3504-bit shifter

March 20, 1989

2

LOGIC DIAGRAM

139 10

V

CC

= Pin 16

GND = Pin 8

OE

S1 S0

SF00208

1

I–3

Y0

15

2

I–2

Y1

14

3

I–1

Y2

12

4

I0

Y3

11

5I16I27

I3

OUTPUTS

OE S1 S0 I3 I2 I1 I0 I–1 I–2 I–3 Y3 Y2 Y1 Y0

H X X X X X X X X X Z Z Z Z

L L L D3 D2 D1 D0 X X X D3 D2 D1 D0 L L H X D2 D1 D0 D–1 X X D2 D1 D0 D–1 L H L X X D1 D0 D–1 D–2 X D1 D0 D–1 D–2 L H H X X X D0 D–1 D–2 D–3 D0 D–1 D–2 D–3

H = High voltage level L = Low voltage level X = Don’t care Z = High impedance “off” state Dn = High or Low state of referenced In input

FUNCTION TABLE

INPUTS

Philips Semiconductors FAST Products Product specification

74F3504-bit shifter

March 20, 1989

3

APPLICATION FOR 16-BIT SHIFT UP 0, 1, 2, OR 3 PLACES

GND

S0 S1

OE

S0 S1 OE

I-3 I-2 I-1 I0 I1 I2 I3

Y0 Y1 Y2 Y3

S0 S1 OE

I-3 I-2 I-1 I0 I1 I2 I3

Y0 Y1 Y2 Y3

S0 S1 OE

I-3 I-2 I-1 I0 I1 I2 I3

Y0 Y1 Y2 Y3

S0 S1 OE

I-3 I-2 I-1 I0 I1 I2 I3

Y0 Y1 Y2 Y3

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

S0 S1 MODE

L L No shift H L Shift 1 place L H Shift 2 places H H Shift 3 places

SF00209

APPLICATION FOR 8-BIT END AROUND SHIFT 0, 1, 2, 3, 4, 5, 6, OR 7 PLACES

S0 S1 S2

S0 S1 OE

I-3 I-2 I-1 I0 I1 I2 I3

Y0 Y1 Y2 Y3

S0 S1 OE

I-3 I-2 I-1 I0 I1 I2 I3

Y0 Y1 Y2 Y3

S0 S1 OE

I-3 I-2 I-1 I0 I1 I2 I3

Y0 Y1 Y2 Y3

S0 S1 OE

I-3 I-2 I-1 I0 I1 I2 I3

Y0 Y1 Y2 Y3

0 1 2 3 4 5 6 7

S2 S1 S0 MODE

L L L No shift L L H Shift end around 1 L H L Shift end around 2 L H H Shift end around 3 H L L Shift end around 4 H L H Shift end around 5 H H L Shift end around 6 H H H Shift end around 7

SF00210

S3

0 1 2 3 4 5 6 7

Philips Semiconductors FAST Products Product specification

74F3504-bit shifter

March 20, 1989

4

APPLICATION FOR 13-BIT TWO’S COMPLEMENT SCALER

S0 S1

S0 S1 OE

I-3 I-2 I-1 I0 I1 I2 I3

Y0 Y1 Y2 Y3

S0 S1 OE

I-3 I-2 I-1 I0 I1 I2 I3

Y0 Y1 Y2 Y3

S0 S1 OE

I-3 I-2 I-1 I0 I1 I2 I3

Y0 Y1 Y2 Y3

9 5 1

12 11 10 9 8 7 6 5 4 3 2 1

S1 S0 SCALE

L L

÷8 1/8

L H

÷4 1/4

H L ÷2 1/2 H H No change 1

SF00211

12 11 10

0

2348 7 6 0

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)

SYMBOL

PARAMETER RATING UNIT

V

CC

Supply voltage –0.5 to +7.0 V

V

IN

Input voltage –0.5 to +7.0 V

I

IN

Input current –30 to +5 mA

V

OUT

Voltage applied to output in High output state –0.5 to V

CC

V

I

OUT

Current applied to output in Low output state 48 mA

T

amb

Operating free-air temperature range 0 to +70 °C

T

stg

Storage temperature range –65 to +150 °C

RECOMMENDED OPERATING CONDITIONS

LIMITS

SYMBOL

PARAMETER

MIN NOM MAX

UNIT

V

CC

Supply voltage 4.5 5.0 5.5 V

V

IH

High-level input voltage 2.0 V

V

IL

Low-level input voltage 0.8 V

I

IK

Input clamp current –18 mA

I

OH

High-level output current –3 mA

I

OL

Low-level output current 24 mA

T

amb

Operating free-air temperature range 0 +70 °C

Philips Semiconductors FAST Products Product specification

74F3504-bit shifter

March 20, 1989

5

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

1

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

1

MIN TYP

2

MAX

UNIT

VCC = MIN, VIL = MAX ±10%V

CC

2.4

VOHHigh-level output voltage

VIH = MIN, IOH = MAX ±5%V

CC

2.7 3.4

V

VCC = MIN, VIL = MAX ±10%V

CC

0.35 0.50

VOLLow-level output voltage

VIH = MIN, IOL = MAX ±5%V

CC

0.35 0.50

V

IK

Input clamp voltage VCC = MIN, II = I

IK

–0.73 –1.2 V

I

Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA

I

IH

High-level input current VCC = MAX, VI = 2.7V 20 µA

I

IL

Low-level input current VCC = MAX, VI = 0.5V –1.2 mA

I

OZH

Off-state output current, High-level voltage applied

VCC = MAX, VO = 2.7V 50 µA

I

OZL

Off-state output current, Low-level voltage applied

VCC = MAX, VO = 0.5V –50 µA

I

OS

Short-circuit output current

3

VCC = MAX –60 –150 mA

I

CCH

22 35 mA

I

CCL

26 41 mA

I

CCZ

26 42 mA

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

CC

= 5V, T

amb

= 25°C.

3. Not more than one output should be shorted at a time. For testing I

OS

, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I

OS

tests should be performed last.

AC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL

PARAMETER

TEST

CONDITION

VCC = +5.0V

T

amb

= +25°C

CL = 50pF, RL = 500Ω

VCC = +5.0V ± 10%

T

amb

= 0°C to +70°C

CL = 50pF, RL = 500Ω

UNIT

MIN TYP MAX MIN MAX

t

PLH

t

PHL

Propagation delay In to Yn

Waveform 1

3.0

2.5

4.5

4.0

6.0

5.5

3.0

2.5

7.0

6.5

ns

t

PLH

t

PHL

Propagation delay Sn to Yn

Waveform 1

4.0

3.0

7.8

6.5

10.0

8.5

4.0

3.0

11.0

9.5

ns

t

PZH

t

PZL

Output Enable time to High or Low level

Waveform 2 Waveform 3

2.5

4.0

5.0

7.0

9.0

2.5

4.0

8.0

10.0

ns

t

PHZ

t

PLZ

Output Disable time to High or Low level

Waveform 2 Waveform 3

2.0

3.9

4.0

5.5

2.0

6.5

ns

I

CC

Supply current (total)

VCC = MAX

Philips Semiconductors FAST Products Product specification

74F3504-bit shifter

March 20, 1989

6

AC WAVEFORMS

For all waveforms, VM = 1.5V.

V

M

V

M

V

M

V

M

Yn

In, I–n, Sn

t

PLH

t

PHL

SF00212

Waveform 1. Propagation Delay Data and Select to Output

VOH–0.3V

V

M

V

M

V

M

Yn

t

PZH

t

PHZ

SF00213

OE

0V

Waveform 2. 3-State Output Enable Time to High Level

and Output Disable Time from High Level

VOL+0.3V

V

M

V

M

V

M

Yn

t

PZL

t

PLZ

SF00214

OE

Waveform 3. 3-State Output Enable Time to Low Level

and Output Disable Time from Low Level

TEST CIRCUIT AND WAVEFORMS

t

w

90%

V

M

10%

90%

V

M

10%

90%

V

M

10%

90%

V

M

10%

NEGATIVE PULSE

POSITIVE PULSE

t

w

AMP (V)

0V

t

THL (tf

)

INPUT PULSE REQUIREMENTS

rep. rate

t

w

t

TLH

t

THL

1MHz 500ns

2.5ns 2.5ns

Input Pulse Definition

V

CC

family

74F

D.U.T.

PULSE

GENERATOR

R

L

C

L

R

T

V

IN

V

OUT

Test Circuit for Open Collector Outputs

DEFINITIONS:

RL= Load resistor;

see AC electrical characteristics for value.

CL= Load capacitance includes jig and probe capacitance;

see AC electrical characteristics for value.

R

T

= Termination resistance should be equal to Z

OUT

of

pulse generators.

t

THL (tf

)

t

TLH (tr

)

t

TLH (tr

)

AMP (V)

amplitude

3.0V

1.5V

V

M

R

L

7.0V

SF00128

TEST SWITCH

t

PLZ

closed

t

PZL

closed

All other open

SWITCH POSITION