Datasheet 74f299 DATASHEETS (Philips)

INTEGRATED CIRCUITS

74F299

8-bit universal shift/storage register (3-State)

Product specification IC15 Data Handbook

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1990 Mar 01

Philips Semiconductors Product specification

I/On

74F2998-bit universal shift/storage register (3-State)

FEA TURES

•Common parallel I/O for reduced pin count

•Additional serial inputs and outputs for expansion

•Four operating modes: Shift left, shift right, load and store

•3-State outputs for bus-oriented applications

DESCRIPTION

The 74F299 is an 8-bit universal shift/storage register with 3-State outputs. Four modes of operation are possible: Hold (store), shift left, shift right and parallel load. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0 and Q7 to allow easy serial cascading. A separate active-Low Master Reset is used to reset the register.

The 74F299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Function Table. All flip-flop outputs are brought out through 3-State buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words.

A Low signal on MR the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of clock are observed.

A High signal on either OE puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-State buffers are also disabled by High signals on both S0 and S1 in preparation for a parallel load operation.

overrides the Select and CP inputs and resets

0 or OE1 disables the 3-State buffers and

PIN CONFIGURATION

1

S0

0

2

OE

1

OE

3 4

I/O6

5

I/O4

6

I/O2

7

I/O0

8

Q0

MR

9

GND

10 11

TYPE TYPICAL f

MAX

74F299 115MHz 58mA

20

V

CC

S1

19

DS7

18

Q7

17

I/O7

16

I/O5

15

I/O3

14

I/O1

13

CP

12

DS0

SF00865

TYPICAL

SUPPLY CURRENT

(TOTAL)

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

20-pin plastic DIP N74F299N SOT146-1

20-pin plastic SOL N74F299D SOT163-1

20-pin plastic SSOP II N74F299DB SOT339-1

COMMERCIAL

RANGE

= 5V ±10%,

V

CC

T

= 0°C to +70°C

amb

PKG DWG #

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION

74F(U.L.)

HIGH/LOW

DS0 Serial data input for right shift 1.0/1.0 20µA/0.6mA DS7 Serial data input for left shift 1.0/1.0 20µA/0.6mA S0, S1 Mode select inputs 1.0/2.0 20µA/1.2mA CP Clock pulse input (Active rising edge) 1.0/1.0 20µA/0.6mA MR Asynchronous Master Reset input (Active Low) 1.0/1.0 20µA/0.6mA OE0, OE1 Output Enable input (Active Low) 1.0/1.0 20µA/0.6mA Q0, Q7 Serial outputs 50/33 1.0mA/20mA

Multiplexed parallel data inputs or 3.5/1.0 70µA/0.6mA 3-State parallel outputs 150/40 3.0mA/24mA

NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High State and 0.6mA in the Low state.

1990 Mar 01 853-0365 98989

2

LOAD VALUE

HIGH/LOW

Philips Semiconductors Product specification

OPERATING MODE

74F2998-bit universal shift/storage register (3-State)

LOGIC SYMBOL

1 19 12

9

2

3

V

= Pin 20

CC

GND = Pin 10

S0 S1 CP

MR

OE0 OE1

Q0 Q7

8 17

11 18

DS0 DS7

I/00 I/O2 I/O4 I/O6I/O1 I/O3 I/O5 I/O7

713614515416

SF00866

LOGIC SYMBOL (IEEE/IEC)

4R &

0

M

1

C4/1→ /2←

1, 4D 3, 4D

5, 13

3, 4D

6, 13

3, 4D

12, 13

2, 4D

SRG8

EN13

3

0 3

9 2

3

1 19 12

11

7

13

6 14

5 15

4

16

18

Z5

Z6Z6

Z12

FUNCTION TABLE

INPUTS INPUTS

OEn MR S1 S0 CP

L L X X X Asynchronous Reset; Q0 - Q7 = Low L H H H ↑ Parallel load; I/On → Qn (I/On outputs disabled) L H L H ↑ Shift right; DS0 → Q0, Q0 → Q1, etc. L H H L ↑ Shift left; DS7 → Q7, Q7 → Q6, etc. L H L L X Hold

H X X X X Outputs in High Z

H = High voltage level L = Low voltage level X = Don’t care ↑ = Low-to-High clock transition

8

17

SF00890

1990 Mar 01

3

Philips Semiconductors Product specification

74F2998-bit universal shift/storage register (3-State)

LOGIC DIAGRAM

18

DS7

OE OE1

2

0

3

19

S1

1

S0

CP D

Q

R

D

Q

R

D

Q

R

D

17

Q7

16

I/O7

4

I/O6

15

I/O5

VCC = Pin 20 GND = Pin 10

DS0

CP

MR

CP D

Q

R

D

CP D

Q

R

D

CP D

Q

R

D

CP D

Q

R

D

CP D

Q

R

11

12

9

D

5

I/O4

14

I/O3

6

I/O2

13

I/O1

7

I/O0

8

Q0

SF00868

1990 Mar 01

4

Philips Semiconductors Product specification

I

Current applied to output in Low output state

IOHHigh-level output current

IOLLow-level output current

74F2998-bit universal shift/storage register (3-State)

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)

SYMBOL PARAMETER RATING UNIT

V

CC

V

IN

I

IN

V

OUT

T

amb

T

stg

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT

V

CC

V

IH

V

IL

I

IK

T

amb

Supply voltage –0.5 to +7.0 V Input voltage –0.5 to +7.0 V Input current –30 to +5 mA Voltage applied to output in High output state –0.5 to +V

pp

p

Q0, Q7 40 mA

I/On 48 mA

CC

V

Operating free-air temperature range 0 to +70 °C Storage temperature –65 to +150 °C

MIN NOM MAX

Supply voltage 4.5 5.0 5.5 V High-level input voltage 2.0 V Low-level input voltage 0.8 V Input clamp current –18 mA

p

Q0, Q7 –1 mA

I/On –3 mA

Q0, Q7 20 mA

I/On 24 mA

Operating free-air temperature range 0 70 °C

1990 Mar 01

5

Philips Semiconductors Product specification

NO TAG

Q0, Q7

I

1mA

VOHHigh-level output voltage

V

MAX

I/On

IH

I

3mA

VOLLow-level output voltage

V

MAX

I

MAX

In ut current at

IILLow-level input current

V

MAX, V

5V

74F2998-bit universal shift/storage register (3-State)

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

LIMITS

SYMBOL PARAMETER TEST CONDITIONS

= –

p

IL

V

=

= MIN

IH

VCC = MIN,

OH

,

= –

OH

VCC = MIN,

p

V

IK

I

Input clamp voltage VCC = MIN, II = I Input current at

maximum input voltage

others VCC = MAX, VI = 7.0V 100 µA

I/On VCC = 5.5V, VI = 5.5V 1 mA

=

IL

VIH = MIN

,

OL

=

IK

±10%V

±5%V

±10%V

±5%V

±10%V

±5%V

CC

MIN

2.5 V

2.7 3.4 V

2.4 V

2.7 3.3 V

TYP

NO TAG

MAX

0.35 0.50 V

–0.73 –1.2 V

except

I

IH

High-level input current

p

I/On

S0, S1

others

VCC = MAX, VI = 2.7V 20 µA

CC

=

= 0.

I

–1.2 mA –0.6 mA

Off-state output current, High-level voltage

I

I I

I

IH +

IL +

OS

CC

I

OZH

applied Off-state output current

I

OZL

Low-level voltage applied Short-circuit output current

Supply current (total) I

I/On only

NO TAG

I

CCH CCL

I

CCZ

VCC = MAX, VO = 2.7V 70 µA

VCC = MAX, VO = 0.5V –0.6 mA

VCC = MAX –60 –150 mA

55 60 mA

VCC = MAX 70 90 mA

65 95 mA

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

3. Not more than one output should be shorted at a time. For testing I

= 5V, T

CC

techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting

amb

= 25°C.

, the use of high-speed test apparatus and/or sample-and-hold

OS

of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I

tests should be performed last.

OS

UNIT

1990 Mar 01

6

Philips Semiconductors Product specification

f

Maximum clock frequenc

Waveform 1

74F2998-bit universal shift/storage register (3-State)

AC ELECTRICAL CHARACTERISTICS

LIMITS

T

SYMBOL PARAMETER TEST CONDITIONS

I/O

MAX

t

PLH

t

PHL

t

PLH

t

PHL

t

PHL

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

Propagation delay CP to Q0 or Q7

Propagation delay CP to I/On

Propagation delay MR to Q0 or Q7

Propagation delay MR to I/On

Output Enable time Sn, OE

to I/On

Output Disable time Sn, OE to I/On

y

Qn

Waveform 1

Waveform 2 5.5 7.5 9.5 5.5 10.5 ns

Waveform 2 5.5 7.5 10.0 5.5 10.5 ns Waveform 4

Waveform 5 Waveform 4

Waveform 5

= +25°C T

amb

VCC = +5.0V VCC = +5.0V ± 10%

CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω

MIN TYP MAX MIN MAX

70 100 70 MHz 85 115 85 MHz

4.0

4.5

4.0

3.5

4.0

2.5

1.5

5.0

6.0

6.5

6.0

7.5

4.5

2.5

7.5

8.0

9.0

8.0

10.0

7.0

5.5

= 0°C to +70°C

amb

3.5

4.5

4.0

3.5

4.0

2.5

1.5

8.5

10.0

9.0

11.0

8.0

6.5

UNIT

ns ns

AC SETUP REQUIREMENTS

LIMITS

T

= +25°C T

SYMBOL PARAMETER TEST CONDITIONS

amb

VCC = +5.0V VCC = +5.0V ± 10%

CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω

MIN TYP MAX MIN MAX

ts(H) ts(L)

th(H) th(L)

ts(H) t

(L)

s

th(H) th(L)

tw(H) tw(L)

Setup time, High or Low S0 or S1 to CP

Hold time, High or Low S0 or S1 to CP

Set-up time, High or Low I/On, DS

or DSR to CP

L

Hold time, High or Low I/On, DSL or DSR to CP

Waveform 3

CP Pulse width, High or Low Waveform 1

6.5

6.5 0

0

3.5

3.5 0

0

5.0

4.5

tw(L) MR Pulse width, Low Waveform 2 4.5 4.5 ns t

rec

Recovery time, MR to CP Waveform 2 4.0 4.0 ns

= 0°C to +70°C

amb

7.5

7.5 0

0

4.0

4.0 0

0

5.0

4.5

UNIT

ns ns

ns

1990 Mar 01

7

Philips Semiconductors Product specification

74F2998-bit universal shift/storage register (3-State)

AC WAVEFORMS

For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance.

1/f

MAX

Q0, Q7, I/On

CP

t

PHL

V

M

tW(H)

tW(L)

V

M

t

PLH

V

M

V

M

SF00869

Waveform 1. Propagation Delay, Clock Input to Output,

Clock Width, and Maximum Clock Frequency

S0, S1,

I/On

DSL,

DS

CP

R

VMV

M

ts(H) th(H) th(L)ts(L)

V

M

VMV

M

Waveform 3. Setup and Hold Times

V

M

SF00871

MR

CP

Q0, Q7, I/On

V

M

tW(L) t

t

PHL

V

M

REC

V

M

V

M

SF00870

Waveform 2. Master Reset Pulse Width, Master Reset to Output

Delay, and Master Reset to Clock Recovery Time

Sn, OEn

I/On

V

t

PZH

M

V

M

t

PHZ

V

M

VOH -0.3V

0V

SF00872

Waveform 4. 3-State Output Enable Time to High Level

and Output Disable Time from High Level

Sn, OEn

I/On

V

t

PZL

M

V

M

t

PLZ

M

+0.3V

V

OL

SF00873

Waveform 5. 3-State Output Enable Time to Low Level and

Output Disable Time from Low Level

1990 Mar 01

8

Philips Semiconductors Product specification

74F2998-bit universal shift/storage register (3-State)

TEST CIRCUIT AND WAVEFORM

V

PULSE

GENERATOR

IN

R

Test Circuit for 3-State Outputs

SWITCH POSITION

TEST SWITCH

t t

PLZ PZL

closed closed

All other open

T

D.U.T.

CC

V

OUT

7.0V

R

L

C

R

L

NEGATIVE PULSE

POSITIVE PULSE

90%

10%

V

M

10%

t

THL (tf

t

TLH (tr

90%

V

M

Input Pulse Definition

t

w

V

M

10%

)

t

)

TLH (tr

t

)

THL (tf

90%

V

M

t

w

90%

10%

AMP (V)

0V

AMP (V)

0V

DEFINITIONS:

= Load resistor;

R

L

see AC electrical characteristics for value.

C

= Load capacitance includes jig and probe capacitance;

L

see AC electrical characteristics for value.

R

= Termination resistance should be equal to Z

T

pulse generators.

OUT

of

family

74F

INPUT PULSE REQUIREMENTS

V

amplitude

3.0V

M

1.5V

rep. rate

1MHz 500ns

t

w

t

TLH

t

THL

2.5ns 2.5ns

SF00777

1990 Mar 01

9

Philips Semiconductors Product specification

8-bit universal shift/storage register (3-State)

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

74F299

1990 Mar 01

10

Philips Semiconductors Product specification

8-bit universal shift/storage register (3-State)

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

74F299

1990 Mar 01

11

Philips Semiconductors Product specification

8-bit universal shift/storage register (3-State)

SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1

74F299

1990 Mar 01

12

Philips Semiconductors Product specification

8-bit universal shift/storage register (3-State)

NOTES

74F299

1990 Mar 01

13

Philips Semiconductors Product specification

8-bit universal shift/storage register (3-State)

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

74F299

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 10-98 Document order number: 9397-750-05117

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yyyy mmm dd

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