Datasheet 74f273a DATASHEETS (Philips)

INTEGRATED CIRCUITS

74F273A

Octal D flip-flop

Product specification IC15 Data Handbook

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1996 Mar 12

Philips Semiconductors Product specification

74F273AOctal D flip–flop

FEA TURES

• High impedance inputs for reduced loading

µA in Low and High states)

(20

All outputs will be forced Low independently of Clock or Data inputs by a Low voltage level on the MR

input. The device is useful for applications where the true output only is required and the CP and MR

are common to all elements.

• Ideal buffer for MOS microprocessor or memory

• Eight edge–triggered D–type flip–flops

• Buffered common clock

• Buffered asynchronous Master Reset

TYPE

74F273A 170MHz 25mA

TYPICAL

f

MAX

TYPICAL SUPPL Y CURRENT

• See 74F377A for clock enable version

• See 74F373 for transparent latch version

• See 74F374 for 3–State version

DESCRIPTION

The 74F273 has eight edge–triggered D–type flip–flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR simultaneously .

The register is fully edge–triggered. The state of each D input, one setup time before the Low–to–High clock transition, is transferred to the corresponding flip–flop’s Q output.

) inputs load and reset (clear) all flip–flops

ORDERING INFORMATION

COMMERCIAL RANGE

V

PACKAGES

20–pin plastic DIP 74F273AN SOT146-1

20–pin plastic SOL 74F273AD SOT163-1

= 5V±10%;

CC

T

= 0°C to +70°C

amb

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION

D0 – D7 Data inputs 1.0/0.033 20µA/20µA

MR Master Reset input (active–Low) 1.0/0.033 20µA/20µA CP Clock pulse input (active rising edge) 1.0/0.033 20µA/20µA

Q0 – Q7 Data outputs 50/33 1.0mA/20mA

74F(U.L.)

HIGH/LOW

(TOTAL)

PKG. DWG. #

LOAD VALUE

HIGH/LOW

PIN CONFIGURATION

20 19 18 17 16 15 14 13 12

SF00346

V Q7 D7 D6 Q6 Q5 D5 D4

CP

CC

1

MR

2

Q0

3

D0

4

D1

5

Q1

6

Q2

7

D2

8

D3

9

Q3 Q4

10 11

GND

1996 Mar 12 853–0066 16555

LOGIC SYMBOL

11

1

V

= Pin 20

CC

GND = Pin 10

2

3 4 7 8 13 14 1817

D0 D1 D2 D3 D4 D5 D6 D7

CP MR

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

SF00347

Philips Semiconductors Product specification

74F273AOctal D flip–flop

LOGIC SYMBOL (IEEE/IEC)

1 11

32 4

7 8 13 14 17 18

LOGIC DIAGRAM

D0

11

CP

R

C1

1D

D1

3

Q

D

CP

R

D

4

D

CP

R

Q

D

5 6 9 12 15 16 19

SF00348

D2

7

D

CP

R

D

D3

8

Q

D

CP

R

D

D4

13

Q

D

CP

R

D

D5

14

Q

D

CP

R

D

D6

17

Q

D

CP

R

D

D7

18

Q

D

CP

R

D

1

MR

VCC = Pin 20 GND = Pin 10

2

Q0

Q1

5

Q2

6

9

Q3

FUNCTION TABLE

INPUTS OUTPUTS OPERATING

MR CP Dn Q0 – Q7 MODE

L X X L Reset (clear) H ↑ h H Load ”1” H ↑ l L Load ”0”

H = High voltage level h = High voltage level one set–up time prior to the Low–to–High clock transition L = Low voltage level l = Low voltage level one set–up time prior to the Low–to–High clock transition X = Don’t care ↑ = Low–to–High clock transition

Q4

12

Q5

15

Q6

16

19

Q7

SF00349

1996 Mar 12

3

Philips Semiconductors Product specification

74F273AOctal D flip–flop

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.)

SYMBOL

V

T

V

I

OUT

I

OUT

amb

T

CC

IN

stg

Supply voltage –0.5 to +7.0 V Input voltage –0.5 to +7.0 V Input current –30 to +5 mA

Voltage applied to output in High output state –0.5 to V Current applied to output in Low output state 40 mA Operating free air temperature range 0 to +70

Storage temperature range –65 to +150

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT

V

T

CC

V V

I

OH

I

OL

amb

IH IL

Ik

Supply voltage 4.5 5.0 5.5 V High–level input voltage 2.0 V Low–level input voltage 0.8 V Input clamp current –18 mA High–level output current –1 mA Low–level output current 20 mA Operating free air temperature range 0 +70

PARAMETER RATING UNIT

CC

V

°C °C

MIN TYP MAX

°C

1996 Mar 12

4

Philips Semiconductors Product specification

74F273AOctal D flip–flop

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

SYMBOL

V

OH

V

OL

V

IK

I

IH

I

IL

I

OS

I

CC

High-level output voltage inputs VIH = 4.5V3, IOH = MAX ±5%V

Low-level output voltage VCC = MIN, VIL = MAX, ±10%V

Input clamp voltage VCC = MIN, II = I Input current at maximum input voltage VCC = 0.0V, VI = 7.0V 100 µA High–level input current VCC = MAX, VI = 2.7V 20 µA Low–level input current VCC = MAX, VI = 0.5V –20 µA

Short–circuit output current Supply current (total) I

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

3. To reduce the effect of external noise during test.

4. Not more than one output should be shorted at a time. For testing I techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.

PARAMETER TEST LIMITS UNIT

1

CC

MIN TYP2MAX

2.5 V

CC

2.7 3.4 V

CC

2.5 V

CC

2.7 3.4 V

CC CC

0.30 0.50 V

–0.73 -1.2 V

27 43 mA

= 5V, T

CC

amb

4

= 25°C.

CONDITIONS

MR & CP VCC = MIN, VIL = 0.0V3, ±10%V

other VCC = MIN, VIL = MAX, ±10%V inputs VIH = MIN, IOH = MAX ±5%V

VIH = MIN, IOH = MAX ±5%V

IK

VCC = MAX -60 -150 mA

CCH

I

CCL

VCC = MAX 24 38 mA

, the use of high-speed test apparatus and/or sample-and-hold

OS

AC CHARACTERISTICS FOR ’F273A

SYMBOL PARAMETER WAVEFORM

f

MAX

t

PLH

t

PHL

t

PHL

Maximum clock frequency 1 150 170 125 MHz Propagation delay

CP to Qn Propagation delay

MR to Qn

1

2 5.0 7.0 9.0 5.0 9.5 ns

LIMITS

T

= +25°C

amb

VCC = +5.0V

CL = 50pF RL = 500Ω

T

= 0°C to +70°C

amb

VCC = +5.0V ±10%

CL = 50pF

RL = 500Ω

Min Typ Max Min Max

3.5

5.0

7.0

8.0

9.5

3.0

4.5

9.0

10.0

UNIT

ns

1996 Mar 12

5

Philips Semiconductors Product specification

74F273AOctal D flip–flop

AC SETUP REQUIREMENTS FOR ’F273A

LIMITS

T

= +25°C

amb

V

= +5.0V

SYMBOL PARAMETER WAVEFORM

CC

CL = 50pF RL = 500Ω

Min Typ Max Min Max

ts(H)

ts(L)

th(H)

th(L)

tw(H)

tw(L)

Setup time, High or Low Dn to CP

Hold time, High or Low Dn to CP

Clock pulse width High or Low

3

1

3.0

2.0

0.5

0.0

4.5

3.5

tw(L) Master Reset pulse width, Low 2 3.0 3.5 ns

t

REC

Recovery time MR to CP

2 4.0 5.0 ns

T

= 0°C to +70°C

amb

V

= +5.0V ±10%

CC

CL = 50pF

RL = 500Ω

2.5

1.0

5.0

4.0

UNIT

ns

AC WAVEFORMS

1/f

max

CP

Qn

V

M

tw(H)

PHL

V

M

tw(L)t

V

M

Waveform 1. Propagation Delay, Clock Input to Output, Clock

Pulse Width, and Maximum Clock Frequency

MR

CP

Qn

V

M

tw(L)

t

PHL

V

M

Waveform 2. Master Reset Pulse Width, Master Reset to Output

Delay and Master Reset to Clock Recovery Time

V

M

t

PLH

V

M

SF00294

V

M

t

REC

V

M

SF00158

Dn

CP

V

M

th(H)ts(H)

V

M

V

M

th(L)ts(L)

V

M

SF00191

Waveform 3. Data Setup and Hold Times

NOTE: For all waveforms, VM = 1.5V.

The shaded areas indicate when the input is permitted to change for predictable output performance.

1996 Mar 12

6

Philips Semiconductors Product specification

74F273AOctal D flip–flop

TEST CIRCUIT AND WAVEFORMS

V

CC

PULSE

GENERATOR

V

IN

R

T

D.U.T.

V

OUT

Test Circuit for Open Collector Outputs

SWITCH POSITION

TEST SWITCH

t t

PLZ PZL

closed closed

All other open

7.0V

R

L

R

C

L

NEGATIVE PULSE

POSITIVE PULSE

90%

10%

V

M

10%

t

THL (tf

t

TLH (tr

90%

V

M

Input Pulse Definition

t

w

V

M

10%

)

t

w

t

TLH (tr

t

THL (tf

)

90%

V

M

90%

10%

AMP (V)

0V

AMP (V)

0V

DEFINITIONS:

R

= Load resistor;

L

see AC electrical characteristics for value.

= Load capacitance includes jig and probe capacitance;

C

L

see AC electrical characteristics for value.

R

= Termination resistance should be equal to Z

T

pulse generators.

OUT

of

family

74F

INPUT PULSE REQUIREMENTS

V

amplitude

3.0V

M

1.5V

rep. rate

1MHz 500ns

t

w

t

TLHtTHL

2.5ns 2.5ns

SF00128

1996 Mar 12

7

Philips Semiconductors Product specification

74F273AOctal D flip-flop

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

1996 Mar 12

8

Philips Semiconductors Product specification

74F273AOctal D flip-flop

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

1996 Mar 12

9

Philips Semiconductors Product specification

74F273AOctal D flip-flop

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 10-98 Document order number: 9397-750-051 13

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