Datasheet 74f225 DATASHEETS (Philips)

INTEGRATED CIRCUITS

74F225

16X5 asynchronous FIFO (3-State)

Product specification IC15 Data Handbook

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1992 Jun 15

Philips Semiconductors Product specification

74F22516 × 5 asynchronous FIFO (3-State)

FEA TURES

•Independent synchronous inputs and outputs

•Organized as 16 words of 5 bits

Ready (IR), Unload Clock Output (UNCPOUT) and Output Ready (OR). The data outputs are non–inverting with respect to the data inputs and are disabled when the OE Low, the data outputs are enabled to function as totem–pole outputs.

•DC to 25MHz data rate

•3–State outputs

•Cascadable in word–width and depth direction

DESCRIPTION

This 80–bit active element First–In–First–Out (FIFO) is a monolithic Schottky–clamped transistor–transistor logic (STTL) array organized as 16–words of 5–bits each. A memory system using the ’F225 can be easily expanded in multiples of 16–words of 5–bits as shown in Figure 1. The 3–State outputs controlled by a single enable input (OE

) make bus connection and multiplexing simple. The ’F225 processes data in a parallel format at any desired clock rate from DC to 25MHz. Status of the ’F225 is provided by three outputs, Input

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS DESCRIPTION 74F (U.L.)

CPA, CPB Load clock A and load clock B inputs 1.0/0.033 20µA/20µA

D0 – D4 Data inputs 1.0/0.033 20µA/20µA

OE Output enable input (active–Low) 1.0/0.033 20µA/20µA

UNCPIN Unload clock input 1.0/0.033 20µA/20µA

MR Master reset input (active–Low) 1.0/0.033 20µA/20µA

IR Input ready output 50/33 1.0mA/20mA

UNCPOUT Unload clock output (active–Low) 50/33 1.0mA/20mA

Q0 – Q4 Data outputs 150/40 3.0mA/24mA

OR Output ready output 50/33 1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

TYPE

74F225 25MHz 65mA

ORDERING INFORMATION

DESCRIPTION COMMERCIAL RANGE

20–pin plastic DIP N74F225N SOT146-1

20–pin plastic SOL N74F225D SOT163-1

TYPICAL f

ORDER CODE

V

CC

T

= 0°C to +70°C

amb

HIGH/LOW

input is High. When OE is

TYPICAL SUPPL Y

MAX

= 5V ±10%,

CURRENT

( TOTAL)

LOAD VALUE

HIGH/LOW

PKG DWG #

RESET MODE

A High–to–Low transition on the Master Reset (MR) input invalidates all data stored in the FIFO by clearing the control logic and setting OR Low. This High–to–Low transition on the MR effect the data outputs but since OR is driven Low, it signifies invalid data on the outputs.

input does not

READ MODE

The Output Ready (OR) output is High when valid data is present on the data outputs. Data in the array is shifted on the Low–to–High transition of the Unload Clock Input (UNCPIN). In order for Output Ready (OR) to go High, Unload Clock Input (UNCPIN) must also be High.

WRITE MODE

Data may be written into the array on the Low–to–High transition of either load clock (CPA or CPB) input. When writing data into the FIFO, one of the load clock inputs must be held High while the other strobes data into the FIFO. This arrangement allows either load clock to function as an inhibit for the other. Input Ready (IR) monitors the status of the last word location and signifies when the FIFO is full. This output is High whenever the FIFO is available to accept new data. The unload clock output (UNCPOUT) also monitors the last word location. This output generates a Low–logic–level pulse (synchronized to the internal clock pulse) when the last word location is vacant

June 15, 1992 853-1652 06992

2

Philips Semiconductors Product specification

74F22516 × 5 asynchronous FIFO (3-State)

PIN CONFIGURATION

CPA

1

IR

2

UNCPOUT

3

D0

4

D1

5 6

D2 D3

7

D4

8 9

OE

10 11

GND

LOGIC SYMBOL

CPA

1

CPB

19

UNCPIN

16

OE

9

MR

18

Q0 Q1 Q2 Q3 Q4 IR OR

4 5 6 7 8

D0 D1 D2 D3 D4

UNCPOUT

20 19 18 17 16 15 14 13 12

SF00334

V

CC

CPB MR OR UNCPIN

Q0 Q1 Q2 Q3 Q4

IEC/IEEE SYMBOL

EN5

CT=0

CT<16

CT>0

1D

FIFO 16 X 5

CTR

&

1

&

–

Z4

+

G1

G2/Z3

2CT<16

5

3

2

17

4

15 14 13 12

11

SF00336

9

18

1 19

16 4

5 6 7 8

3

V

CC

GND

= Pin 20

= Pin 10

15 14 13 12 11 2 17

SF00335

June 15, 1992

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Philips Semiconductors Product specification

74F22516 × 5 asynchronous FIFO (3-State)

LOGIC DIAGRAM

Word 16 (last word)

Detail A

4

D0

Word 15

Word 3–14 same as 2 or 16

Word 2

Word 1 (first word)

15

QO

UNC-

POUT

D1

D2

D3

D4

CPA CPB

IR

MR

5

6

7

8

1 19

3

2

18

D

CP

CLR

Q

Detail A

14

13

12

11

9

17

OR

16

UNCPIN

V

= pin 20

CC

GND = pin 10

SF00337

Q1

Q2

Q3

Q4

OE

June 15, 1992

4

Philips Semiconductors Product specification

74F22516 × 5 asynchronous FIFO (3-State)

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.)

SYMBOL PARAMETER RATING UNIT

V

I

OUT

T

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT

V

T

Supply voltage

CC

Input voltage –0.5 to +7.0 V

IN

I

Input current –30 to +5 mA

IN

Voltage applied to output in High output state –0.5 to V

OUT

–0.5 to +7.0 V

Current applied to output in Low output state IR, OR, UNCPOUT 40 mA Current applied to output in Low output state Data outputs 48 mA Operating free air temperature range 0 to +70

amb

Storage temperature range –65 to +150

stg

MIN NOM MAX

Supply voltage 4.5 5.0 5.5 V

CC

V V

I

OH

High–level input voltage 2.0 V

IN

Low–level input voltage 0.8 V

IL

Input clamp current –18 mA

Ik

High–level output current IR, OR, UNCPOUT –1 mA

Data outputs –3 mA

I

OL

Low–level output current IR, OR, UNCPOUT 20 mA

Data outputs 24 mA

amb

Operating free air temperature range 0 +70

CC

V

°C °C

°C

June 15, 1992

5

Philips Semiconductors Product specification

74F22516 × 5 asynchronous FIFO (3-State)

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

SYMBOL PARAMETER TEST CONDITIONS

IR, OR, VCC = MIN, VIL = MAX

V

High-level output voltage UNCPOUT VIH = MIN, IOH = MAX

OH

Data VCC = MIN, VIL = MAX outputs VIH = MIN, IOH = MAX

V

I

OZH

I

OZL

I I

OS CC

Low-level output voltage VCC = MIN, VIL = MAX

OL

VIH = MIN, I

Input clamp voltage VCC = MIN, II = I

IK

I

Input current at maximum input voltage VCC = MAX, VI = 7.0V 100

I

High–level input current VCC = MAX, VI = 2.7V 20

IH

Low–level input current VCC = MAX, VI = 0.5V –20 µA

IL

Offset–output current, High–level voltage applied

Offset–output current, Low–level voltage applied

Short-circuit output current

3

VCC = MAX, VI = 2.7V 50 µA

VCC = MAX, VI = 0.5V –50 µA VCC = MAX -60 -150 mA

OL

= MAX

IK

Supply current (total) VCC = MAX 65 95 mA

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

3. Not more than one output should be shorted at a time. For testing I

techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.

= 5V, T

CC

amb

= 25°C.

, the use of High-speed test apparatus and/or sample-and-hold

OS

1

±10%V

±5%V

±10%V

±5%V

±10%V

±5%V

CC

LIMITS UNIT

MIN TYP

2

MAX

2.5 V

2.7 V

2.4 V

2.7 V

0.35 0.50 V

-0.73 -1.2 V

µA µA

June 15, 1992

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Philips Semiconductors Product specification

74F22516 × 5 asynchronous FIFO (3-State)

AC ELECTRICAL CHARACTERISTICS

LIMITS

T

= +25°C T

amb

SYMBOL PARAMETER TEST VCC = +5.0V

CONDITION

CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω

MIN TYP MAX MIN MAX

f

MAX

t

PLH

t

PHL

t

PLH

t

PHL

t

SK

t

PLH

t

PLH

t

PLH

t

PHL

tw(L)

t

PHL

t

PHL

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

Maximum clock frequency, Cascade mode

Propagation delay UNCPIN to Qn

Propagation delay UNCPIN to OR

Output skew Qn to OR ↑

Propagation delay UNCPIN to IR

Propagation delay CPA or CPB to OR

Propagation delay CPA or CPB to UNCPOUT

Pulse width, Low UNCPOUT

Propagation delay CPA or CPB to IR

Propagation delay MR to OR

Propagation delay MR to IR

Output enable time to High or Low level

Output disable time from High or Low level

Waveform 2 and 3 25 25 MHz

Waveform 2

10.0

16.0

9.5

6.0

13.0

12.0

20.0

8.5

Waveform 4 2.0 12.0 0.0 15.0 ns

Waveform 2 50 60 70 50 85 ns

Waveform 4 55 65 75 50 90 ns

Waveform 4

20.0

8.5

23.0

11.5

Waveform 4 12.0 ns

Waveform 3 11.0 13.5 17.0 9.0 19.0 ns

Waveform 3 5.5 8.5 11.5 5.0 13.0 ns

Waveform 3 2.0 4.0 7.0 1.5 7.5 ns Waveform 5

Waveform 6 Waveform 5

Waveform 6

1.5

2.5

1.5

2.0

3.5

4.5

3.5

4.0

19.5

16.0

25.0

11.0

27.0

15.0

6.5

7.5

7.0

= 0°C to +70°C

amb

VCC = +5.0V ± 10%

9.0

8.5

14.0

5.0

17.0

7.5

1.0

2.0

1.0

1.5

22.0

19.0

29.0

12.0

29.0

16.0

7.0

9.0

7.5

UNIT

ns

AC SETUP REQUIREMENTS

LIMITS

T

= +25°C T

amb

SYMBOL PARAMETER TEST VCC = +5.0V

CONDITION

CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω

MIN TYP MAX MIN MAX

ts(H)

ts(L)

th(H) th(L)

t

rec

tw(H)

tw(L) tw(L)

Setup time, High or Low Dn to CPA or CPB

Hold time, High or Low Dn to CPA or CPB

Recovery time MR to CPA or CPB

CPA or CPB pulse width, High or Low

UNCPIN pulse width, High or Low

Waveform 1

0.0

14.0

12.5

Waveform 1 0.0 0.0 ns

Waveform 1

Waveform 2

6.5

3.0

24.0

3.5

tw(L) MR pulse width, Low Waveform 1 3.5 4.5 ns

June 15, 1992

7

= 0°C to +70°C

amb

VCC = +5.0V ± 10%

0.0

16.5

14.0

8.5

3.5

28.0

4.0

UNIT

ns

Philips Semiconductors Product specification

74F22516 × 5 asynchronous FIFO (3-State)

TYPICAL TIMING DIAGRAM

MR

CPA

CPB

Dn

UNCPIN

UNCPOUT

OR

Qn

Word 1

IR

Clear

Load word 1

Load word 2

Word 2

Word 1

NOTE: Shaded areas Indicates irrelevant input conditions.

Word 3 is Low

Load words 3–15

Word

Load word 16

16

Unload word 16

Word 16

SF00338

Word 1 Word 2

Unload word 2

Unload word 3

Word 3

Unload words 4–15

June 15, 1992

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Philips Semiconductors Product specification

74F22516 × 5 asynchronous FIFO (3-State)

AC WAVEFORMS

MR

CP

Dn

tw(L)

V

M

V

M

tw(H)

t

h

t

su

V

M

V

M

tw(L)

V

M

V

M

V

M

t

su

Waveform 1. MR and Clock Pulse Widths, Data Setup and

to Clock Setup Time

1/fMAX

V

M

tw(H)

t

PLH

V

M

t

PLH

V

M

t

PLH

V

M

V

M

t

V

UNCPIN

Qn

OR

IR

Hold Times and MR

tw(L)

V

M

t

PHL

V

M

Waveform 2. UNCPIN to Output Delays

M

SF00339

V

M

PHL

M

SF00340

1/f

CPA or CPB

UNCPOUT

OR

Qn

V

M

t

PHL

t

PLH

t

SK

V

M

V

MAX

V

M

tw(L)

V

M

V

M

t

PLH

V

M

SF00342

Waveform 4. CPA or CPB to UNCPOUT and OR Delay,

UNCPOUT Pulse Width and Qn to OR Skew

OE

Qn

V

M

t

PZH

V

M

t

PHZ

VOH -0.3V

M

SF00343

Waveform 5. 3-State Output Enable Time to High Level and

Output Disable Time from High Level

0V

V

M

t

PZL

Output Disable Time from Low Level

CPA or CPB

MR

OR

1/f

MAX

V

M

V

M

t

PHL

V

IR

M

t

PLH

t

PHL

V

M

V

M

V

M

SF00341

OE

Qn

Waveform 6. 3-State Output Enable Time to Low Level and

Waveform 3. CPA or CPB to IR Delay and MR to IR

and OR Delay

NOTES:

1. For all waveforms, V

2. The shaded areas indicate when the input is permitted to change for predictable output performance.

June 15, 1992

= 1.5V.

M

9

V

M

t

PLZ

V

M

VOL +0.3V

SF00344

Philips Semiconductors Product specification

74F22516 × 5 asynchronous FIFO (3-State)

APPLICATION

Load clock

NC

5–bit data input

Master reset

Input ready

5–bit data input

NC

CPA CPB UNCPOUT IR D0 D1 D2 D3 D4

MR OE

CPA CPB UNCPOUT IR D0 D1 D2 D3 D4

OR

UNCPIN

NC NC

Q0

Q1 Q2 Q3 Q4

OR

UNCPIN

NC

Q0

Q1 Q2 Q3 Q4

Figure 1. Expanding the 74F225 FIFO (48 words of 10 bits)

TEST CIRCUIT AND WAVEFORM

CPA CPB UNCPOUT IR D0 D1 D2 D3 D4

MR OE MR OE

MR OE MR OE CPA CPB UNCPOUT IR D0 D1 D2 D3 D4

OR

UNCPIN

Q0

Q1 Q2 Q3 Q4

OR

UNCPIN

Q0

Q1 Q2 Q3 Q4

NC

CPA CPB UNCPOUT IR D0 D1 D2 D3 D4

OR

UNCPIN

Q0

Q1 Q2 Q3 Q4

OR

UNCPIN

Q0

Q1 Q2 Q3 Q4

Output ready

Unload clock

5–bit data output

Output enable

5–bit data output

SF00345

V

CC

R

PULSE

GENERATOR

V

IN

R

T

D.U.T.

V

OUT

L

C

R

L

Test Circuit for Open Collector Outputs

SWITCH POSITION

TEST SWITCH

t

PLZ

t

PZL

closed closed

All other open

DEFINITIONS:

= Load resistor;

R

L

see AC electrical characteristics for value.

C

= Load capacitance includes jig and probe capacitance;

L

see AC electrical characteristics for value.

R

= Termination resistance should be equal to Z

T

pulse generators.

OUT

of

7.0V NEGATIVE

PULSE

POSITIVE PULSE

family

74F

90%

10%

amplitude

t

w

V

M

10%

)

V

90%

M

t

THL (tf

t

TLH (tr

)

t

TLH (tr

t

THL (tf

t

w

Input Pulse Definition

INPUT PULSE REQUIREMENTS

V

rep. rate

M

3.0V

1.5V

1MHz 500ns

10%

)

90%

t

V

M

V

M

w

90%

10%

t

TLHtTHL

2.5ns 2.5ns

AMP (V)

0V

AMP (V)

0V

SF00128

June 15, 1992

10

Philips Semiconductors Product specification

16X5 asynchronous FIFO (3-State)

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

74F225

1992 Jun 15

11

Philips Semiconductors Product specification

16X5 asynchronous FIFO (3-State)

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

74F225

1992 Jun 15

12

Philips Semiconductors Product specification

16X5 asynchronous FIFO (3-State)

74F225

NOTES

1992 Jun 15

13

Philips Semiconductors Product specification

16X5 asynchronous FIFO (3-State)

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

74F225

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 10-98 Document order number: 9397-750-05099

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