Datasheet 74F219SJX, 74F219SJ, 74F219SCX, 74F219SC, 74F219PC Datasheet (Fairchild Semiconductor)

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June 1988 Revised July 1999

74F219 64-Bit Random Access Memory with 3-STATE Outputs

General Description

The 74F219 is a high-speed 64-bit RAM organized as a 16word by 4-bit array. Address inputs are buffered to minimize loading and are full y decoded on-chip. The outputs are 3-STATE and are in the high-impedance state whenever the Chip Sele ct (CS

) input is HIGH. The outputs are active only in the Read mode. This device is similar t o the 74F189 but features non-inverting, rather than inverting, data outputs.

Features

■ 3-STATE outputs for data bus applications

■ Buffered inputs minimize loading

■ Address decoding on-chip

■ Diode clamped inputs minimize ringing

■ Available in SOIC (300 mil only)

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbol Connection Diagram

Order Number Package Number Package Description

74F219SC M16B 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F219SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F219PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F219

Unit Loading/Fan Out

Function Table

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

Block Diagram

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

A0–A

Address Inputs 1.0/1.0 20 µA/−0.6 mA

Chip Select Input (Active LOW) 1.0/2.0 20 µA/−1.2 mA

Write Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA

0–D3

Data Inputs 1.0/1.0 20 µA/−0.6 mA

0–O3

3-STATE Data Outputs 150/40 (33.3) −3 mA/24 mA (20 mA)

Inputs

Operation Condition of Outputs

L L Write High Impedance L H Read True Stored Data H X Inhibit High Impedance

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74F219

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyon d which the device

may be damaged or have its useful life impaired . Functional operation under these condit ions is not implied.

Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.

DC Electrical Characteristics

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V

Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output

in HIGH State (with V

= 0V)

Standard Output −0.5V to V

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the r ated I

(mA)

Free Air Ambi ent Temperature 0°C to +70°C Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

Conditions

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

Output HIGH 10% V

2.5

VMin

IOH = −1 mA

Voltage 10% V

2.4 IOH = −3 mA

5% V

2.7 IOH = −1 mA

5% V

2.7 IOH = −3 mA

Output LOW 10% V

0.5 V Min IOL = 24 mA

Voltage

Input HIGH

5.0 µAMaxVIN = 2.7V

Current

BVI

Input HIGH Current

7.0 µAMaxVIN = 7.0V

Breakdown Test

CEX

Output HIGH

50 µAMaxV

OUT

= V

Leakage Current

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All Other Pins Grounded

Output Leakage

3.75 µA0.0

IOD

= 150 mV

Circuit Current All Other Pins Grounded

Input LOW −0.6

mA Max

VIN = 0.5V (An, WE, Dn)

Current −1.2

VIN = 0.5V (CS)

OZH

Output Leakage Current 50 µAMaxV

OUT

= 2.7V

OZL

Output Leakage Current −50 µAMaxV

OUT

= 0.5V

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

Bus Drainage Test 500 µA0.0VV

OUT

= 5.25V

Power Supply Current 37 55 mA Max

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74F219

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

= −55°C to +125°CTA = 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF CL = 50 pF

Min Typ Max Min Max Min Max

PLH

Access Time, HIGH or LOW 10.0 18.5 26.0 9.0 32.0 10.0 27.0

PHL

An to O

8.0 13.5 19.0 8.0 23.0 8.0 20.0

PZH

Access Time, HIGH or LOW 3.5 6.0 8.5 3.5 10.5 3.5 9.5 ns

PZL

CS to O

5.0 9.0 13.0 5.0 15.0 5.0 14.0

PHZ

Disable Time, HIGH or LOW 2.0 4.0 6.0 2.0 8.0 2.0 7.0

PLZ

CS to O

3.0 5.5 8.0 2.5 10.0 3.0 9.0

PZH

Write Recovery Time 6.5 20.0 28.0 6.5 37.5 6.5 29.0 ns

PZL

HIGH or LOW, WE to O

6.5 11.0 15.5 6.5 17.5 6.5 16.5

PHZ

Disable Time, HIGH or LOW 4.0 7.0 10.0 3.5 12.0 4.0 11.0

PLZ

WE to O

5.0 9.0 13.0 5.0 15.0 5.0 14.0

Symbol Parameter

TA = +25°CTA = −55°C to +125°CTA = 0°C to +70°C

UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V

Min Max Min Max Min Max

tS(H) Setup Time, HIGH or LOW 0 0 0 ns tS(L)

An to WE

000

tH(H) Hold Time, HIGH or LOW 2.0 2.0 2.0 tH(L)

An to WE

2.0 2.0 2.0

tS(H) Setup Time, HIGH or LOW 10.0 11.0 10.0 ns tS(L)

Dn to WE

10.0 11.0 10.0

tH(H) Hold Time, HIGH or LOW 0 2.0 0 tH(L)

Dn to WE

02.00

tS(L) Setup Time, LOW 0 0 0 ns

CS to WE

tH(L) Hold Time, LOW 6.0 7.5 6.0

CS to WE

tW(L)

WE Pulse Width, LOW

6.0 15.0 6.0 ns

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74F219

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M16B

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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74F219 64-Bit Random Access Memory with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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