Datasheet 74f195a DATASHEETS (Philips)

INTEGRATED CIRCUITS

74F195A

4-bit parallel-access shift register

Product specification IC15 Data Handbook

 

1996 Mar 12

Philips Semiconductors Product specification

D0–D3

Data inputs

J, K

J-K or D type serial inputs

CP

Clock Pulse input (active rising edge)

MR

Master Reset input (active Low)

74F195A4-bit parallel-access shift register

J, K

FEA TURES

•Shift right and parallel load capability

•J – K (D) inputs to first stage

•Complement output from last stage

•Asynchronous Master Reset

•Diode inputs

DESCRIPTION

The 74F195A is a 4-Bit Parallel Access Shift Register and its functional characteristics are indicated in the Logic Diagram and Function Table. This device is useful in a variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds.

The 74F195A operates in two primary modes: shift right (Q0→Q1) and parallel load, which are controlled by the state of the Parallel Enable (PE and K direction Q0→Q1→Q2→Q3 following each Low-to-High clock transition.

The J and K special applications, and by tying the two together the simple D-type input is made for general applications.

The device appears as four common clocked D flip-flops when the PE parallel inputs (D0–D3) is transferred to the respective Q0–Q3 outputs. Shift left operation (Q3–Q2) can be achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE

All parallel and serial data transfers are synchronous, occurring after each Low-to-High clock transition. The 74F195A utilizes edge-triggering, therefore there is no restriction on the activity of the

) input. Serial data enters the first flip-flop (Q0) via the J

inputs when the PE input is High, and is shifted one bit in the

inputs provide the flexibility of the J-K type input for

input is Low. After the Low-to-High clock transition, data on the

input Low.

, Dn, and PE inputs for logic operation, other than the set-up and

hold time requirements. A Low on the asynchronous Master Reset (MR

) input sets all Q

outputs Low, independent of any other input condition.

PIN CONFIGURATION

1

MR

2

J

3

K

D0

4

D1

5

D2

6

D3

TYPE TYPICAL f

MAX

74F195A 180MHz 40mA

16

V

CC

15

Q0

14

Q1

13

Q2

12

Q3

11

Q3

107

CP

98GND PE

SF00757

TYPICAL

SUPPLY CURRENT

(TOTAL)

ORDERING INFORMATION

COMMERCIAL RANGE

DESCRIPTION

16-pin plastic DIP N74F195AN SOT 38-4

16-pin plastic SO N74F195AD SOT 109-1

VCC = 5V ±10%,

T

= 0°C to +70°C

amb

PKG. DWG. #

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION

Q0–Q3,

Q3

NOTE:

One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

1996 Mar 12 853-0024 16555

74F (U.L.)

LOAD VALUE HIGH/LOW

HIGH/LOW

p

74F195 1.0/0.033 20µA/20µA

74F195A 1.0/1.0 20µA/0.6mA

74F195 1.0/0.033 20µA/20µA

74F195A 1.0/1.0 20µA/0.6mA

74F195 1.0/0.033 20µA/20µA

74F195A 1.0/1.0 20µA/0.6mA

74F195 2.0/0.066 40µA/40µA

74F195A 1.0/1.0 20µA/0.6mA

Data outputs 50/33 1.0mA/20mA

2

Philips Semiconductors Product specification

74F195A4-bit parallel-access shift register

LOGIC SYMBOL

9 2

10

3 1MR

= Pin 16

V

CC

GND = Pin 8

PE J CP

K

LOGIC DIAGRAM

CP

PE

MR

IEC/IEEE SYMBOL

4

56

7

9

CP

R

1

10

2 3 4 5 6 7

R

D

Q2 Q3

13 12

D3D0

11Q3

SF00758

D1 D2

Q0 Q1

15 14

10

9

2

J

3

K

1

4

D0

M1 R

C2/1

1, 2J 1, 2K 1, 2D 1, 2D

S

SRG4

Q

SF00759

15

14 13 12

11

Q0

VCC = Pin 16 GND = Pin 8

1996 Mar 12

5

D1

6

D2

7

D3

CP

R

CP

R

CP

R

D

R

D

R

D

S

Q

S

Q

S

Q

14

13

12

11

SF00760

Q1

Q2

Q3

3

Philips Semiconductors Product specification

OPERATING MODES

SYMBOL

PARAMETER

UNIT

74F195A4-bit parallel-access shift register

FUNCTION TABLE

INPUTS OUTPUTS

MR CP PE J K Dn Q0 Q1 Q2 Q3 Q3

L X X X X X L L L L H Reset (clear) H ↑ h h h X H q0 q1 q2 q2 Shift, set First stage H ↑ h l l X L q0 q1 q2 q2 Shift, reset First stage H ↑ h h l X q0 q0 q1 q2 q2 Shift, toggle First stage H ↑ h l h X q0 q0 q1 q2 q2 Shift, retain First stage

H = High voltage level h = High voltage level one setup time prior to Low-to-High clock transition L = Low voltage level l = Low voltage level one setup time prior to Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition dn(qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the Low-to-High clock transition.

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)

SYMBOL PARAMETER RATING UNIT

V V I

IN

V I

OUT

T T

CC IN

OUT

amb stg

Supply voltage –0.5 to +7.0 V Input voltage –0.5 to +7.0 V Input current –30 to +5 mA Voltage applied to output in High output state –0.5 to +V

CC

V Current applied to output in Low output state 40 mA Operating free-air temperature range 0 to +70 °C Storage temperature –65 to +150 °C

RECOMMENDED OPERATING CONDITIONS

V V V I I I T

CC IH

IL IK OH OL

amb

Supply voltage 4.5 5.0 5.5 V High-level input voltage 2.0 V Low-level input voltage 0.8 V Input clamp current –18 mA High-level output current –1 mA Low-level output current 20 mA Operating free-air temperature range 0 70 °C

LIMITS

MIN NOM MAX

1996 Mar 12

4

Philips Semiconductors Product specification

NO TAG

VOHHigh-level output voltage

CC

,

IL

VOLLow-level output voltage

CC

,

IL

V

f

MH

74F195A4-bit parallel-access shift register

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

LIMITS

SYMBOL PARAMETER TEST CONDITIONS

p

V

IK

I

IH

I

IL

I

OS

I

CC

Input clamp voltage VCC = MIN, II = I Input current at maximum input voltage VCC = MAX, VI = 7.0V 74F195A 100 µA High-level input current VCC = MAX, VI = 2.7V all others 20 µA Low-level input current VCC = MAX, VI = 0.5V 74F195A –600 mA Short-circuit output current

3

Supply current (total) VCC = MAX 74F195A 40 58 mA

VCC = MIN, VIL = MAX VIH = MIN, IOH = MAX

VCC = MIN, VIL = MAX VIH = MIN, IOL = MAX

IK

VCC = MAX –60 –150 mA

±10%V

±5%V

±10%V

±5%V

CC

MIN

2.5 V

2.7 3.4 V

TYP

NO TAG

MAX

0.35 0.50

–0.73 –1.2 V

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

3. Not more than one output should be shorted at a time. For testing I

= 5V, T

CC

techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting

amb

= 25°C.

, the use of high-speed test apparatus and/or sample-and-hold

OS

of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I

tests should be performed last.

OS

UNIT

AC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER

MAX

t

PLH

t

PHL

t

PLH

t

PHL

t

PHL

t

PLH

Maximum clock frequency

Propagation delay CP to Qn

Propagation delay CP to Q3

Propagation delay MR to Qn

Propagation delay MR to Q3

Load mode

Shift mode

LIMITS

TEST

CONDITION

VCC = +5V

T

= +25°C

amb

C

= 50pF, RL = 500Ω

L

VCC = +5V ± 10%

T

= 0°C to +70°C

amb

C

= 50pF, RL = 500Ω

L

UNIT

MIN TYP MAX MIN MAX

Waveform

NO TAG

Waveform

NO TAG

Waveform

NO TAG

165 180 150 180 190 170

3.0

2.5

2.0

5.0

4.0

5.5

4.0

9.5

7.0

9.5

6.5

2.5

2.0

2.5

2.0

10.0

7.5

9.5

7.0

Waveform 2 2.0 4.0 7.0 2.0 7.0 ns

Waveform 2 2.5 4.5 8.0 2.0 10.0 ns

z

ns

1996 Mar 12

5

Philips Semiconductors Product specification

74F195A4-bit parallel-access shift register

AC SETUP REQUIREMENTS

LIMITS

SYMBOL PARAMETER

tS(H) tS(L)

th(H) th(L)

tS(H) tS(L)

th(H) th(L)

tW(H)

tW(L)

t

REC

Setup time, High or Low J, K and Dn to CP

Hold time, High or Low J, K and Dn to CP

Setup time, High or Low PE to CP

Hold time, High or Low PE to CP

CP Pulse width High

MR Pulse width Low

Recovery time MR to CP

TEST

CONDITION

VCC = +5V

T

= +25°C

amb

C

= 50pF, RL = 500Ω

L

MIN TYP MAX MIN MAX

Waveform 3

Waveform 4

Waveform

NO TAG

2.5

0.0

1.0

2.0

2.5

0.0

4.5 4.5 ns

Waveform 2 4.5 4.5 ns

Waveform 2 2.5 3.0 ns

VCC = +5V ± 10%

T

= 0°C to +70°C

amb

C

= 50pF, RL = 500Ω

L

2.5

0.0

1.0

2.0

2.5

0.0

UNIT

ns

AC WAVEFORMS

For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.

1/f

max

CP

Q3

Qn

V

M

tw(H)

t

PHL

t

PLH

V

M

V

M

V

M

V

M

t

PLH

V

M

t

PHL

V

M

Waveform 1. Propagation Delay, Clock Input to Output,

Clock Pulse Width, and Maximum Clock Frequency

,

J, K

CP

V

Dn

V

M

th(H)ts(H)

V

M

V

M

th(L)ts(L)

V

M

SF00761

MR

CP

Qn

Q3

Waveform 3. Master Reset Pulse Width, Master Reset to

Output Delay, and Master Reset to Clock Recovery T ime

SERIAL-SHIFT RIGHT PARALLEL LOAD

PE

CP

V

M

t

PHL

t

PLH

V

M

(H)

t

s

V

M

V

M

t

(L)

w

V

rec

V

M

SF00762

V

t

h

V

M

ts(L)

M

t

h

V

M

1996 Mar 12

Waveform 2. Data Setup and Hold Times

SF00763

Qn

RESPONSE Qn=Qn–1 Qn=Dn

Waveform 4. Setup and Hold Times, Parallel Enable to Clock

6

SF00764

Philips Semiconductors Product specification

74F195A4-bit parallel-access shift register

TEST CIRCUIT AND WAVEFORMS

V

CC

PULSE

GENERATOR

V

IN

R

T

D.U.T.

V

OUT

R

C

L

Test Circuit for Totem-Pole Outputs

DEFINITIONS:

= Load resistor;

R

L

see AC ELECTRICAL CHARACTERISTICS for value.

= Load capacitance includes jig and probe capacitance;

C

L

see AC ELECTRICAL CHARACTERISTICS for value.

R

= T ermination resistance should be equal to Z

T

pulse generators.

OUT

of

NEGATIVE PULSE

POSITIVE PULSE

family

74F

90%

10%

amplitude

t

w

V

M

10%

)

V

90%

M

t

THL (tf

t

TLH (tr

)

t

TLH (tr

t

THL (tf

t

w

Input Pulse Definition

INPUT PULSE REQUIREMENTS

V

rep. rate

M

3.0V

1.5V

1MHz 500ns

10%

)

90%

t

w

V

M

V

M

90%

10%

t

TLHtTHL

2.5ns 2.5ns

AMP (V)

0V

AMP (V)

0V

SF00006

1996 Mar 12

7

Philips Semiconductors Product specification

4-bit parallel-access shift register

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

74F195A

1996 Mar 12

8

Philips Semiconductors Product specification

4-bit parallel-access shift register

74F195A

NOTES

1996 Mar 12

9

Philips Semiconductors Product specification

4-bit parallel-access shift register

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

74F195A

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 10-98 Document order number: 9397-750-05096

 

yyyy mmm dd

10