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© 1999 Fairchild Semiconductor Corporation DS009494 www.fairchildsemi.com
April 1988
Revised July 1999
74F190 Up/Down Decade Counter with Preset and Ripple Clock
74F190
Up/Down Decade Counter with Preset and Ripple Clock
General Description
The 74F190 is a rev ersible BCD (8421) decade counter
featuring synchronous cou nting and asynchrono us presetting. The preset feature allows the 74F190 to be used in
programmable dividers. The Count Enable input, the Terminal Count output and the Ripple Clo ck output m ake possible a variety of methods of implementing multistage
counters. In the counting modes, state changes are initiated by th e rising edge of the clock.
Features
■ High-speed—125 MHz typical count frequency
■ Synchronous counting
■ Asynchronous parallel load
■ Cascadable
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F190SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F190PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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74F190
Unit Loading/Fan Out
Functional Description
The 74F190 is a synchronous up/down BCD decade
counter containin g four edge- trigger ed fl ip-fl ops, wi th inter nal gating and s teering logic to provide individual preset,
count-up and count -down operations. It has an asynchro nous parallel load capability permitting the counter to be
preset to any desired number. When the Parallel Load (PL
)
input is LOW, information present on the Parallel Data
inputs (P
0–P3
) is loaded into the counter and appear s on
the Q outputs. This o peration overr ides the counting functions, as indicated in the Mode Select Table. A HIGH signal
on the CE
input inhibits countin g. When C E is LOW, internal state changes are initiat ed synchr onousl y by the L OWto-HIGH tran sit ion of the c lock input . Th e direc ti on of c ount ing is determined by the U
/D input signal, as indicate d in
the Mode Select Table, CE
and U/D can be changed wi th
the clock in either state, provided only that the recommended setup and hold times are observed.
Two types of outputs are pro vided as overflow/underflow
indicators. The Terminal Count (TC) output is normally
LOW and goes HIGH when a circuit reaches zero in the
count-down mode or rea ches 9 in the cou nt-up mode. The
TC output will then remain HIGH until a state change
occurs, whether by count ing or presetting or until U
/D is
changed. The TC output should not be used as a clock signal because it is subjec t to decoding spikes. The TC sign al
is also used internally to enable the Ripple Clock (RC
) out-
put. The RC
output is normally HIGH. When CE is LOW
and TC is HIGH, the RC
output will go LOW when the clock
next goes LOW and will stay LOW until the clock goes
HIGH again. This feature simplifies the design of multi-
stage counters. For a discussion and illustrations of the
various methods of implementing multistage counters,
please see the 74F191 data sheet.
RC Truth Table
Mode Select Table
*TC is generated internally
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
= LOW Pulse
Pin Names Description
U.L.
Input I
IH/IIL
HIGH/LOW
Output I
OH/IOL
CE Count Enable Input (Active LOW) 1.0/3.0 20 µA/−1.8 mA
CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA
P
0–P3
Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA
PL
Asynchronous Parallel Load Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
U
/D Up/Down Count Control Input 1.0/1.0 20 µA/−0.6 mA
Q
0–Q3
Flip-Flop Outputs 50/33.3 −1 mA/ 20 mA
RC
Ripple Clock Output (Active LOW) 50/33.3 −1 mA/20 mA
TC Terminal Count Output (Active HIGH) 50/33.3 −1 mA/ 20 mA
Inputs Output
CE
TC* CP RC
LH
HXX H
XLX H
Inputs
Mode
PL
CE U/D CP
HL L
Count Up
HL H
Count Down
L X X X Preset (Asyn.)
H H X X No Change (Hold)
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74F190
State Diagram
Logic Diagram
Please note that this d iagram is provided only f or t he understanding of lo gic operations and should not be used to estimat e propagation delays.
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74F190
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditi ons is not implied.
Note 2: Either voltage limit or curren t limit is sufficient to protect in put s .
DC Electrical Characteristics
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V
CC
Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
CC
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
V
OH
Output HIGH 10% V
CC
2.5
VMin
IOH = −1 mA
Voltage 5% V
CC
2.7 IOH = −1 mA
V
OL
Output LOW 10% V
CC
0.5 V Min IOL = 20 mA
Voltage
I
IH
Input HIGH
5.0 µAMaxVIN = 2.7V
Current
I
BVI
Input HIGH Current
7.0 µAMaxVIN = 7.0V
Breakdown Test
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
IID = 1.9 µA
Test All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current −0.6
mA Max
VIN = 0.5V, except CE
−1.8
VIN = 0.5V, CE
I
OS
Output Short-Circuit Current −60 −150 mA Max V
OUT
= 0V
I
CCL
Power Supply Current 38 55 mA Max VO = LOW
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74F190
AC Electrical Characteristics
AC Operating Requirements
Symbol Parameter
TA = +25°CT
A
−55°C to +125°CTA = 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF CL = 50 pF
Min Typ Ma x Min Max Min Max
f
MAX
Maximum Clock Frequency 100 125 75 90 MHz
t
PLH
Propagation Delay 3.0 5.5 7.5 3.0 9.5 3.0 8.5
ns
t
PHL
CP to Q
n
5.0 8.5 11.0 5.0 13.5 5.0 12.0
t
PLH
Propagation Delay 6.0 10.0 13.0 6.0 16.5 6.0 14.0
t
PHL
CP to TC 5.0 8.5 11.0 5.0 13.5 5.0 12.0
t
PLH
Propagation Delay 3.0 5.5 7.5 3.0 9.5 3.0 8.5
ns
t
PHL
CP to RC
3.0 5.0 7.0 3.0 9.0 3.0 8.0
t
PLH
Propagation Delay 3.0 5.0 7.0 3.0 9.0 3.0 8.0
t
PHL
CE to RC
3.0 5.5 7.0 3.0 9.0 3.0 8.0
t
PLH
Propagation Delay 7.0 11.0 18.0 7.0 22.0 7.0 20.0 ns
t
PHL
U /D to RC
5.5 9.0 12.0 5.5 14.0 5.5 13.0
t
PLH
Propagation Delay 4.0 7.0 10.0 4.0 13.5 4.0 11.0
t
PHL
U /D to TC
4.0 6.5 10.0 4.0 12.5 4.0 11.0
t
PLH
Propagation Delay 3.0 4.5 7.0 3.0 9.0 3.0 8.0
ns
t
PHL
Pn to Q
n
6.0 10.0 13.0 6.0 16.0 6.0 14.0
t
PLH
Propagation Delay 5.0 8.5 11.0 5.0 13.0 5.0 12.0
ns
t
PHL
PL to Q
n
5.5 9.0 12.0 5.5 14.5 5.5 13.0
Symbol Parameter
TA = +25°CTA −55°C to +125°CTA = 0°C to +70°C
UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V
Min Max Min Max Min Max
tS(H) Setup Time, HIGH or LOW 4.5 6.0 5.0 ns
tS(L)
Pn to PL
4.5 6.0 5.0
tH(H) Hold Time, HIGH or LOW 2.0 2.0 2.0
tH(L)
Pn to PL
2.0 2.0 2.0
tS(L) Setup Time, LOW 10.0 10.5 10.0 ns
CE to CP
tH(L) Hold Time, LOW 0 0 0
CE to CP
tS(H) Setup Time, HIGH or LOW 12.0 12.0 12.0 ns
tS(L)
U /D to CP
12.0 12.0 12.0
tH(H) Hold Time, HIGH or LOW 0 0 0
tH(L)
U /D to CP
000
tW(L) PL Pulse Width, LOW 6.0 8.5 6.0 ns
tW(L) CP Pulse Width, LOW 5.0 7.0 5.0 ns
t
REC Recovery Time PL to CP
6.0 7.5 6.0 ns
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74F190
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
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74F190 Up/Down Decade Counter with Preset and Ripple Clock
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent license s are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided i n the labe li ng, can be re asonably expected to result in a significant injury to the
user.
2. A critical component in any componen t of a life s uppor t
device or system whose failu re to perform can b e reasonably expected to c ause th e fa i lure of the li fe s upp or t
device or system, or to affect its safety or effectiveness.
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