Datasheet 74f175a DATASHEETS (Philips)

INTEGRATED CIRCUITS

74F175A

Quad D flip-flop

Product specification Supersedes data of 1996 Mar 12 IC15 Data Handbook

 

2000 Jun 30

Philips Semiconductors Product specification

74F175AQuad D flip-flop

FEA TURES

•Four edge-triggered D-type flip-flops

•Buffered common clock

•Buffered asynchronous Master Reset

•True and complementary outputs

•Industrial temperature range available (–40°C to +85°C)

•PNP light loading inputs

DESCRIPTION

The 74F175A is a quad, edge-triggered D-type flip-flop with individual D inputs and both Q and Q Clock (CP) and Master Reset (MR flip-flops simultaneously.

The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output.

All Q outputs will be forced Low independently of clock or data inputs by a Low voltage level on the MR for applications where both true and complementary outputs are required, and the CP and MR

ORDERING INFORMATION

DESCRIPTION

16-pin plastic DIP N74F175AN I74F175AN SOT38-4

16-pin plastic SO N74F175AD I74F175AD SOT109-1

outputs. The common buffered

) inputs load and reset (clear) all

input. The device is useful

are common to all storage elements.

COMMERCIAL RANGE

V

= 5V ±10%,

CC

= 0°C to +70°C

T

amb

PIN CONFIGURATION

TYPE TYPICAL f

74F175A 160MHz 22mA

ORDER CODE

INDUSTRIAL RANGE

V

T

amb

1

MR

Q0

2

0

Q

3

D0

4

D1

5

Q

1

6

Q1

GND

max

= 5V ±10%,

CC

= –40°C to +85°C

16

V

CC

Q3

15

3

Q

14

D3

13

D2

12

Q

2

11

Q2

107

98

CP

SF00718

TYPICAL SUPPL Y

CURRENT (TOTAL)

PKG. DWG. #

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS DESCRIPTION

74F (U.L.)

HIGH/LOW

D0 – D3 Data inputs 74F175A 1.0/0.033 20µA/20µA

MR Master reset input (active–Low) 74F175A 1.0/0.033 20µA/20µA

CP Clock input (active rising edge) 74F175A 1.0/0.033 20µA/20µA Q0–Q3 True outputs 50/33 1.0mA/20mA Q0–Q3 Complementary outputs 50/33 1.0mA/20mA

NOTE:

One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

2000 Jun 30 853–0047 24024

2

LOAD VALUE

HIGH/LOW

Philips Semiconductors Product specification

T

O erating free air tem erature range

74F175AQuad D flip-flop

LOGIC SYMBOL

9 1

VCC = Pin 16 GND = Pin 8

LOGIC DIAGRAM

= Pin 16

V

CC

GND = Pin 8

4 5 12 13

D0 D1 D2 D3

CP MR

Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3

2 3 7 6 10 11 15 14

9

CP

1

MR

SF00719

D0

4

DQ

CP

IEC/IEEE SYMBOL

1 9

4

5

12

13

D1

5

DQ

RD

32 6 1110 14157

Q

0Q0 Q1Q1 Q2Q2 Q3Q3

CP

RD

D2

12

DQ

CP

RD

D3

13

DQ

CP

RD

R

C1

2

1D

Q

SF00721

3 7

6 10 11 15

14

SF00720

FUNCTION TABLE

INPUTS OUTPUTS

MR CP Dn Q

n

Q

n

OPERATING

MODE

L X X L H Reset (clear) H ↑ h H L Load “1” H ↑ I L H Load “0”

H = High voltage level h = High state must be present one setup time before the

Low-to-High clock transition L = Low voltage level l = Low state must be present one setup time before the

Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.)

SYMBOL PARAMETER RATING UNIT

V

I

V

I

OUT

T

Supply voltage –0.5 to +7.0 V

CC

Input voltage –0.5 to +7.0 V

IN

Input current –30 to +5 mA

IN

Voltage applied to output in High output state –0.5 to V

OUT

Current applied to output in Low output state

40 mA

Commercial range 0 to +70

amb

stg

p

Storage temperature range –65 to +150

p

Industrial range –40 to +85

CC

V

°C °C °C

2000 Jun 30

3

Philips Semiconductors Product specification

T

O

V

High-level out ut voltage

CC IL

V

CC IL

V

74F175AQuad D flip-flop

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT

MIN NOM MAX

V

V V

I

OH

I

amb

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

SYMBOL

Notes to DC electrical characteristics

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I

Supply voltage 4.5 5.0 5.5 V

CC

High-level input voltage 2.0 V

IH

Low-level input voltage 0.8 V

IL

Input clamp current –18 mA

IK

High-level output current –1 mA Low-level output current

OL

Commercial range 0 +70

perating free air temperature range

Industrial range –40 +85

PARAMETER TEST LIMITS UNIT

CONDITIONS

OH

V

Low-level output voltage

OL

p

VCC= MIN, VIL = MAX, VIH = MIN, IOH = MAX

VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX

V

I

OS

I

CC

Input clamp voltage VCC = MIN, II = I

IK

I

Input current at maximum input voltage VCC = 0.0V, VI = 7.0V 100 µA

I

High-level input current VCC = MAX, VI = 2.7V 20 µA

IH

Low-level input current VCC = MAX, VI = 0.5V –20 µA

IL

Short-circuit output current

3

VCC = MAX –60 –150 mA

IK

Supply current (total) VCC = MAX 22 31 mA

= 5V, T

CC

OS

= 25°C.

amb

tests should be performed last.

1

"10%V

"5%V

"10%V

"5%V

CC

MIN TYP2MAX

2.5

2.7 3.4

0.30 0.5

–0.73 –1.2 V

20 mA

°C °C

AC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER TEST VCC = +5V

f

max

t

PLH

t

PHL

t

PLH

t

PHL

t

PHL

t

PHL

2000 Jun 30

Maximum clock frequency

Propagation delay CP to Qn or Q

n

Propagation delay

to Qn

MR Propagation delay

to Qn

MR

LIMITS

T

= 25°C T

amb

CONDITION CL = 50pF,

= 500Ω

R

L

= 0°C to +70°C T

amb

= *40°C to +85°C

amb

VCC = +5.0V ± 10% VCC = +5.0V ± 10%

CL = 50pF,

= 500Ω

R

L

CL = 50pF,

= 500Ω

R

L

UNIT

MIN TYP MAX MIN MAX MIN MAX

Waveform 1 140 160 125 110 MHz

Waveform 1

3.0

4.5

4.0

6.0

6.5

8.5

2.5

4.0

7.5

9.0

2.5

4.0

8.0

10.0

ns

Waveform 3 4.5 6.5 9.0 4.5 10.0 4.5 11.0 ns

Waveform 3 4.5 6.0 8.0 4.0 9.0 4.0 10.0 ns

4

Philips Semiconductors Product specification

74F175AQuad D flip-flop

AC SETUP REQUIREMENTS

LIMITS

T

= 25°C T

amb

SYMBOL PARAMETER TEST VCC = +5V

CONDITION CL = 50pF,

= 500Ω

R

L

MIN TYP MAX MIN MAX MIN MAX

ts(H)

(L)

t

s

th(H) t

(L)

h

tw(H)

(L)

t

w

tw(L)

t

REC

Setup time, High or Low Dn to CP

Hold time, High or Low Dn to CP

CP Pulse width High or Low

MR Pulse width Low

Recovery time MR

to CP

Waveform 2

Waveform 1

3.0

0.0

3.0

4.0

Waveform 3 3.5 3.5 4.0 ns

Waveform 3 4.0 4.5 5.0 ns

= 0°C to +70°C T

amb

= 40°C to +85°C

amb

VCC = +5.0V ± 10% VCC = +5.0V ± 10%

CL = 50pF,

= 500Ω

R

L

3.5

0.0

3.5

5.0

CL = 50pF,

= 500Ω

R

L

4.0

0.0

4.0

5.5

UNIT

ns

AC WAVEFORMS

For all waveforms, VM = 1.3V.

1/f

max

V

M

CP

Q

n

t

PHL

t

PLH

tw(H)

Waveform 1. Propagation delay for clock input to output, clock

pulse width, and maximum clock frequency

Dn

CP

V

M

Waveform 2. Data setup time and hold times

V

M

tw(L)

V

M

V

M

V

M

th(H)ts(H)

V

M

V

M

t

PLH

V

M

t

PHL

V

M

SF00722

V

M

th(L)ts(L)

V

M

SF00191

MR

CP

Q

V

M

tw(L)

t

PHL

n

t

PLH

n

V

M

t

REC

V

M

V

M

V

M

SF00723

Waveform 3. Master Reset pulse width, Master Reset to output

delay and Master Reset to Clock recovery time

2000 Jun 30

5

Philips Semiconductors Product specification

74F175AQuad D flip-flop

TEST CIRCUIT AND WAVEFORMS

V

CC

PULSE

GENERATOR

V

IN

R

T

D.U.T.

V

OUT

R

C

L

Test Circuit for Totem-Pole Outputs

DEFINITIONS:

= Load resistor;

R

L

see AC ELECTRICAL CHARACTERISTICS for value.

C

= Load capacitance includes jig and probe capacitance;

L

see AC ELECTRICAL CHARACTERISTICS for value.

R

= Termination resistance should be equal to Z

T

pulse generators.

OUT

of

NEGATIVE PULSE

POSITIVE PULSE

family

74F

90%

10%

amplitude

t

w

V

M

10%

)

V

90%

M

t

THL (tf

t

TLH (tr

)

t

TLH (tr

t

THL (tf

t

w

Input Pulse Definition

INPUT PULSE REQUIREMENTS

V

rep. rate

M

3.0V 1.5V

1MHz 500ns

10%

)

90%

t

w

V

M

V

M

90%

10%

t

TLHtTHL

2.5ns 2.5ns

AMP (V)

0V

AMP (V)

0V

SF00006

2000 Jun 30

6

Philips Semiconductors Product specification

74F175AQuad D flip-flop

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

2000 Jun 30

7

Philips Semiconductors Product specification

74F175AQuad D flip-flop

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

2000 Jun 30

8

Philips Semiconductors Product specification

74F175AQuad D flip-flop

NOTES

2000 Jun 30

9

Philips Semiconductors Product specification

74F175AQuad D flip-flop

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 2000

Date of release: 06-00

Document order number: 9397-750 07531

 

yyyy mmm dd

10