Datasheet 74f173 DATASHEETS (Philips)

INTEGRATED CIRCUITS

74F173

Quad D-type flip-flop (3-State)

Product specification IC15 Data Handbook

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1990 Aug 31

Philips Semiconductors Product specification

74F173Quad D-type flip–flop (3-State)

FEA TURES

• Edge–triggered D–type register

• Gated clock enable for hold ”do nothing” mode

• 3–state output buffers

• Gated output enable control

• Speed upgrade of N8T10 and current sink upgrade

• Controlled output edges to minimize ground bounces

• 48mA sinking capability

DESCRIPTION

The 74F173 is a high speed 4–bit parallel load register with clock enable control, 3–state buffered outputs, and master reset (MR). When the two clock enable (E are low, the data on the D inputs is loaded into the register simultaneously with low–to–high clock (CP) transition. When one or both enable inputs are high one setup time before the low–to–high clock transition, the register retains the previous data.

TYPE TYPICAL f

74F173 125MHz 23mA

0 and E1) inputs

max

Data inputs and clock enable inputs are fully edge–triggered and must be stable only one setup time before the low–to–high clock transition.

The master reset (MR) is an active–high asynchronous input. When the MR is high, all four flip–flops are reset (cleared) independently of any other input condition.

The 3–state output buffers are controlled by a 2–input NOR gate. When both output enable (OE

0 and OE1) inputs are

low, the data in the register is presented at the Q output. When one or both OE

inputs are high, the outputs are forced

to a high impedance ”off” state. The 3–state output buffers are completely independent of

the register operation; the OE

transition does not affect the

clock and reset operations.

TYPICAL SUPPLY CURRENT (TOTAL)

ORDERING INFORMATION

ORDER CODE

DESCRIPTION COMMERCIAL RANGE

= 5V ±10%, T

V

CC

16–pin plastic DIP N74F173N SOT38-4

16–pin plastic SO N74F173D SOT109-1

= 0°C to +70°C

amb

PKG DWG #

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS DESCRIPTION 74F (U.L.) HIGH/

LOW

D0 – D3 Data inputs 1.0/1.0 20µA/0.6mA

CP Clock input 1.0/1.0 20µA/0.6mA

E0, E1 Clock enable inputs 1.0/1.0 20µA/0.6mA

MR Master reset input 1.0/1.0 20µA/0.6mA

OE0, OE1 Output enable inputs 1.0/1.0 20µA/0.6mA

Q0 – Q3 Data outputs 750/80 15mA/48mA

Note to input and output loading and fan out table

1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.

LOAD VALUE

HIGH/LOW

August 31, 1990 853–1 160 00286

2

Philips Semiconductors Product specification

74F173Quad D-type flip–flop (3-State)

PIN CONFIGURATION

1

OE0

2

OE1

3

Q0

4

Q1

5

Q2

6

Q3 CP

GND

LOGIC SYMBOL

9

10

15

E0 E1

7

CP MR

1

OE0

2

OE1

16

V

15

MR

14

D0

13

D3

12

D2

11

Q

107

E

98

E0

SF00290

14 13 12 11

D0 D1 D2 D3

Q0 Q1 Q2 Q3

CC

2 1

IEC/IEEE SYMBOL

14 13 12 11

&9 10 7 1 2 15

C1

&

EN

R

1D

3 4 5 6

SF00292

VCC = Pin 16 GND = Pin 8

3456

SF00291

FUNCTION TABLE

INPUTS OUTPUTS OUTPUTS

MR CP E0 E1 Dn Qn (register)

H X X X X L Reset (clear)

L ↑ l l l L Parallel load L ↑ l l h H L X h X X qn Hold (do nothing) L X X h X qn

Notes to function table

H = High–voltage level h = High state one setup time before the low–to–high clock transition L = Low–voltage level l = Low state one setup time before the low–to–high clock transition qn = Lower case letters indicate the state of the referenced input (or output) on setup time prior to the low–to–high clock transition X = Don’t care ↑ = Low–to–high clock transition

August 31, 1990

3

Philips Semiconductors Product specification

74F173Quad D-type flip–flop (3-State)

FUNCTION TABLE

INPUTS OUTPUTS OUTPUTS

Qn (register) OE0 OE1 Qn

L L L L Read H L L H X H X Z Disabled X X H Z

Notes to function table

H = High–voltage level L = Low–voltage level X = Don’t care Z = High impedance ”off” state

LOGIC DIAGRAM

VCC = Pin 16 GND = Pin 8

MR

OE

OE1

E0

E1

CP

D0

9

10

7

15 1

0

2

14

D

Q

CP

RD

D1

13

DCPQ

Q

3

Q0

RD

D2

12

DCPQ

Q

4

Q1

RD

D3

11

D

Q

CP

Q

5

Q2

RD

SF00293

Q

6

Q3

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.)

SYMBOL

V

CC

V

IN

I

IN

V

OUT

I

OUT

T

amb

T

stg

Supply voltage –0.5 to +7.0 V Input voltage –0.5 to +7.0 V Input current –30 to +5 mA

Voltage applied to output in high output state –0.5 to V Current applied to output in low output state Operating free air temperature range 0 to +70

Storage temperature range –65 to +150

PARAMETER RATING UNIT

CC

96 mA

V

°C °C

August 31, 1990

4

Philips Semiconductors Product specification

74F173Quad D-type flip–flop (3-State)

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT

MIN NOM MAX

V

CC

V

IH

V

IL

I

Ik

I

OH

I

OL

T

amb

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

SYMBOL

V

OH

V

OL

V

IK

I

IH

I

IL

I

OZH

I

OZL

I

OS

I

CC

Notes to DC electrical characteristics

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

3. Not more than one output should be shorted at a time. For testing I techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I

Supply voltage 4.5 5.0 5.5 V High–level input voltage 2.0 V Low–level input voltage 0.8 V Input clamp current –18 mA High–level output current –15 mA Low–level output current Operating free air temperature range 0 +70

48 mA

°C

PARAMETER TEST LIMITS UNIT

CONDITIONS

VCC = MIN, VIL = MAX,

High-level output voltage

VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX, VIH = MIN, IOH = –15mA

Low-level output voltage VCC = MIN, VIL = MAX, ±10%V

VIH = MIN, IOL = MAX ±5%V

Input clamp voltage VCC = MIN, II = I

IK

1

±10%V

±5%V

±10%V

±5%V

MIN TYP2MAX

2.4 V

CC

2.7 3.4 V

CC

2.0 V

CC

2.0 3.1 V

CC

0.35 0.50 V

–0.73 -1.2 V Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA High–level input current VCC = MAX, VI = 2.7V 20 µA Low–level input current VCC = MAX, VI = 0.5V –0.6 mA

Off–state output current, high–level voltage applied VCC = MAX, V

= 2.7V 50

O

Off–state output current, low–level voltage applied VCC = MAX, VO = 0.5V –50 Short–circuit output current3

Supply current (total) I

= 5V, T

CC

OS

= 25°C.

amb

tests should be performed last.

VCC = MAX -60 -150 mA

I

CCH CCLVCC

I

CCZ

= MAX 27 37 mA

, the use of high-speed test apparatus and/or sample-and-hold

OS

19 26 mA

23 32 mA

µA µA

August 31, 1990

5

Philips Semiconductors Product specification

74F173Quad D-type flip–flop (3-State)

AC ELECTRICAL CHARACTERISTICS

LIMITS

T

= +25°C T

amb

SYMBOL PARAMETER TEST VCC = +5.0V

CONDITION CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω

MIN TYP MAX MIN MAX

f

max

t

PLH

t

PHL

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

THL

t

TLH

Maximum clock frequency Waveform 1 100 125 90 MHz Propagation delay

CP to Qn Propagation delay

MR to Qn Output enable time

to high or low level Output disable time

from high or low level Transition time

10% to 90%, 90% to 10%

Waveform 1

Waveform 2 6.5 8.5 11.5 6.0 12.5 ns Waveform 4

Waveform 5 Waveform 4

Waveform 5 Waveform 5

Waveform 4

4.5

6.0

3.5

5.5

1.5

3.0

2.0

4.0

6.5

8.0

5.0

7.0

3.5

5.0

7.5

9.0

10.5

8.0

10.0

7.0

8.5

8.0

10.0

= 0°C to +70°C

amb

VCC = +5.0V ± 10%

4.0

5.5

2.5

4.5

1.0

2.5

2.0

4.0

10.0

11.5

8.5

11.0

8.0

9.0

8.5

11.0

UNIT

ns

AC SETUP REQUIREMENTS

LIMITS

T

= +25°C T

amb

SYMBOL PARAMETER TEST VCC = +5.0V

= 0°C to +70°C

amb

VCC = +5.0V ± 10%

CONDITION CL = 50pF, RL = 500Ω CL= 50pF, RL = 500Ω

MIN TYP MAX MIN MAX

t

(H)

su

t

(L)

su

t

(H)

h

t

(L)

h

t

(H)

su

t

(L)

su

t

(H)

h

t

(L)

h

t

(H)

w

t

(L)

w

t

(H) MR Pulse width, high Waveform 2 3.5 3.5 ns

w

t

rec

Setup time, high or low level Dn to CP

Hold time, high or low level Dn to CP

Setup time, high or low level E to CP

Hold time, high or low level E to CP

CP Pulse width, high or low

Waveform 3

Waveform 1

2.5

4.5

7.5

3.0

6.0

3.0

4.0

0 0

5.0

8.5

0 0

3.0

6.0

Recovery time, MR to CP Waveform 2 4.5 5.5 ns

AC WAVEFORMS

1/f

max

CP

V

M

tw(H)

PHL

V

M

tw(L)t

V

M

t

PLH

UNIT

ns

Qn

V

M

V

M

SF00294

Waveform 1. Propagation delay for clock input to output, clock pulse widths, and maximum clock frequency

August 31, 1990

6

Philips Semiconductors Product specification

74F173Quad D-type flip–flop (3-State)

MR

V

Qn

CP

M

tw(H)

t

PHL

V

M

V

M

t

rec

V

M

V

M

SF00295

Waveform 2. Master reset pulse width, master reset to output delay and master reset to clock recovery time

E

n, Dn

CP

V

M

(H) th(H)

t

su

V

M

V

M

V

M

tsu(L) th(L)

V

M

SF00296

OE

Qn

V

t

PZH

M

10%

90%

V

M

t

PHZ

M

VOH -0.3V

0V

SF00297

Waveform 4. 3-state output enable time to high level, output disable time from high level and transition time to high level

OE

Qn

V

t

PZL

M

90%

V

M

10%

t

V

PLZ

M

3.5V

VOL +0.3V

SF00298

Waveform 5. 3-state output enable time to low level, output disable time from low level and transition time to low level

Waveform 3. Data and enable setup time and hold times

Notes to AC waveforms

1. For all waveforms, VM = 1.5V.

2. The shaded areas indicate when the input is permitted to change for predictable output performance.

TEST CIRCUIT AND WAVEFORMS

V

CC

R

PULSE

GENERATOR

V

IN

R

T

D.U.T.

V

OUT

L

R

C

L

Test Circuit for Open Collector Outputs

SWITCH POSITION

TEST SWITCH

t t

PLZ PZL

closed closed

All other open

DEFINITIONS:

= Load resistor;

R

L

see AC electrical characteristics for value.

C

= Load capacitance includes jig and probe capacitance;

L

see AC electrical characteristics for value.

R

= Termination resistance should be equal to Z

T

pulse generators.

OUT

of

7.0V NEGATIVE

PULSE

POSITIVE PULSE

family

74F

90%

10%

amplitude

V

M

10%

t

THL (tf

t

TLH (tr

90%

V

M

Input Pulse Definition

INPUT PULSE REQUIREMENTS

V

3.0V

1.5V

t

)

t

rep. rate

M

1MHz 500ns

w

V

M

10%

t

)

TLH (tr

t

)

THL (tf

90%

V

M

w

t

TLHtTHL

w

90%

10%

AMP (V)

0V

AMP (V)

0V

2.5ns 2.5ns

SF00128

August 31, 1990

7

Philips Semiconductors Product specification

74F173Quad D-type flip-flop (3-State)

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

1990 Aug 31

8

Philips Semiconductors Product specification

74F173Quad D-type flip-flop (3-State)

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

1990 Aug 31

9

Philips Semiconductors Product specification

74F173Quad D-type flip-flop (3-State)

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 10-98 Document order number: 9397-750-05088

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yyyy mmm dd

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