Datasheet 74f169 DATASHEETS (Philips)

INTEGRATED CIRCUITS

74F168*, 74F169 4-bit up/down binary synchronous counter

* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.

Product specification 1996 Jan 05 IC15 Data Handbook

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Philips Semiconductors Product specification

74F1694-bit up/down binary synchronous counter

FEA TURES

•Synchronous counting and loading

•Up/Down counting

•Modulo 16 binary counter

•Two Count Enable inputs for n-bit cascading

•Positive edge-triggered clock

•Built-in carry look-ahead capability

•Presettable for programmable operation

DESCRIPTION

The 74F169 is a 4-bit synchronous, presettable Modulo 16 up/down counter featuring an internal carry look-ahead for applications in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the Count Enable inputs and internal gating. This mode of operation eliminates the output spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the flip-flops on the Low-to-High transition of the clock.

The counter is fully programmable; that is, the outputs may be preset to either level.

Presetting is synchronous with the clock and takes place regardless of the levels of the Count Enable inputs. A Low level on the Parallel Enable (PE D

input to be loaded into the counter on the next Low-to-High

n

transition of the clock. The direction of counting is controlled by the Up/Down (U/D

High will cause the count to increase, a Low will cause the count to decrease.

The carry look-ahead circuitry provides for n-bit synchronous applications without additional gating. Instrumental in accomplishing

this function are two Count Enable inputs (CET Terminal Count (TC) output. Both Count Enable inputs must be Low to count. The CET TC duration approximately equal to the High level portion of the Q output. The Low level TC pulse is used to enable successive cascaded stages.

) input disables the counter and causes the data at the

) input; a

, CEP) and a

input is fed forward to enable the TC output. The

output thus enabled will produce a Low output pulse with a

0

PIN CONFIGURATION

1

U/D

2

CP

3

D

0

4

D

1

5

D

2

6

D

3

CEP

7

GND

TYPE TYPICAL f

MAX

74F169 115MHz 35mA

16

V

CC

15

TC

14

Q

0

13

Q

1

12

Q

2

11

Q

3

CET

10

98

PE

SF00766

TYPICAL

SUPPLY CURRENT

(TOTAL)

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

16-pin plastic DIP N74F169N SOT38-4

16-pin plastic SO N74F169D SOT109-1

COMMERCIAL RANGE

VCC = 5V ±10%,

T

= 0°C to +70°C

amb

DWG #

PKG

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION

D0 - D

3

Parallel data inputs 1.0/1.0 20µA/0.6mA

74F(U.L.)

HIGH/LOW

CEP Count Enable parallel input (active Low) 1.0/1.0 20µA/0.6mA CET Count Enable Trickle input (active Low) 1.0/2.0 20µA/1.2mA CP Clock input (active rising edge) 1.0/1.0 20µA/0.6mA PE Parallel Enable input (active Low) 1.0/1.0 20µA/0.6mA U/D Up/Down count control input 1.0/1.0 20µA/0.6mA Q0 - Q

3

Flip-flop outputs 50/33 1.0mA/20mA

TC Terminal count output (active Low) 50/33 1.0mA/20mA

NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.

1996 Jan 05 853–0350 16190

2

LOAD VALUE

HIGH/LOW

Philips Semiconductors Product specification

OPERATING MODE

74F1694-bit up/down binary synchronous counter

LOGIC SYMBOL

3456

D

0D1D2D3

Q0Q1Q2Q

TC

3

11121314

15

SF00786

10

VCC = Pin 16 GND = Pin 8

9

PE

1

U/D CP

2

CEP

7

CET

FUNCTIONAL DESCRIPTION

The 74F169 uses edge-triggered J-K-type flip-flops and have no constraints on changing the control or data input signals in either state of the clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode Select Table. When PE Low, the data on the D rising edge of the Clock. In order for counting to occur, both CEP and CET must be Low and PE must be High; the U/D input determines the direction of counting. The Terminal Count (TC output is normally High and goes Low, provided that CET

- D3 inputs enter the flip-flops on the next

0

is Low,

)

LOGIC SYMBOL (IEEE/IEC)

9

1

10 7 2

3 4 5 6

when a counter reaches zero in the Count Down mode or reaches 15 in the Count Up mode. The TC the Count Enable Parallel (CEP derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC signal is not recommended (see logic equations below).

is

1) Count Enable = CEP⋅CET⋅PE

2) Up: TC = Q

3) Down: TC = Q

⋅(U/D)⋅CET

0⋅Q3

0⋅Q1⋅Q2⋅Q3

CTR DIV 16

M1 [LOAD] M2 [COUNT] M3 [UP] M4 [DOWN] G5

G6

2, 3, 5, 6+/C7

2, 4, 5, 6–

1, 7D

3, 5 CT=15

4, 5 CT=0

[1] [2] [4] [8]

15

14 13 12 11

SF00787

output state is not a function of

) input level. Since the TC signal is

. For this reason the use of TC as a clock

⋅(U/D)⋅CET

MODE SELECT — FUNCTION TABLE

INPUTS OUTPUTS

CP U/D CEP CET PE D

n

↑ X X X l l L (1) Parallel load (Dn→Qn) ↑

↑ ↑

X X X X X H (1) h l l h X Count Up (1) Count Up (increment)

l l l h X Count Down (1) Count Down (decrement)

X h X h X q X X X h X q

H = High voltage level steady state h = High voltage level one setup time prior to the Low-to-High clock transition L = Low voltage level steady state l = Low voltage level one setup time prior to the Low-to-High clock transition q = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition

(1)= The TC

is Low when CET is Low and the counter is at Terminal Count.

Terminal Count Up is (HHHH) and Terminal Count Down is (LLLL).

Q

n

n n

TC

(1) Hold (do nothing)

H

1996 Jan 05

3

Philips Semiconductors Product specification

OPERATING MODE

74F1694-bit up/down binary synchronous counter

MODE SELECT TABLE

INPUTS

PE CEP CET U/D

L X X X Load(Dn→Qn) H L L H Count Up (Increment) H L L L Count Down (Decrement) H H X X No Change (Hold) H X H X No Change (Hold)

H = High Voltage L = Low Voltage Level X = Don’t care

LOGIC DIAGRAM

3

D

0

STATE DIAGRAM

DCPQ

Q

01234

15

14

13

COUNT DOWN COUNT UP

5

6

7

89101112

14

Q

0

SF00788

VCC= Pin 16 GND = Pin 8

PE

CEP CET

CP

U/D

4

D

1

5

D

2

6

D

3

9

7

10

2

1

DCPQ

13

12

11

15

SF00789

Q

1

Q

2

Q

3

TC

Q

1996 Jan 05

4

Philips Semiconductors Product specification

74F1694-bit up/down binary synchronous counter

APPLICATION

CP

U/D

PE

D

0D1D2D3

PE U/D CP

CEP CET

Q0Q1Q2Q

LEAST SIGNIFICANT

4-BIT COUNTER

D

0D1D2D3

PE

U/D

TC

3

CP CEP

CET

Q0Q1Q2Q

TC

3

PE

U/D CP

CEP CET

D

0D1D2D3

Q0Q1Q2Q

Figure 1. Synchronous Multistage Counting Scheme

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)

SYMBOL

V

CC

V

IN

I

IN

V

OUT

I

OUT

T

amb

T

STG

Supply voltage –0.5 to +7.0 V Input voltage –0.5 to +7.0 V Input current –30 to +5 mA Voltage applied to output in High output state –0.5 to +V Current applied to output in Low output state 40 mA Operating free-air temperature range 0 to +70 °C Storage temperature –65 to +150 °C

PARAMETER RATING UNIT

D

0D1D2D3

PE

U/D

TC

3

CP CEP

CET

Q0Q1Q2Q

CC

MOST SIGNIFICANT

4-BIT COUNTER

TC

3

SF00790

V

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT

Min Nom Max

V

CC

V

IH

V

IL

I

IK

I

OH

I

OL

T

amb

1996 Jan 05

Supply voltage 4.5 5.0 5.5 V High-level input voltage 2.0 V Low-level input voltage 0.8 V Input clamp current –18 mA High-level output current –1 mA Low-level output current 20 mA Operating free-air temperature range 0 70 °C

5

Philips Semiconductors Product specification

NO TAG

VOHHigh-level output voltage

CC

,

IL

,

VOLLow-level output voltage

CC

,

IL

,

IILLow-level input current

74F1694-bit up/down binary synchronous counter

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

LIMITS

SYMBOL PARAMETER TEST CONDITIONS

MIN

TYP

NO TAG

MAX

UNIT

p

V

IK

I

IH

I

OS

I

CC

Input clamp voltage VCC = MIN, II = I Input current at maximum input

voltage High-level input current VCC = MAX, VI = 2.7V 20 µA

p

Short-circuit output current Supply current (total)

CET VCC = MAX, VI = 0.5V –1.2 mA Others VCC = MAX, VI = 0.5V –0.6 mA

NO TAG

4

VCC = MIN, VIL = MAX, VIH = MIN, I

OH

= MAX

VCC = MIN, VIL = MAX, VIH = MIN, I

OL

= MAX

IK

VCC = MAX, VI = 7.0V 100 µA

VCC = MAX –60 –150 mA VCC = MAX 35 52 mA

±10%V

±5%V

±10%V

±5%V

2.5 V

CC

2.7 3.4 V

CC

0.35 0.50 V

–0.73 –1.2 V

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

3. Not more than one output should be shorted at a time. For testing I

= 5V, T

CC

techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting

amb

= 25°C.

, the use of high-speed test apparatus and/or sample-and-hold

OS

of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I

is measured after applying a momentary 4.5V , then ground to the clock input with all other inputs grounded and all outputs open.

4. I

CC

tests should be performed last.

OS

1996 Jan 05

6

Philips Semiconductors Product specification

74F1694-bit up/down binary synchronous counter

AC ELECTRICAL CHARACTERISTICS

LIMITS

T

= +25°C T

amb

SYMBOL PARAMETER TEST CONDITIONS VCC = +5V VCC = +5V ± 10% UNIT

CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω

MIN TYP MAX MIN MAX

f

MAX

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

Maximum clock frequency Waveform 1 100 115 90 MHz Propagation delay

CP to Q

(PE, High or Low)

n

Propagation delay CP to TC

Propagation delay CET to TC

Propagation delay U/D to TC

Waveform 1

Waveform 2

Waveform 3

3.0

4.0

5.5

4.0

2.5

3.5

4.0

6.5

9.0

12.0

8.5

4.5

6.0

8.5

8.0

8.5

11.5

15.5

11.0

6.0

8.0

15.0

10.5

AC SETUP REQUIREMENTS

LIMITS LIMITS

T

= +25°C T

SYMBOL PARAMETER TEST CONDITIONS VCC = +5.0V VCC = +5.0V ± 10% UNIT

ts(H) ts(L)

th(H) th(L)

ts(H) ts(L)

th(H) th(L)

ts(H) ts(L)

th(H) th(L)

ts(H) t

(L)

s

th(H) th(L)

tw(H) tw(L)

Setup time, High or Low Dn to CP

Hold time, High or Low Dn to CP

Set-up time, High or Low CEP or CET to CP

Hold time, High or Low CEP or CET to CP

Set-up time, High or Low PE to CP

Hold time, High or Low PE to CP

Set-up time, High or Low U/D

to CP

Hold time, High or Low U/D to CP

CPU or CPD pulse width, High or Low

Waveform 4

Waveform 5

Waveform 4

Waveform 6

Waveform 1

amb

CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω

MIN TYP MIN MAX

4.0

3.0

5.0

5.0 0

0

8.0

8.0 0

0

11.0

7.0 0

0

5.0

= 0°C to +70°C

amb

3.0

4.0

5.5

4.0

2.5

3.5

4.0

= 0°C to +70°C

amb

4.5

3.5

5.5

5.5 0

0

9.0

9.0 0

0

12.5

8.0 0

0

5.5

9.5

13.0

17.0

12.5

7.0

9.0

15.5

12.0

ns ns

1996 Jan 05

7

Philips Semiconductors Product specification

74F1694-bit up/down binary synchronous counter

AC WAVEFORMS

For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance.

1/f

MAX

CP

Q

TC

V

M

tW(H)

t

PLH

n

t

PHL

V

M

tW(L)

V

M

V

M

t

PHL

PLH

V

M

V

M

V

M

SF00791A

Waveform 1. Propagation Delay, Clock Input to Output,

Clock Pulse Width, and Maximum Clock Frequency

CET

TC

Waveform 2. Propagation Delays CET Input to

D

n

V

M

t

PHL

V

M

Terminal Count Output

V

t

V

M

s

M

t

h

V

M

t

PLH

V

M

SF00792

U/D

V

M

t

PHL

TC

V

M

t

PLH

M

Waveform 3. Propagation Delay U/D Input to

Terminal Count Output

CET

CEP

CPn

Q

n

V

M

ts(L)

NO CHANGE

V

M

th(L) th(H)

V

M

V

M

COUNT

Waveform 5. Count Enable Setup and Hold Times

V

M

ts(H)

V

M

SF00793

PE

CPn

V

MVM

ts(L) ts(H)th = 0

V

M

VMV

M

th = 0

V

M

SF00794

Waveform 4. Parallel Data and Parallel Enable

Setup and Hold Times

V

M

V

M

NO

V

M

CHANGE

U/D

CPn

Q

n

M

ts(L)

V

M

th(L) th(H)

V

M

COUNT UPCOUNT DOWN

SF00795

V

M

ts(H)

V

M

SF00796

Waveform 6. Up/Down Control Setup and Hold Times

1996 Jan 05

8

Philips Semiconductors Product specification

74F1694-bit up/down binary synchronous counter

TIMING DIAGRAM (Typical Load, Count, and Inhibit Sequences)

PE

D

0

D

1

D

2

D

3

CP

U/D

CEP and CET

Q

0

Q

1

Q

2

Q

3

TC

789012 210987

}

LOAD

COUNT UP COUNT DOWNINHIBIT

NOTES:

The operation of the 74F169 is similar to the Illustration above.

1. Load (preset) to BCD seven

2. Count up to eight, nine (maximum), zero, one, and two

3. Inhibit

4. Count down to one, zero (minimum), nine, eight, and seven

TEST CIRCUIT AND WAVEFORM

V

CC

V

PULSE

GENERATOR

IN

R

T

Test Circuit for Totem-Pole Outputs

DEFINITIONS:

R

= Load resistor;

L

see AC ELECTRICAL CHARACTERISTICS for value.

C

= Load capacitance includes jig and probe capacitance;

L

see AC ELECTRICAL CHARACTERISTICS for value.

R

= Termination resistance should be equal to Z

T

pulse generators.

D.U.T.

V

OUT

R

C

L

of

OUT

NEGATIVE PULSE

POSITIVE PULSE

family

74F

2SEQUENCE

90%

10%

amplitude

SF00797

t

w

V

M

10%

)

t

THL (tf

)

t

TLH (tr

90%

V

M

t

TLH (tr

t

THL (tf

t

w

Input Pulse Definition

INPUT PULSE REQUIREMENTS

V

rep. rate

M

3.0V 1.5V

1MHz 500ns

10%

)

90%

t

V

M

V

M

w

90%

10%

t

TLHtTHL

2.5ns 2.5ns

AMP (V)

0V

AMP (V)

0V

1996 Jan 05

SF00006

9

Philips Semiconductors Product specification

74F168*, 74F1694-bit up/down binary synchronous counter

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.

1996 Jan 05

10

Philips Semiconductors Product specification

74F168*, 74F1694-bit up/down binary synchronous counter

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.

1996 Jan 05

11

Philips Semiconductors Product specification

74F168*, 74F1694-bit up/down binary synchronous counter

DEFINITIONS

Data Sheet Identification Product Status Definition

Objective Specification

Preliminary Specification

Product Specification

Formative or in Design

Preproduction Product

Full Production

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

LIFE SUPPORT APPLICA TIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected

to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.

This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.

Philips Semiconductors and Philips Electronics North America Corporation

register eligible circuits under the Semiconductor Chip Protection Act.

 Copyright Philips Electronics North America Corporation 1996

(print code) Date of release: July 1994 Document order number: 9397-750-05087