Datasheet 74alvt16821 DATASHEETS (Philips)

INTEGRATED CIRCUITS

74ALVT16821

20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

Product specification Supersedes data of 1997 May 01 IC24 Data Handbook

 

1998 Feb 13

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

FEA TURES

•20-bit positive-edge triggered register

•5V I/O Compatible

•Multiple V

and GND pins minimize switching noise

CC

•Live insertion/extraction permitted

•Power-up reset

•Power-up 3-State

•Output capability: +64mA/-32mA

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

•Bus hold data inputs eliminate the need for external pull-up

resistors to hold unused inputs

QUICK REFERENCE DATA

C

t

PLH

t

PHL

C

OUT

I

CCZ

IN

Propagation delay nCP to nQ

Input capacitance VI = 0V or V Output capacitance VO = 0 or V Total supply current Outputs disabled 40 70 µA

CL = 50pF

DESCRIPTION

The 74ALVT16821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. It is designed for V compatibility to 5V .

The 74ALVT16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE

Each register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output.

The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors.

The active Low Output Enable (nOE independent of the register operation. When nOE the register appears at the outputs. When nOE are in high impedance “off” state, which means they will neither drive nor load the bus.

CONDITIONS

T

CC

amb

= 25°C

CC

) control gates.

74AL VT16821

operation at 2.5V or 3.3V with I/O

) controls all ten 3-State buffers

is Low, the data in

is High, the outputs

TYPICAL

2.5V 3.3V

2.6

2.7 3 3 pF 9 9 pF

1.7

1.8

ns

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

56-Pin Plastic SSOP Type III –40°C to +85°C 74ALVT16821 DL AV16821 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVT16821 DGG AV16821 DGG SOT364-1

1998 Feb 13 853-1869 18962

2

Philips Semiconductors Product specification

2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

LOGIC SYMBOL

56 54 52 51 49 48 47 45 44 43

1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7

1CP

56

1OE

1

1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7

2 3 5 6 8 9 10 12 13 14

42 41 40 38 37 36 34 33 31 30

2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7

29

2CP

28

2OE

2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7

15 16 17 19 20 21 23 24 26 27

LOGIC SYMBOL (IEEE/IEC)

1OE

1CP

2OE

2CP

1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8

1D9 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9

1 56 28 29

55 54 52 51 49 48 47 45 44

43 42 41 40 38 37 36 34 33 31 30

EN2

C1

EN4

C3

1D

3D

2 ∇

4 ∇

1D8 1D9

1Q8 1Q9

2D8 2D9

2Q8 2Q9

SH00002

2 3 5 6 8

9 10 12 13 14 15 16 17 19 20 21 23 24 26 27

SH00003

1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8

1Q9 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9

PIN CONFIGURATION

1 2

1Q0

3

1Q1

4

GND

5

1Q2

6

1Q3

7

V

CC

8

1Q4

9

1Q5

10

1Q6

11

GND

12

1Q7

13

1Q8

14

1Q9

15

2Q0

16

2Q1

17

2Q2

18

GND

19

2Q3

20

2Q4

21

2Q5

22

V

CC

23

2Q6

24

2Q7

25

GND

26

2Q8

27

2Q9

28 29

2OE

74ALVT16821

561OE

1CP

55

1D0

54

1D1

53

GND

52

1D2

51

1D3

50

V

CC

49

1D4

48

1D5

47

1D6

46

GND

45

1D7

44

1D8

43

1D9

42

2D0

41

2D1

40

2D2

39

GND

38

2D3

37

2D4

36

2D5

35

V

CC

34

2D6

33

2D7

32

GND

31

2D8

30

2D9 2CP

SH00001

1998 Feb 13

3

Philips Semiconductors Product specification

INTERNAL

OPERATING

2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

56, 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37,

36, 34, 33, 31, 30

2, 3, 5, 6, 8, 9, 10,

12, 13, 14,

15, 16, 17, 19, 20,

21, 23, 24, 26, 27

1, 28 1OE, 2OE

56, 29 1CP, 2CP

4, 11, 18, 25, 32,

39, 46, 53

7, 22, 35, 50 V

LOGIC DIAGRAM

1D0 - 1D9 2D0 - 2D9

1Q0 - 1Q9 2Q0 - 2Q9

Data inputs

Data outputs

Output enable inputs (active-Low)

Clock pulse inputs (active rising edge)

GND Ground (0V)

CC

Positive supply voltage

74ALVT16821

FUNCTION TABLE

INPUTS

nOE nCP nDx

L

↑

L

↑

l

h

INTERNAL REGISTER

L

H

L ↑ X NC NC Hold

H

↑

H

↑XDn

NC

Dn

H = High voltage level h = High voltage level one set-up time prior to the Low-to-High

clock transition L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High

clock transition NC= No change X = Don’t care Z = High impedance “off” state ↑ = Low to High clock transition

= Not a Low-to-High clock transition

↑

OUTPUTS nQ0 - nQ9

L

H

Z Z

OPERATING

MODE

Load and read

register

Disable outputs

nCP

nOE

nD0

D

CP Q

nQ0

nD1

D

CP Q

nQ1

nD2

D

CP Q

nQ2

nD3

D

CPQ

nQ3

nD4

D

CP Q

nQ4

nD5

D

CPQ

nQ5

nD6

D

CP Q

nQ6

nD7

D

CPQ

nQ7

nD8

D

CPQ

nQ8

nD9

D

CPQ

nQ9

SH00004

1998 Feb 13

4

Philips Semiconductors Product specification

I

DC output current

mA

SYMBOL

PARAMETER

UNIT

I

mA

2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

ABSOLUTE MAXIMUM RATINGS

SYMBOL

V

I V

I

OK

OUT

T

CC

IK

stg

DC supply voltage –0.5 to +4.6 V DC input diode current VI < 0 –50 mA DC input voltage

I

DC output diode current VO < 0 –50 mA DC output voltage

p

Storage temperature range –65 to 150 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

PARAMETER CONDITIONS RATING UNIT

3

1, 2

Output in Off or High state –0.5 to +7.0 V

Output in Low state 128

Output in High state –64

74ALVT16821

–1.2 to +7.0 V

RECOMMENDED OPERATING CONDITIONS

2.5V RANGE LIMITS 3.3V RANGE LIMITS MIN MAX MIN MAX

V

CC

V

I

OH

OL

∆t/∆v Input transition rise or fall rate; Outputs enabled 10 10 ns/V

T

amb

DC supply voltage 2.3 2.7 3.0 3.6 V Input voltage 0 5.5 0 5.5 V

I

High-level input voltage 1.7 2.0 V

IH

Input voltage 0.7 0.8 V

IL

High-level output current –8 –32 mA Low-level output current 8 32 Low-level output current; current duty cycle ≤ 50%; f ≥ 1kHz 24 64

Operating free-air temperature range –40 +85 –40 +85 °C

1998 Feb 13

5

Philips Semiconductors Product specification

VOHHigh-level out ut voltage

V

VOLLow–level out ut voltage

V

IIIn ut leakage current

4

µA

Data ins

4

Bus Hold current

Data inputs

7

2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

DC ELECTRICAL CHARACTERISTICS (3.3V 0.3V RANGE)

SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT

V

RST

I

OFF

I

HOLD

I

EX

I

PU/PD

I

OZH

I

OZL

I

CCH

I

CCL

I

CCZ

∆I

NOTES:

1. All typical values are at V

2. This is the increase in supply current for each input at the specified voltage level other than V

3. This parameter is valid for any V transition time of 100µsec is permitted. This parameter is valid for T

4. Unused pins at V

5. I

CCZ

6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.

7. This is the bus hold overdrive current required to force the input to the opposite logic state.

Input clamp voltage VCC = 3.0V; IIK = –18mA –0.85 –1.2 V

IK

p

VCC = 3.0 to 3.6V; IOH = –100µA VCC–0.2 V VCC = 3.0V; IOH = –32mA 2.0 2.3 VCC = 3.0V; IOL = 100µA 0.07 0.2

p

VCC = 3.0V; IOL = 16mA 0.25 0.4 VCC = 3.0V; IOL = 32mA 0.3 0.5 VCC = 3.0V; IOL = 64mA 0.4 0.55

Power-up output low voltage6VCC = 3.6V; IO = 1mA; VI = VCC or GND 0.55 V

VCC = 3.6V; VI = VCC or GND Control pins 0.1 ±1

p

VCC = 0 or 3.6V; VI = 5.5V 0.1 10 VCC = 3.6V; VI = V VCC = 3.6V; VI = 0V

CC

p

Off current VCC = 0V; VI or VO = 0 to 4.5V 0.1 ±100 µA

VCC = 3V; VI = 0.8V 75 130

p

Current into an output in the High state when VO > V

Power up/down 3-State output

3

current

CC

3-State output High current VCC = 3.6V; VO = 3.0V; VI = VIL or V 3-State output Low current VCC = 3.6V; VO = 0.5V; VI = VIL or V

Quiescent supply current VCC = 3.6V; Outputs Low, VI = GND or V

Additional supply current per

CC

is measured with outputs pulled up to VCC or pulled down to ground.

input pin

2

or GND.

CC

= 3.3V and T

CC

between 0V and 1.2V with a transition time of up to 10msec. From V

VCC = 3V; VI = 2.0V –75 –140 VCC = 0V to 3.6V; VCC = 3.6V ±500

VO = 5.5V; VCC = 3.0V 10 125 µA VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or V

OE/OE = Don’t care

IH IH

VCC = 3.6V; Outputs High, VI = GND or V

VCC = 3.6V; Outputs Disabled; VI = GND or V

CC

I

0 0.07 0.1

CC,

O =

I

0 5.1 7 mA

CC,

O =

CC,

5

I

0

O =

VCC = 3V to 3.6V; One input at VCC–0.6V, Other inputs at VCC or GND

= 25°C.

amb

= 25°C only.

amb

or GND

CC

74ALVT16821

LIMITS

MIN TYP1MAX

CC

0.5 1

0.1 -5

1 ±100 µA

0.5 5 µA

0.5 –5 µA

0.07 0.1

0.04 0.4 mA

= 1.2V to VCC = 3.3V ± 0.2V a

µA

AC CHARACTERISTICS (3.3V 0.3V RANGE)

GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; T

f

MAX

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

NOTE:

1. All typical values are at V

1998 Feb 13

= –40°C to +85°C.

amb

SYMBOL PARAMETER WAVEFORM

Maximum clock frequency 1 150 MHz Propagation delay

nCP to nQx Output enable time

to High and Low level Output disable time

from High and Low level

= 3.3V and T

CC

amb

= 25°C.

1 3

4 3

4

6

LIMITS

T

= –40 to +85oC

amb

VCC = +3.3V

MIN TYP MAX

0.5

1.0

0.5

1.5

1.7

1.8

2.1

1.4

2.9

2.4

3.2

3.5

2.4

4.2

3.4

UNIT

ns

Philips Semiconductors Product specification

VOHHigh-level out ut voltage

V

IIIn ut leakage current

4

µA

Data ins

4

HOLD

µA

2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

AC SETUP REQUIREMENTS (3.3V 0.3V RANGE)

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

LIMITS

T

= -40 to +85oC

SYMBOL PARAMETER WAVEFORM

ts(H) ts(L)

th(H) th(L)

tw(H) tw(L)

Setup time, High or Low nDx to nCP

Hold time, High or Low nDx to nCP

nCP pulse width High or Low

2

1

DC ELECTRICAL CHARACTERISTICS (2.5V 0.2V RANGE)

SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT

V

RST

I

OFF

I

HOLD

I

EX

I

PU/PD

I

OZH

I

OZL

I

CCH

I

CCL

I

CCZ

∆I

NOTES:

1. All typical values are at V

2. This is the increase in supply current for each input at the specified voltage level other than V

3. This parameter is valid for any V transition time of 100µsec is permitted. This parameter is valid for T

4. Unused pins at V

5. I

CCZ

6. Not guaranteed.

7. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.

Input clamp voltage VCC = 2.3V; IIK = –18mA –0.85 –1.2 V

IK

p

VCC = 2.3 to 3.6V; IOH = –100µA VCC–0.2 V VCC = 2.3V; IOH = –8mA 1.8 2.1 VCC = 2.3V; IOL = 100µA 0.07 0.2

Low-level output voltage

OL

VCC = 2.3V; IOL = 24mA 0.3 0.5 VCC = 2.3V; IOL = 8mA 0.4

Power-up output low voltage7VCC = 2.7V; IO = 1mA; VI = VCC or GND 0.55 V

VCC = 2.7V; VI = V

p

VCC = 0 or 2.7V; VI = 5.5V 0.1 10 VCC = 2.7V; VI = V

or GND Control pins 0.1 ±1

CC

VCC = 2.7V; VI = 0 Off current VCC = 0V; VI or VO = 0 to 4.5V 0.1 100 µA Bus Hold current VCC = 2.3V; VI = 0.7V 90 Data inputs Current into an output in the

High state when VO > V Power up/down 3-State output

current 3-State output High current VCC = 2.7V; VO = 2.3V; VI = VIL or V 3-State output Low current VCC = 2.7V; VO = 0.5V; VI = VIL or V

Quiescent supply current VCC = 2.7V; Outputs Low, VI = GND or V

6

CC

3

VCC = 2.3V; VI = 1.7V –10

VO = 5.5V; VCC = 2.3V 10 125 µA

VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or V

OE/OE = Don’t care

IH IH

VCC = 2.7V; Outputs High, VI = GND or V

CC,

I

VCC = 2.7V; Outputs Disabled; VI = GND or V Additional supply current per

CC

is measured with outputs pulled up to VCC or pulled down to ground.

input pin

2

or GND.

CC

= 2.5V and T

CC

between 0V and 1.2V with a transition time of up to 10msec. From V

VCC = 2.3V to 2.7V; One input at VCC–0.6V,

Other inputs at VCC or GND

= 25°C.

amb

= 25°C only.

amb

VCC = +3.3V ±0.3V

MIN TYP

1.5

0.5

1.5

p

CC

I

0 0.04 0.1

O =

0 2.3 4.5 mA

O =

CC,

I

O =

or GND

CC

5

0

CC

74ALVT16821

UNIT

0.1

LIMITS

MIN TYP1MAX

CC

0.1 1

0.1 -5

1 100 µA

0.5 5 µA

0.5 –5 µA

0.04 0.1

0.04 0.4 mA

= 1.2V to VCC = 2.5V ± 0.3V a

ns

V

1998 Feb 13

7

Philips Semiconductors Product specification

2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

AC CHARACTERISTICS (2.5V "0.2V RANGE)

GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; T

SYMBOL PARAMETER WAVEFORM

f

MAX

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

Maximum clock frequency 1 150 MHz Propagation delay

nCP to nQx Output enable time

to High and Low level Output disable time

from High and Low level

NOTE:

1. All typical values are at V

= 3.3V and T

CC

amb

AC SETUP REQUIREMENTS (2.5V "0.2V RANGE)

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORM

ts(H) ts(L)

th(H) th(L)

tw(H) tw(L)

Setup time, High or Low nDx to nCP

Hold time, High or Low nDx to nCP

nCP pulse width High or Low

= –40°C to +85°C.

amb

= 25°C.

1 3

4 3

4

74ALVT16821

LIMITS

T

= -40 to +85oC

amb

VCC = +2.5V ±0.2V

MIN TYP MAX

1.0

1.5

1.0

1.5

1.0

2.6

2.7

2.8

1.8

2.7

2.1

4.0

4.4

4.6

3.0

4.1

3.3

LIMITS

T

= -40 to +85oC

amb

VCC = +2.5 ±0.2V

MIN TYP

2

1

1.5

2.0

0.3

0.5

1.5

0.1

0.5

–0.5 –0.1

UNIT

ns

UNIT

ns

AC WAVEFORMS

VM = 1.5V at VCC w 3.0V; VM = VCC/2 at VCC v 2.7V

= VOL + 0.3V at VCC w 3.0V; VX = VOL + 0.15V at VCC v 2.7V

V

X

V

= VOH – 0.3V at VCC w 3.0V; VY = V

Y

1/f

MAX

nCP

nQx

V

M

tw(H)

t

PH

V

M

L

tw(L)

V

M

V

Waveform 1. Propagation Delay, Clock Input to Output,

Clock Pulse Width, and Maximum Clock frequency

– 0.15V at VCC v 2.7V

OH

3.0V or V whichever

M

t

PLH

V

M

is less

0V

V

OH

V

OL

SH00005

3.0V or V

CC

whichever

V

CC

nDx

CP

V

M

th(H)ts(H)

V

M

V

M

th(L)ts(L)

V

M

is less

0V

3.0V or V whichever is less

0V

SH00006

CC

Waveform 2. Data Setup and Hold Times

1998 Feb 13

8

Philips Semiconductors Product specification

2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

3.0V or V

nOE

V

M

t

PHZ

V

OH

V

M

Y

nQx

V

M

t

PZH

Waveform 3. 3-State Output Enable Time to High Level

and Output Disable Time from High Level

TEST CIRCUIT AND WAVEFORM

V

CC

PULSE

GENERATOR

V

IN

D.U.T.

R

T

V

OUT

C

L

Test Circuit for 3-State Outputs

SWITCH POSITION

TEST SWITCH

t

PLZ/tPZL

t

PLH/tPHL

t

PHZ/tPZH

6V or V

Open

GND

CC x 2

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value. C

= Load capacitance includes jig and probe capacitance:

L

See AC CHARACTERISTICS for value.

= Termination resistance should be equal to Z

R

T

pulse generators.

OUT

whichever is less

0V

SH00007

R

L

R

L

of

CC

6.0V or VCC x 2

Open

GND

FAMILY

74ALVT16

74ALVT16821

nOE

V

M

t

PZL

nQx

Waveform 4. 3-State Output Enable Time to Low Level

and Output Disable Time from Low Level

90%

NEGATIVE PULSE

POSITIVE PULSE

10%

V

M

10% 10%

t

(tF)

THL

t

(tR)t

TLH

90% 90%

V

M

INPUT PULSE REQUIREMENTS

Amplitude Rep. Rate t

3.0V or V whichever

CC

v10MHz 500ns

is less

V

M

t

PLZ

V

M

t

W

V

t

W

V

X

V

OL

90%

M

t

TLH

THL

M

10%

t

R

v2.5ns v2.5ns

3.0V or V whichever is less

0V

3.0V or V

0V

SH00008

V

IN

0V

(tR)

(tF)

V

IN

0V

t

F

SW00025

CC

1998 Feb 13

9

Philips Semiconductors Product specification

20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1

74ALVT16821

1998 Feb 13

10

Philips Semiconductors Product specification

20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1

74ALVT16821

1998 Feb 13

11

Philips Semiconductors Product specification

20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

74ALVT16821

NOTES

1998 Feb 13

12

Philips Semiconductors Product specification

20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

74ALVT16821

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 05-96 Document order number: 9397-750-03574

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