Datasheet 74alvch16821 DATASHEETS (Philips)

INTEGRATED CIRCUITS

74ALVCH16821

20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

Product specification IC24 Data Handbook

 

1998 May 29

Philips Semiconductors Product specification

CPDPower dissipation capacitance per buffer

V

GND to V

1

pF

20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

FEA TURES

•Wide supply voltage range of 1.2V to 3.6V

•Complies with JEDEC standard no. 8-1A

•Current drive ± 24 mA at 3.0 V

•CMOS low power consumption

•Direct interface with TTL levels

•MULTIBYTE

•Low inductance multiple V

and ground bounce

•All data inputs have bus hold

•Output drive capability 50Ω transmission lines @ 85°C

QUICK REFERENCE DATA

GND = 0V; T

SYMBOL

t

PHL/tPLH

C

I

F

max

NOTE:

1. C P f

= input frequency in MHz; CL = output load capacitance in pF;

i

f

o

 (C

TM

flow-through standard pin-out architecture

and ground pins for minimum noise

CC

= 25°C; tr = tf ≤ 2.5ns

amb

PARAMETER CONDITIONS TYPICAL UNIT

Propagation delay nCP to nQ

Input capacitance 5.0 pF

Maximum clock frequency

is used to determine the dynamic power dissipation (PD in W):

PD

= CPD × V

D

= output frequency in MHz; VCC = supply voltage in V;

L

CC

2

× V

× fo) = sum of outputs.

CC

n

p

2

× fi +  (CL × V

p

2

× fo) where:

CC

p

DESCRIPTION

The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE

Each register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output.

When nOE When nOE Operation of the nOE

The 74ALVCH16821 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF

=

I

VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF

CC

74AL VCH16821

) control gates.

is LOW, the data in the register appears at the outputs. is HIGH, the outputs are in high impedance OFF state.

input does not affect the state of the flip-flops.

2.6

2.5

Outputs enabled 33 Outputs disabled 17

250 350

ns

p

MHz

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

56-Pin Plastic SSOP Type III –40°C to +85°C 74ALVCH16821 DL ACH16821 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVCH16821 DGG ACH16821 DGG SOT364-1

1998 May 29 853-2066 19467

2

Philips Semiconductors Product specification

Data in uts

Data out uts

20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

55, 54, 52, 51, 49,

48, 47, 45, 44, 43

42, 41, 40, 38, 37,

36, 34, 33, 31, 30

2, 3, 5, 6, 8,

9, 10, 12, 13, 14

15, 16, 17, 19, 20,

21, 23, 24, 26, 27

1, 28 1OE, 2OE

56, 29 1CP, 2CP

4, 11, 18, 25,

32, 39, 46, 53

7, 22, 35, 50 V

PIN CONFIGURATION

1D0 - 1D9

2D0 - 2D9

1Q0 - 1Q9

2Q0 - 2Q9

1

1Q0

2

1Q1

3

GND

4

1Q2

5

1Q3

6

V

7

CC

1Q4

8

1Q5

9

1Q6

10

GND

11

1Q7

12

1Q8

13

1Q9

14

2Q0

15

2Q1

16

2Q2

17

GND

18

2Q3

19

2Q4

20

2Q5

21

V

22

CC

23

2Q6

24

2Q7

25

GND

26

2Q8

27

2Q9

28 29

2OE

p

Output enable inputs (active-Low)

Clock pulse inputs (active rising edge)

GND Ground (0V)

CC

Positive supply voltage

561OE

1CP

55

1D0

54

1D1

53

GND

52

1D2

51

1D3

50

V

CC

1D4

49

1D5

48

1D6

47

GND

46

1D7

45

1D8

44

1D9

43

2D0

42

2D1

41

2D2

40

GND

39

2D3

38

2D4

37

2D5

36

V

35

CC

34

2D6

33

2D7

32

GND

31

2D8

30

2D9 2CP

74ALVCH16821

FUNCTION TABLE

INPUTS OUTPUT

nOE CP Dx Q

L ↑ L L L ↑ H H L



H X X Z

H = HIGH voltage level L = LOW voltage level X = Don’t care Z = High impedance OFF state ↑ = LOW to HIGH clock transition  = Not a LOW-to-HIGH clock transition

LOGIC SYMBOL

2

1Q0

1Q1

3

1Q2

5 6

1Q3 1Q4

8

1Q5

9

1Q6

10

1Q7

12 13

1Q8

14

1Q9

2Q0

15

2Q1

16

2Q2

17

2Q3

19 20

2Q4

21

2Q5 2Q6

23 24

2Q7 2Q8

26

2Q9

27

X Q0

1

2OE

56

1CP1OE

2CP

2928

1D0

1D1 1D2

1D3 1D4

1D5 1D6

1D7 1D8

1D9 2D0

2D1 2D2

2D3 2D4

2D5 2D6

2D7 2D8

2D9

55

54 52 51 49 48 47 45 44 43

42 41 40

38 37

36 34

33 31 30

SH00127

1998 May 29

SH00001

3

Philips Semiconductors Product specification

20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

LOGIC SYMBOL (IEEE/IEC)

1OE

1CP

2OE

2CP

1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8

1D9 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9

1 56 28 29

55 54 52 51 49 48 47 45 44

43 42 41 40 38 37 36 34 33 31 30

EN2

EN4

1D

3D

C1

C3

2 ∇

4 ∇

2 3 5 6 8

9 10 12 13 14 15 16 17 19 20 21 23 24 26 27

SH00003

1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8

1Q9 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9

74ALVCH16821

LOGIC DIAGRAM

nD0

D

CP Q

nCP

nOE

nQ0

nD1

D

CP Q

nQ1

nD2

D

CP Q

nQ2

nD3

D

CPQ

nQ3

nD4

D

CP Q

nQ4

nD5

D

CPQ

nQ5

nD6

D

CP Q

nQ6

nD7

D

CPQ

nQ7

nD8

D

CPQ

nQ8

nD9

D

CPQ

nQ9

SH00004

1998 May 29

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Philips Semiconductors Product specification

SYMBOL

PARAMETER

CONDITIONS

UNIT

V

DC in ut voltage

V

20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

RECOMMENDED OPERATING CONDITIONS

MIN MAX

DC supply voltage 2.5V range (for max. speed performance @ 30 pF output load)

CC

DC supply voltage 3.3V range (for max. speed performance @ 50 pF output load)

T

V

amb

tr, t

O

DC Input voltage range 0 V

I

DC output voltage range 0 V Operating free-air temperature range –40 +85 °C

Input rise and fall times

f

VCC = 2.3 to 3.0V VCC = 3.0 to 3.6V

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V)

SYMBOL

I

GND

V

CC

I

IK

I

OK

V

O

I

O

, I

T

stg

DC supply voltage –0.5 to +4.6 V DC input diode current VI 0 –50 mA

DC output diode current V DC output voltage Note 1 –0.5 to VCC +0.5 V DC output source or sink current VO = 0 to V DC VCC or GND current 100 mA

CC

Storage temperature range –65 to +150 °C Power dissipation per package

P

TOT

–plastic medium-shrink (SSOP) –plastic thin-medium-shrink (TSSOP)

NOTE:

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

PARAMETER CONDITIONS RATING UNIT

p

For control pins For data inputs

VCC or VO  0 50 mA

O

1

CC

For temperature range: –40 to +125 °C above +55°C derate linearly with 11.3 mW/K above +55°C derate linearly with 8 mW/K

2.3 2.7

3.0 3.6

0 0

74ALVCH16821

LIMITS

CC CC

20 10

–0.5 to +4.6

–0.5 to VCC +0.5

50 mA

850 600

V V

ns/V

mW

1998 May 29

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Philips Semiconductors Product specification

VIHHIGH level Input voltage

V

VILLOW level Input voltage

V

I

100µA

V

0.2

V

VOHHIGH level output voltage

V

I

100µA

GND

0.20

V

µ

I

g

V

GND

µ

I

Bus hold LOW sustaining current

A

I

Bus hold HIGH sustaining current

A

20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions. V oltage are referenced to GND (ground = 0 V).

SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT

p

V

I

OZ

I

CC

∆I

BHL

BHH

I

BHLO

I

BHHO

LOW level output voltage

OL

I

Input leakage current

I

3-State output OFF-state current Quiescent supply current VCC = 2.3 to 3.6V; VI = VCC or GND; IO = 0 0.2 40 µA

Additional quiescent supply current VCC = 2.3V to 3.6V; VI = VCC – 0.6V; IO = 0 150 750 µA

CC

Bus hold LOW overdrive current VCC = 3.6V Bus hold HIGH overdrive current VCC = 3.6V

NOTES:

1. All typical values are at T

2. Valid for data inputs of bus hold parts.

amb

= 25°C.

VCC = 2.3 to 2.7V 1.7 1.2 VCC = 2.7 to 3.6V 2.0 1.5 VCC = 2.3 to 2.7V 1.2 0.7 VCC = 2.7 to 3.6V 1.5 0.8

= 2.3 to 3.6V;

CC

;

=

I

VCC = 2.3V; VI = VIH or VIL; IO = –6mA V VCC = 2.3V; VI = VIH or VIL; IO = –12mA V VCC = 2.7V; VI = VIH or VIL; IO = –12mA V VCC = 3.0V; VI = VIH or VIL; IO = –12mA V VCC = 3.0V; VI = VIH or V

= 2.3 to 3.6V;

CC

;

=

I

;

or

;

IH

IO = –24mA VCC1.0 V

IL;

or

IH

= –

IL

O

;

=

IL

O

CC

CC CC CC CC

VCC = 2.3V; VI = VIH or VIL; IO = 6mA 0.07 0.40 V VCC = 2.3V; VI = VIH or VIL; IO = 12mA 0.15 0.70 VCC = 2.7V; VI = VIH or VIL; IO = 12mA 0.14 0.40 VCC = 3.0V; VI = VIH or V

= 2.3 to 3.6V;

CC

=

or

I

CC

;

IO = 24mA 0.27 0.55

IL;

VCC = 2.7 to 3.6V; VI = VIH or VIL; VO = VCC or GND

VCC = 2.3V; VI = 0.7V VCC = 3.0V; VI = 0.8V VCC = 2.3V; VI = 1.7V VCC = 3.0V; VI = 2.0V

2 2

2 2 2 2

74ALVCH16821

LIMITS

MIN TYP



0.3 V



0.6 V



0.5 V



0.6 V



45 –

75 150 –45 –75 –175 500 µA

–500 µA

1

MAX

CC

0.08



CC

0.26



CC

0.14



CC

0.09



CC

0.28



CC

0.1 5

0.1 10 µA

V

A

µ

1998 May 29

6

Philips Semiconductors Product specification

20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

AC CHARACTERISTICS FOR VCC = 2.3V TO 2.7V RANGE

GND = 0V; tr = tf ≤ 2.0ns; CL = 30pF

SYMBOL PARAMETER WAVEFORM VCC = 2.5V ± 0.2V UNIT

MIN TYP

t

PLH/tPHL

t

PZH/tPZL

t

PHZ/tPLZ

t

W

t

SU

t

h

F

max

NOTE:

1. All typical values are at V

AC CHARACTERISTICS FOR VCC = 3.0V TO 3.6V RANGE AND VCC = 2.7V

GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF

SYMBOL PARAMETER WAVEFORM VCC = 3.3 ± 0.3V VCC = 2.7V UNIT

t

PHL/tPLH

t

PZH/tPZL

t

PHZ/tPLZ

t

W

t

SU

t

h

F

max

NOTES:

1. All typical values are at T

Propagation delay nCP to nQ

n

3-State output enable time nOEn to nQ

n

3-State output disable time nOEn to nQ

n

1, 4 1.0 2.6 5.8 ns

2, 4 1.0 2.8 6.6 ns

2, 4 1.0 2.2 5.7 ns

nCP pulse width HIGH or LOW 3, 4 3.0 1.8 ns Set up time nDn to nCP 3, 4 1.4 0.3 ns Hold time nDn to nCP 3, 4 0.4 0.0 ns Maximum clock pulse frequency 1, 4 150 250 MHz

= 2.5V and T

CC

amb

= 25°C.

LIMITS

1

MAX MIN TYP

Propagation delay nCP to nQ

n

3-State output enable time nOEn to nQ

n

3-State output disable time nOEn to nQ

n

nCP pulse width HIGH or LOW

MIN TYP

1, 4 1.0 2.5 4.5 1.0 2.8 5.3 ns

2, 4 1.0 2.3 5.1 1.0 3.2 6.2 ns

2, 4 1.0 2.8 4.6 1.0 3.1 5.0 ns

3, 4 3.3 0.2 3.3 1.7 ns

Set up time nDn to nCP 3, 4 1.0 0.2 1.2 0.3 ns Hold time nDn to nCP 3, 4 0.8 0.4 0.6 –0.3 ns Maximum clock pulse

frequency

= 25°C.

amb

1, 4 150 350 150 300 MHz

74ALVCH16821

LIMITS

1

MAX

1

MAX

1998 May 29

7

Philips Semiconductors Product specification

20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

AC WAVEFORMS

VCC = 2.3 TO 2.7 V RANGE

= 0.5 V

1. V

M

2. V

= VOL + 0.15V

X

= VOH – 0.15V

3. V

Y

4. V

= V

I

5. VOL and VOH are the typical output voltage drop that occur with

V

1. V

2. V

3. V

4. V

5. V

CC

the output load.

= 3.0 TO 3.6 V RANGE AND VCC = 2.7 V

CC

= 1.5 V

M

= VOL + 0.3V

X

= VOH – 0.3V

Y

= 2.7 V

I

and VOH are the typical output voltage drop that occur with

OL

the output load.

1/f

MAX

V

nCP INPUT

nQ

OUTPUT

n

GND

V

OH

V

I

OL

V

M

t

PHL

w

V

M

t

PLH

V

M

SH00128

Waveform 1. The input (nCP) to output propagation delays.

nCP INPUT

GND

nDn INPUT

GND

V

nQn OUTPUT

V

Waveform 3. Set up and hold times.

TEST CIRCUIT

PULSE GENERATOR

74ALVCH16821

V

I

V

M

t

su

t

V

I

OH

OL

V

I

R

T

V

M

V

CC

D.U.T.

h

V

t

su

t

h

V

M

SH00129

S

1

2 * V

CC

Open GND

O

C

L

RL = 500 Ω

V

I

nOE INPUT

GND

V

CC

OUTPUT LOW-to-OFF OFF-to-LOW

V

OL

V

OH

OUTPUT HIGH-to-OFF OFF-to-HIGH

GND

V

M

t

PLZ

t

outputs enabled

PHZ

t

PZL

V

X

t

PZH

V

Y

outputs disabled

Waveform 2. The 3-State enable and disable times.

V

M

V

M

outputs enabled

SW00308

Test Circuit for switching times

DEFINITIONS

RL = Load resistor C

= Load capacitance includes jig and probe capacitance

L

R

= Termination resistance should be equal to Z

T

of pulse generators.

OUT

SWITCH POSITION

TEST S

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

2  V

GND

V

1

CC

< 2.7V V

V

I

CC

2.7V2.7–3.6V

Waveform 4. Load circuitry for switching times

SV00906

1998 May 29

8

Philips Semiconductors Product specification

20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1

74ALVCH16821

1998 May 29

9

Philips Semiconductors Product specification

20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1

74ALVCH16821

1998 May 29

10

Philips Semiconductors Product specification

20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

74ALVCH16821

NOTES

1998 May 29

11

Philips Semiconductors Product specification

20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

74ALVCH16821

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 05-96 Document order number: 9397-750-04553

 

1998 May 29

12