Datasheet 74ALVC162838 Datasheet (Fairchild Semiconductor)

November 2001
Revised November 2001

74ALVC162838
Low Voltage 16-Bit Selectable Register /Buffer

with 3.6V Tolerant Inputs/Outputs
and 26

Ω Series Resistors in the Outputs

Resistors in the Outputs

74ALVC162838 Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs/Outputs and 26

General Description

The ALVC162838 contains sixteen non-inverting selectable
buffered or registered pa ths. T he dev ic e can be c onfi g ur ed
to operate in a regis tered, or flow throu gh buffer mode by
utilizing the register enable (REGE) and Clock (CLK) sig­nals. The device operates in a 16-bit word wide mode. All
outputs can be plac ed into 3-State through the use of the
OE

pin. These devices are ideally suited for buffered or
registered 168 pin and 200 pin SDRAM DIMM memory
modules.

The 74ALVC162838 is designed for l ow voltage (1.6 5V to

3.6V) V
The ALVC162838 is also designed with 26

tors in the outputs. This design reduces line noise in appli­cations such as memory address drivers, clock drivers, and
bus transceivers/transmitters.

The 74ALVC162838 is fabricated with an adva nce d CMOS
technology to achieve high speed operation while maintain­ing low CMOS power dissipation.

applications with I/O compatibility up to 3.6V.

CC

Ω series resis-

Features

■ Compatible with PC100 and PC133 DIMM module
specifications

■ 1.65V–3.6V V

■ 3.6V tolerant inputs and outputs

■ 26

Ω series resistors in the outputs

■ t

(CLK to On)

PD

4.4 ns max for 3.0V to 3.6V V

5.9 ns max for 2.3V to 2.7V VCC

9.8 ns max for 1.65V to 1.95V V

■ Power-off high impedance inputs and outputs

■ Supports live insertion and withdrawal (Note 1)

■ Uses patented noise/EMI reductio n circuitr y

■ Latchup conforms to JEDEC JED78

■ ESD performance:

Human body model
Machine model

Note 1: To ensure the high-impedance state d uring power up or power

should be tied to VCC through a pull-up resistor. The minimum

down, OE
value of the resistor is determined by the current -sourcing capability of the

driver.

supply operation

CC

> 2000V

> 200V

CC

CC

Ordering Code:

Ordering Code Package Number Package Descriptions

74ALVC162838T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol Pin Descriptions

Pin Names Description

OE

I

0–I15

O

0–O15

CLK Clock Input

REGE Register Enable Input

© 2001 Fairchild Semiconductor Corporation DS500711 www.fairchildsemi.com

Output Enable Input (Active LOW)

Inputs

Outputs

Ω

Series

Connection Diagram Truth Table

CLK REGE

↑ HHL H

74ALVC162838

↑ HLL L

XLHLH
XLLLL
XXXHZ

H = Logic HIGH
L = Logic LOW
X = Don’t Care, but not floating
Z = High Impedance
↑ = LOW-to-HIGH Clock Transition

Functional Description

The 74ALVC162838 consists of sixteen selectable non­inverting buffers or regist ers with word wi de modes. Mode
functionality is selected through operation of the CLK and
REGE pin as shown by the truth table. When REGE is held
at a logic HIGH the device oper ates as a 16-bit register.
Data is transferred from I

CLK input. When the REG E pin i s held a t a l ogic LOW the
device operates in a flow through mode and data propa­gates directly from the I to the O outputs. All outputs can be
3-stated by holding the OE

Inputs Outputs

I

n

to On on the rising edge of the

n

pin at a logic HIGH.

OE

O

n

Logic Diagram

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Absolute Maximum Ratings(Note 2) Recommended Operating

Supply Voltage (VCC) −0.5V to +4.6V
DC Input Voltage (V
Output Voltage (V
DC Input Diode Current (I

V

< 0V −50 mA

I

DC Output Diode Current (I

< 0V −50 mA

V

O

) −0.5V to 4.6V

I

) (Note 3) −0.5V to VCC +0.5V

O

)

IK

)

OK

DC Output Source/Sink Current

(I

) ±50 mA

OH/IOL

or GND Current per

DC V

CC

Supply Pin (I

Storage Temperature Range (T

or GND) ±100 mA

CC

) −65°C to +150°C

STG

Conditions

Power Supply

Operating 1.65V to 3.6V
Input Voltage 0V to V
Output Voltage (VO)0V to V
Free Air Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (

= 0.8V to 2.0V, VCC = 3.0V 10 ns/V

V

IN

Note 2: The Absolute Maxi mum Ratings are thos e values beyond which
the safety of the d evice cannot b e guaranteed . The device sh ould not be
operated at these limit s. The parametric values defi ned in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat­ings. The “Recommended Operating Conditions” table will define the condi­tions for actual device oper ation.

Absolute Maximum Rating must be observed.

Note 3: I

O

Note 4: Floating or unused control inputs must be held HIGH or LOW.

(Note 4)

∆t/∆V)

DC Electrical Characteristics

V

Symbol Parameter Conditions

V

IH

V

IL

V

OH

V

OL

I

I

I

OZ

I

OFF

I

CC

∆I

HIGH Level Input Voltage 1.65 - 1.95 0.65 x V

LOW Level Input Voltage 1.65 - 1.95 0.35 x V

HIGH Level Output Voltage IOH = −100 µA 1.65 - 3.6 VCC - 0.2

LOW Level Output Voltage IOL = 100 µA 1.65 - 3.6 0.2

Input Leakage Current 0 ≤ VI ≤ 3.6V 1.65 - 3.6 ±5.0 µA
3-STATE Output Leakage 0 ≤ VO ≤ 3.6V, VI = VIH or V
Power Off Leakage Current 0V ≤ (VI, VO) ≤ 3.6V 0 10 mA
Quiescent Supply Current VI = VCC or GND, IO = 0 3.6 40 µA
Increase in ICC per Input VIH = VCC − 0.6V 2.7 - 3.6 750 µA

CC

IOH = −2 mA 1.65 1.2
I

= −4 mA 2.3 1.9

OH

= −6 mA 2.3 1.7

I

OH

I

= −8 mA 2.7 2

OH

= −12 mA 3.0 2

I

OH

I

= 2 mA 1.65 0.45

OL

= 4 mA 2.3 0.4

I

OL

IOL = 6 mA 2.3 0.55

IOL = 8 mA 2.7 0.6
IOL = 12 mA 3.0 0.8

IL

CC

(V)

2.7 - 3.6 2.0

2.7 - 3.6 0.8

3.0 2.4

3.0 0.55

1.65 - 3.6 ±10 µA

Min Max Units

CC

74ALVC162838

CC
CC

V2.3 - 2.7 1.7

CC

V2.3 - 2.7 0.7

V

V

3 www.fairchildsemi.com

AC Electrical Characteristics

TA = −40°C to +85°C, RL = 500Ω

Symbol Parameter

74ALVC162838

f
t

MAX

PHL

Maximum Clock Frequency 250 200 200 100 MHz

, t

Propagation Delay

PLH

Bus-to-Bus (REGE = 0)

t

, t

PLH

Propagation Delay

PHL

Clock to Bus (REGE = 1)

t

, t

PLH

Propagation Delay

PHL

REGE to Bus

t

, t

PZL

t

PLZ

t

S

t

H

t

W

Output Enable Time 1.3 4.5 1.5 6.2 1.0 5.7 1.5 9.8 ns

PZH

, t

Output Disable Time 1.3 4.6 1.5 5.1 1.0 4.6 1.5 8.3 ns

PHZ

Setup Time 1.0 1.0 1.0 2.5 ns
Hold Time 0.7 0.7 0.7 1.0 ns
Pulse Width 1.5 1.5 1.5 4.0 ns

V

CC

Min Max Min Max Min Max Min Max

1.34.01.55.41.04.91.59.8ns

1.34.41.55.91.05.41.59.8ns

1.34.41.55.91.05.41.59.8ns

CL = 50 pF CL = 30 pF

= 3.3V ± 0.3V VCC = 2.7V VCC = 2.5 ± 0.2V VCC = 1.8V ± 0.15V

Capacitance

Symbol Parameter Conditions

C

IN

C

OUT

C

PD

Input Capacitance VI = 0V or V
Output Capacitance VI = 0V or V

CC
CC

Power Dissipation Capacitance Outputs Enabled f = 10 MHz, CL = 0 pF 3.3 20

Units

TA = +25°C

V

CC

Typical

Units

3.3 6 pF

3.3 7 pF

2.5 20

pF

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AC Loading and Waveforms

FIGURE 1. AC Test Circuit

(Input Characteristics: f

Symbol

V

mi

V

mo

V

X

V

Y

V

L

3.3V ± 0.3V 2.7V 2.5V ± 0.2V 1.8V ± 0.15V

1.5V 1.5V VCC/2 VCC/2

1.5V 1.5V VCC/2 VCC/2

VOL + 0.3V VOL + 0.3V VOL + 0.15V VOL + 0.15V

VOH − 0.3V VOH − 0.3V VOH − 0.15V VOH − 0.15V

6V 6V VCC*2 VCC*2

TEST SWITCH

, t

t

PLH

t

, t

PZL

t

, t

PZH

TABLE 2. Variable Matrix

= 1MHz; t

= tf = 2ns; Z0 = 50Ω)

r

V

CC

TABLE 1. Values for Figure 1

PHL
PLZ
PHZ

Open

V

GND

74ALVC162838

L

FIGURE 2. Waveform for Inverting and

Non-Inverting Functions

FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic

FIGURE 5. Propagation Delay, Pulse Width and

t

Waveforms

rec

FIGURE 3. 3-STAT E Output High Enable and

Disable Times for Low Voltage Logic

FIGURE 6. Setup Time, Hold Time and

Recovery Time for Low Voltage Logic

5 www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted

Series

Ω

Resistors in the Outputs

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied a nd
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are device s or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the

74ALVC162838 Low Voltage 16-Bit Selectable Register/Buff er with 3.6V T olerant Inputs/Outputs and 26

user.

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Package Number MTD48

2. A critical component in any compon ent of a l ife supp ort
device or system whose failu re to perform can be rea­sonably expected to cause the failure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.

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