Datasheet 74ALS646 DATASHEETS (Philips)

Page 1
INTEGRATED CIRCUITS
74ALS646/74ALS646–1 74ALS648/74ALS648–1
Transceiver/register
Product specification IC05 Data Handbook
 
1991 Feb 08
Page 2
T ransceiver/register
74ALS646/646-1 Octal transceiver/register, non-inverting (3-State) 74ALS648/648-1 Octal transceiver/register, inverting (3-State)

FEA TURES

•Combines 74ALS245 and two 74ALS374 type functions in
one chip
•Independent registers for A and B buses
•Multiplexed real-time and stored data
•Choice of non-inverting and inverting data paths
•3-State outputs
•The -1 version sink 48mA I

DESCRIPTION

The 74ALS646/74ALS646-1 and 74ALS648/74ALS648-1 transceivers/registers consist of bus transceiver circuits with 3-State outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes High. Output enable (OE
) and direction (DIR) and select (SAB, SBA) pins are provided
for bus management. The 74ALS646-1 and 74ALS648-1 will sink 48mA if the VCC is
limited to 5.0V ±0.25V.
within the ±5% VCC range
OL

ORDERING INFORMATION

TYPE
74ALS646/646-1 140MHz 48mA 74ALS648/648-1 140MHz 54mA
DESCRIPTION
24-pin plastic DIP
24-pin plastic SOL
74ALS646/74ALS646-1 74ALS648/74ALS648-1
TYPICAL
TYPICAL f
ORDER CODE
COMMERCIAL RANGE
V
= 5V ±10%,
CC
T
= 0°C to +70°C
amb
74ALS646N, 74ALS646-1N,
74ALS648N, 74ALS648-1N
74ALS646D, 74ALS646-1D,
74ALS648D, 74ALS648-1D
SUPPLY CURRENT
MAX
(TOTAL)
DRAWING
NUMBER
SOT222-1
SOT137-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION
A0 – A7 A inputs 1.0/1.0 20µA/0.1mA B0 – B7 B inputs 1.0/1.0 20µA/0.1mA
CPAB A-to-B clock input 1.0/1.0 20µA/0.1mA CPBA B-to-A clock input 1.0/1.0 20µA/0.1mA
SAB A-to-B select input 1.0/1.0 20µA/0.1mA SBA B-to-A select input 1.0/1.0 20µA/0.1mA
DIR Data flow directional control input 1.0/1.0 20µA/0.1mA
OE Output enable input 1.0/1.0 20µA/0.1mA A0 – A7, B0 – B7 Data outputs 750/240 15mA/24mA A0 – A7, B0 – B7 Data outputs (-1 version) 750/480 15mA/48mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
1991 Feb 08 853–1408 01670
2
Page 3
Transceiver/register

PIN CONFIGURATION – 74ALS646/646-1

1
CPAB
2
SAB
3
DIR
4
A0
5
A1
6
A2
7
A3
8
A4
9
A5
10
A6
11
A7
12 13
GND

LOGIC SYMBOL – 74ALS646/646-1

4567891011
V
24
CC
23
CPBA
22
SBA
21
OE
20
B0
19
B1
18
B2
17
B3
16
B4
15
B5
14
B6 B7
SC00118
74ALS646/74ALS646-1 74ALS648/74ALS648-1

PIN CONFIGURATION – 74ALS648/648-1

1
CPAB
2
SAB
3
DIR
4
A0
5
A1
6
A2
7
A3
8
A4
9
A5
10
A6
11
A7
12 13
GND

LOGIC SYMBOL – 74ALS648/648-1

4567891011
V
24
CC
23
CPBA
22
SBA
21
OE
20
B0
19
B
1
18
B
2
17
B3
16
B
4
15
B
5
14
6
B B
7
SC00119
A0 A1 A2 A3 A4 A5 A6 A7 CPAB
1
SAB
2
DIR
3
SPBA
23
SBA
22
OE
21
B0 B1 B2 B3 B4 B5 B6 B7
V
= Pin 24
CC
GND = Pin 12
20 19 18 17 16 15 14 13

IEC/IEEE SYMBOL – 74ALS646/646-1

21 3
23 22 1 2
4
5 6 7 8 9 10 11
G3 3 EN1 [BA] 3 EN2 [AB]
C4
G5
C6
G7
1
1
6D
1
5
4D
1
5
1
7
2
7
SC00120
20
19 18 17 16 15 14 13
A0 A1 A2 A3 A4 A5 A6 A7
CPAB
1
SAB
2
DIR
3
SPBA
23
SBA
22
OE
21
B0 B1 B2 B3 B4 B5 B6 B7
VCC = Pin 24 GND = Pin 12
20 19 18 17 16 15 14 13

IEC/IEEE SYMBOL – 74ALS648/648-1

21 3
23 22 1 2
4
5 6 7 8 9 10 11
G3 3 EN1 [BA] 3 EN2 [AB]
C4
G5
C6
G7
1
1
6D
1
5
4D
1
5
1
7
2
7
SC00121
20
19 18 17 16 15 14 13
1991 Feb 08
SC00122
SC00123
3
Page 4
Transceiver/register

BUS MANAGEMENT FUNCTIONS

The following examples demonstrate the four fundamental bus-management functions that can be performed with the 74ALS646/646-1 and 74ALS648/648-1.
The select pins determine whether data is stored or transferred through the device in real time.
The DIR determines which bus will receive data when the OE pin is Low.
REAL TIME BUS TRANSFER
BUS B TO BUS A
BUS A
BUS B
REAL TIME BUS TRANSFER
BUS A TO BUS B
BUS A BUS A
STORAGE FROM
A, B, OR A AND B
74ALS646/74ALS646-1 74ALS648/74ALS648-1
TRANSFER STORED DATA
TO A AND/OR B
BUS A BUS BBUS BBUS B
OE DIR CPABCPBA SAB SBA
LL X X X L
DIR CPABCPBA SAB SBA
OE
LH X X L X
OE DIR CPABCPBA SAB SBA
XX ↑ XXX XX X ↑ XX HX ↑↑XX
DIR CPABCPBA SAB SBA
OE
L L X H or L X H L H H or L X H X
SF00392
1991 Feb 08
4
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Transceiver/register

LOGIC SYMBOL – 74ALS646/646-1

21
OE
3
DIR
23
CPBA
22
SBA
1
CPAB
2
SAB
1 OF 8 CHANNELS
C1
4
A0
1D
C1
74ALS646/74ALS646-1 74ALS648/74ALS648-1

LOGIC SYMBOL – 74ALS648/648-1

21
OE
3
DIR
23
CPBA
22
SBA
1
CPAB
2
SAB
1D
20
B0
4
A0
1 OF 8 CHANNELS
1D
C1
1D
C1
20
B0
V
= Pin 24
CC
GND = Pin 12
TO 7 OTHER CHANNELS
SC00124
V
= Pin 24
CC
GND = Pin 12
TO 7 OTHER CHANNELS

FUNCTION TABLE

INPUTS DATA I/O OPERATING MODE
OE DIR CPAB CPBA SAB SBA An Bn 74ALS646/74ALS646-1 74ALS648/74ALS648-1
X X ↑ X X X Input Unspecified* Store A, B unspecified* Store A, B unspecified* X X X ↑ X X Unspecified* Input Store B, A unspecified* Store B, A unspecified* H X ↑ ↑ X X Input Input Store A and B data Store A and B data H X H or L H or L X X Input Input Isolation, hold storage Isolation, hold storage
L L X X X L Output Input Real time B data to A bus Real time B data to A bus L L X H or L X H Output Input Stored B data to A bus Stored B data to A bus L H X X L X Input Output Real time A data to B bus Real time A data to B bus L H H or L X H X Input Output Stored A data to B bus Stored A data to B bus
NOTES:
H = High voltage level L = Low voltage level X = Don’t care * = The data output function may be enabled or disabled by various signals at the OE
enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.
↑ = Low-to-High clock transition
and DIR inputs. Data input functions are always
SC00125
1991 Feb 08
5
Page 6
I
Current applied to output in Low output state
SYMBOL
UNIT
IOLLow-level output current
Transceiver/register

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
T
V
V
I
OUT
OUT
amb
T
CC
IN
stg
Supply voltage –0.5 to +7.0 V Input voltage –0.5 to +7.0 V
IN
Input current –30 to +5 mA Voltage applied to output in High output state –0.5 to V
pp
p
Operating free-air temperature range 0 to +70 °C Storage temperature range –65 to +150 °C

RECOMMENDED OPERATING CONDITIONS

V
CC
V V
I
IK
I
OH
T
amb
NOTE:
1. The 48mA limit applies only under the condition of V
Supply voltage 4.5 5.0 5.5 V High-level input voltage 2.0 V
IH
Low-level input voltage 0.8 V
IL
Input clamp current –18 mA High-level output current –15 mA
p
Operating free-air temperature range 0 +70 °C
PARAMETER RATING UNIT
p
All versions 48 mA
-1 version 96 mA
PARAMETER
All versions 24 mA
-1 version 48
= 5.0V ±5%.
CC
74ALS646/74ALS646-1 74ALS648/74ALS648-1
CC
LIMITS
MIN NOM MAX
1
V
mA
1991 Feb 08
6
Page 7
SYMBOL
PARAMETER
TEST CONDITIONS
1
UNIT
CC
,
IL
,
VOHHigh level out ut voltage
All versions
CC
,
IL
,
VOLLow level out ut voltage
I
Transceiver/register
74ALS646/74ALS646-1 74ALS648/74ALS648-1

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
MIN TYP
VCC±10%, VIL = MAX,
-
p
VIH = MIN VCC = MIN, VIL = MAX,
V
= MIN
IH
VCC = MIN, VIL = MAX,
-
p
-1 versions
V
I
IH
I
I
I
CC
Input clamp voltage VCC = MIN, II = I
IK
Input current at maxi-
I
mum input voltage High-level input current
Low-level input current
IL
Output current
O
Supply current (total)
4
control inputs VCC = MAX, VI = 7.0V 0.1 mA
A or B ports VCC = MAX, VI = 5.5V 0.1 mA
3
3
I
CCH
I
CCL
I
CCZ
VIH = MIN VCC = 4.75V, VIL = MAX,
V
= MIN
IH
IK
VCC = MAX, VI = 2.7V 20 µA VCC = MAX, VI = 0.4V –0.1 mA VCC = MAX, VO = 2.25V –30 –112 mA
VCC = MAX
IOH = –0.4mA V
IOH = –3mA 2.4 3.2 V
IOH = –15mA 2.0 V
I
= 12mA 0.25 0.40 V
OL
I
= 24mA 0.35 0.50 V
OL
I
= 48mA 0.35 0.50 V
OL
– 2 V
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
3. For I/O ports, the parameter I
4. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
CC
= 5V, T
IH
= 25°C.
amb
and IIL include the off-state current.
2
MAX
–0.73 –1.5 V
40 57 mA 53 78 mA 51 72 mA
OS
.

AC ELECTRICAL CHARACTERISTICS FOR 74ALS646/74ALS646-1

SYMBOL PARAMETER TEST CONDITION
f t
t t
t t
t t
t t
t
t
t
t
t
t
t
max PLH
PHL PLH
PHL PLH
PHL PLH
PHL PZH
PZL PHZ
PLZ PZH
PZL PHZ
PLZ
Maximum clock frequency Waveform 1 100 MHz Propagation delay
CPBA to An, CPAB to Bn Propagation delay
An to Bn or Bn to An Propagation delay
SBA to An or SAB to Bn (A or B Low) Propagation delay
SBA to An or SAB to Bn (A or B High) Output enable time
OE
to An or Bn
Output disable time OE
to An or Bn
Output enable time DIR to An or Bn
Output disable time DIR to An or Bn
Waveform 1
Waveform 2, 3
Waveform 2, 3
Waveform 2, 3
Waveform 5 Waveform 6
Waveform 5 Waveform 6
Waveform 5 Waveform 6
Waveform 5 Waveform 6
LIMITS
T
= 0°C to +70°C
amb
V
= +5.0V ± 10%
CC
C
= 50pF, RL = 500Ω
L
MIN MAX
5.0
6.0
2.0
3.0
5.0
5.0
5.0
5.0
3.0
5.0
2.0
3.0
2.0
5.0
2.0
3.0
13.0
13.0
8.0
9.0
13.0
11.0
11.0
11.0
9.0
11.0
8.0
10.0
10.0
12.0
10.0
13.0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
1991 Feb 08
7
Page 8
Transceiver/register

AC ELECTRICAL CHARACTERISTICS FOR 74ALS648/74ALS648-1

SYMBOL PARAMETER TEST CONDITION
f t
t t
t t
t t
t t
t
t
t
t
t
t
t
max PLH
PHL PLH
PHL PLH
PHL PLH
PHL PZH
PZL PHZ
PLZ PZH
PZL PHZ
PLZ
Maximum clock frequency Waveform 1 100 MHz Propagation delay
CPBA to An, CPAB to Bn Propagation delay
An to Bn or Bn to An Propagation delay
SBA to An or SAB to Bn (A or B Low) Propagation delay
SBA to An or SAB to Bn (A or B High) Output enable time
OE
to An or Bn
Output disable time OE
to An or Bn
Output enable time DIR to An or Bn
Output disable time DIR to An or Bn
Waveform 1
Waveform 2, 3
Waveform 2, 3
Waveform 2, 3
Waveform 5 Waveform 6
Waveform 5 Waveform 6
Waveform 5 Waveform 6
Waveform 5 Waveform 6
74ALS646/74ALS646-1 74ALS648/74ALS648-1
LIMITS
T
= 0°C to +70°C
amb
V
= +5.0V ± 10%
CC
C
= 50pF, RL = 500Ω
L
MIN MAX
5.0
6.0
1.0
3.0
5.0
5.0
4.0
5.0
2.0
4.0
1.0
2.0
3.0
5.0
2.0
2.0
13.0
13.0
7.0
9.0
13.0
11.0
11.0
11.0
8.0
13.0
8.0
10.0
10.0
12.0
11.0
11.0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns

AC SETUP REQUIREMENTS

SYMBOL PARAMETER TEST CONDITION
t
(H)
su
t
(L)
su
t
(H)
h
t
(L)
h
t
(H)
w
t
(L)
w
Setup time, High or Low An or Bn to CPAB or CPBA
Hold time, High or Low An or Bn to CPAB or CPBA
Pulse width, High or Low CPAB or CPBA
Waveform 4
Waveform 4
Waveform 1
LIMITS
T
= 0°C to +70°C
amb
V
= +5.0V ± 10%
CC
C
= 50pF, RL = 500Ω
L
5.0
5.0
0.0
1.0
6.0
4.0
UNIT
ns
ns
ns
1991 Feb 08
8
Page 9
Transceiver/register

AC WAVEFORMS

For all waveforms, VM = 1.3V. The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
CPBA
or
CPAB
An or Bn
V
M
t
PHL
tw(H)
max
V
M
tw(L)
V
M
V
M
t
PLH
V
M
SF00394
Waveform 1. Propagation Delay for Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
t
PHL
V
M
SBA or SAB
An or Bn
An or Bn
Bn or An
V
t
PLH
M
V
M
V
M
An or Bn
Bn or An
Waveform 2. Propagation Delay for An to Bn or Bn to An
and SAB or SBA to An or Bn
An or Bn
CPBA
or
CPAB
V
M
(H) th(H)
t
su
V
M
74ALS646/74ALS646-1 74ALS648/74ALS648-1
V
M
t
PHL
V
M
V
M
V
M
SBA or SAB
t
PLH
V
M
V
tsu(L) th(L)
V
M
V
An or Bn
SF00395
M
M
SF00396
Waveform 3. Propagation Delay for An to Bn or Bn to An
and SAB or SBA to An or Bn
OE
DIR
An or Bn
V
t
PZH
M
V
V
M
t
PHZ
M
VOH -0.3V
SF00398
Waveform 5. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
SF00397
Waveform 4. Data Setup Time and Hold Times
OE
DIR
0V
An or Bn
V
t
PZL
M
V
V
M
t
PLZ
M
3.5V
VOL +0.3V
SF00399
Waveform 6. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
1991 Feb 08
9
Page 10
Transceiver/register

TEST CIRCUIT AND WAVEFORMS

V
CC
V
PULSE
GENERATOR
IN
R
T
Test Circuit for 3-State and Open Collector Outputs
SWITCH POSITION
TEST SWITCH
t
PLZ
, t
PZL
closed
open collector closed
All other open
DEFINITIONS:
R
= Load resistor;
L
see AC electrical characteristics for value.
CL= Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
D.U.T.
V
OUT
R
L
C
R
L
L
OUT
7.0V
of
NEGATIVE PULSE
POSITIVE PULSE
Family
74ALS
90%
10%
Amplitude
74ALS646/74ALS646-1 74ALS648/74ALS648-1
t
w
V
M
10%
)
t
f
THL (tf
t
)
TLH (tr
90%
V
M
Input Pulse Definition
INPUT PULSE REQUIREMENTS
V
M
3.5V
1.3V
t
TLH (tr
t
t
w
Rep.Rate
1MHz
THL (tf
V
10%
)
)
90%
t
w
500ns
M
V
M
t
TLHtTHL
2.0ns 2.0ns
90%
10%
AMP (V)
0.3V
AMP (V)
0.3V
SC00126
1991 Feb 08
10
Page 11
Transceiver/register
74ALS646/74ALS646–1 74ALS648/74ALS648–1

DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1

1991 Feb 08
11
Page 12
Transceiver/register
74ALS646/74ALS646–1 74ALS648/74ALS648–1

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

1991 Feb 08
12
Page 13
Transceiver/register
74ALS646/74ALS646–1 74ALS648/74ALS648–1

DEFINITIONS

Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
LIFE SUPPORT APPLICA TIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
 
1991 Feb 08
13
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