Datasheet 74ALS573B, 74ALS574A Datasheet (Philips)

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INTEGRATED CIRCUITS

74ALS573B/74ALS574A

Latch flip–flop

Product specification IC05 Data Handbook

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1991 Feb 08

Philips Semiconductors Product specification

74ALS573B/74ALS574ALatch/flip-flop

74ALS573B Octal transparent latch (3-State) 74ALS574A Octal D flip-flop (3-State)

FEA TURES

•74ALS573B is broadside pinout version of 74ALS373

•74ALS574A is broadside pinout version of 74ALS374

•Inputs and outputs on opposite side of package allow easy

interface to microprocessors

•Useful as an input or output port for microprocessors

•3-State outputs for bus interfacing

•Common output enable

•74ALS563A and 74ALS564A are inverting version of 74ALS573B

and 74ALS574A respectively

DESCRIPTION

The 74ALS573B is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE

The 74ALS573B is functionally identical to the 74ALS373 but has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors.

The data on the D inputs is transferred to the latch outputs when the enable (E) input is High. The latch remains transparent to the data input while E is High, and stores the data that is present one setup time before the High-to-Low enable transition.

The 74ALS574A is functionally identical to the 74ALS374 but has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors.

) control gates.

It is an 8-bit edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by clock (CP) and output enable (OE

The register is fully edge triggered. The state of the D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output.

The active-Low output enable (OE independent of the latch operation. When OE transparent data appears at the output.

When OE which means they will neither drive nor load the bus.

is High, the outputs are in high impedance “off” state,

TYPICAL

TYPE

74ALS573B 5.0ns 12mA 74ALS574A 6.0ns 15mA

PROPAGATION

DELA Y

) control gates.

) controls all eight 3-State buffers

is Low, latched or

TYPICAL

SUPPLY CURRENT

(TOTAL)

ORDERING INFORMATION

ORDER CODE

COMMERCIAL RANGE

V

DESCRIPTION

20-pin plastic DIP 74ALS573BN, 74ALS574AN SOT146-1

20-pin plastic SOL 74ALS573BD, 74ALS574AD SOT163-1

20-pin plastic SSOP

Type II

= 5V ±10%,

CC

T

= 0°C to +70°C

amb

74ALS573BDB,

74ALS574ADB

DRAWING

NUMBER

SOT339-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION

D0 – D7 Data inputs 1.0/1.0 20µA/0.2mA

E (74ALS573B) Latch enable input 1.0/1.0 20µA/0.1mA

OE Output Enable input (active-Low) 1.0/1.0 20µA/0.1mA

CP (74ALS574A) Clock pulse input (active rising edge) 1.0/2.0 20µA/0.2mA

Q0 – Q7 Data outputs 130/240 2.6mA/24mA

NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.

74ALS (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

1991 Feb 08 853–1307 01670

2

Philips Semiconductors Product specification

74ALS573B/74ALS574ALatch/flip-flop

PIN CONFIGURATION – 74ALS573B

1

OE

2

D0

3

D1

4

D2

5

D3

6

D4

7

D5

8

D6

9

D7

10 11

GND

20 19 18 17 16 15 14 13 12

LOGIC SYMBOL – 74ALS573B

345678

2

11 E

1

D0 D1Q1D2

OE

Q0

Q2 Q3D3Q4D4Q5

D5

V Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 E

CC

D7

Q6D6Q7

9

SF01073

PIN CONFIGURATION – 74ALS574A

1

OE

2

D0

3

D1

4

D2

5

D3

6

D4

7

D5

8

D6

9

D7

GND

10 11

20 19 18 17 16 15 14 13 12

LOGIC SYMBOL – 74ALS574A

345678

2

11 CP

1

OE

D0 D1Q1D2

Q0

Q2 Q3D3Q4D4Q5

D5

V Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CP

CC

SF01074

9

D7

Q6D6Q7

VCC=Pin 20 GND=Pin 10

IEC/IEEE SYMBOL – 74ALS573B

1 11

2 3 4 5 6 7 8 9

EN1 EN2

2D

1

141516171819

1213

SF01075

VCC=Pin 20 GND=Pin 10

141516171819

1213

SF01076

IEC/IEEE SYMBOL – 74ALS574A

1 11

19 18 17 16 15 14 13 12

SF01077

2 3 4 5 6 7

8 9

EN1

C2

2D

1

19 18 17 16 15 14

13 12

SF01078

1991 Feb 08

3

Philips Semiconductors Product specification

OPERATING MODE

Enable and read register

Latch and read register

Disable outputs

74ALS573B/74ALS574ALatch/flip-flop

LOGIC DIAGRAM – 74ALS573B

D0

2

D1

3

D2

4

D3

5

D4

6

D5

7

D6

8

D7

9

V

= Pin 20

CC

GND = Pin 10

E

OE

D

Q

E

11

1

Q0

D

Q

E

19

Q1

D

Q

E

18

Q2

D

Q

E

17

Q3

D

E

16

D

Q

E

15

Q4

FUNCTION T ABLE – 74ALS573B

INPUTS

OE E Dn

OUTPUTS

REGISTER

L H L L L L H H H H L ↓ l L L L ↓ h H H L L X NC NC Hold H L X NC Z H H Dn Dn Z

H = High-voltage level h = High state must be present one setup time before the High-to-Low enable transition L = Low-voltage level l = Low state must be present one setup time before the High-to-Low enable transition NC= No change X = Don’t care Z = High impedance “off” state ↓ = High-to-Low enable transition

INTERNAL

Q0 – Q7

Q5

D

Q

E

14

Q

Q6

D

Q

E

13

12

Q7

SC00109

p

LOGIC DIAGRAM – 74ALS574A

VCC = Pin 20 GND = Pin 10

1991 Feb 08

CP

OE

D0

2

D CP

11

1

D1

3

Q0

D CP

19

Q

D2

4

Q1

D CP

18

Q

D3

5

Q2

D CP

17

Q

D4

6

Q

16

Q3

D CP

D5

7

D

Q

CP

15

Q4

D6

8

Q5

D CP

14

Q

D7

9

Q6

D

Q

CP

13

Q7

12

SC00110

Q

4

Philips Semiconductors Product specification

OPERATING MODE

Latch and read register

Disable outputs

SYMBOL

PARAMETER

UNIT

74ALS573B/74ALS574ALatch/flip-flop

FUNCTION T ABLE – 74ALS574A

INPUTS

OE CP Dn

OUTPUTS

REGISTER

L ↑ l L L L ↑ h H H L ↑ X NC NC Hold H ↑ X NC Z H ↑ Dn Dn Z

H = High-voltage level h = High state must be present one setup time before the Low-to-High clock transition L = Low-voltage level l = Low state must be present one setup time before the Low-to-High clock transition NC= No change X = Don’t care Z = High impedance “off” state ↑ = Low-to-High clock transition

= Not Low-to-High clock transition

↑

INTERNAL

Q0 – Q7

p

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)

SYMBOL

V

CC

V

IN

I

IN

V

OUT

I

OUT

T

amb

T

stg

Supply voltage –0.5 to +7.0 V Input voltage –0.5 to +7.0 V Input current –30 to +5 mA Voltage applied to output in High output state –0.5 to V Current applied to output in Low output state 48 mA Operating free-air temperature range 0 to +70 °C Storage temperature range –65 to +150 °C

PARAMETER RATING UNIT

RECOMMENDED OPERATING CONDITIONS

V

T

V

I

OH

I

OL

amb

CC

IK

Supply voltage 4.5 5.0 5.5 V High-level input voltage 2.0 V

IH

Low-level input voltage 0.8 V

IL

Input clamp current –18 mA High-level output current –2.6 mA Low-level output current 24 mA Operating free-air temperature range 0 +70 °C

CC

LIMITS

MIN NOM MAX

V

1991 Feb 08

5

Philips Semiconductors Product specification

SYMBOL

PARAMETER

TEST CONDITIONS

1

UNIT

VOHHigh-level output voltage

CC

,

IL

,

VOLLow-level output voltage

CC

,

IL

,

IILLow-level input current

ICCSupply current (total)

74ALS573B/74ALS574ALatch/flip-flop

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

LIMITS

MIN TYP2MAX

IOH = –0.4mA V

IOH = MAX 2.4 3.2 V

I

= 12mA 0.25 0.40 V

OL

I

= 24mA 0.35 0.50 V

OL

I

V

IK

I

IH

OZH

OZL

I

O

p

Input clamp voltage VCC = MIN, II = I

VCC = ±10%, VIL = MAX, VIH = MIN

VCC = MIN, VIL = MAX, VIH = MIN

IK

Input current at minimum input voltage VCC = MAX, VI = 7.0V 0.1 mA High-level input current VCC = MAX, VI = 2.7V 20 µA

p

Off-state output current, High-level voltage applied

Off-state output current, Low-level voltage applied

Output current

3

pp

74ALS573B VCC = MAX, VI = 0.4V –0.1 mA 74ALS574A VCC = MAX, VI = 0.4V –0.2 mA

VCC = MAX, VI = 2.7V 20 µA

VCC = MAX, VI = 0.4V –20 µA

VCC = MAX, VO = 2.25V –30 –112 mA

I

CCH

74ALS573B

74ALS574A

I

CCL

I

CCZ

I

CCH

I

CCL

I

CCZ

VCC = MAX

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I

= 5V, T

CC

amb

= 25°C.

– 2 V

CC

–0.73 –1.2 V

7 12 mA 13 21 mA 15 24 mA 10 16 mA 17 27 mA 18 28 mA

OS

.

1991 Feb 08

6

Philips Semiconductors Product specification

74ALS573B

74ALS573B/74ALS574ALatch/flip-flop

AC ELECTRICAL CHARACTERISTICS

LIMITS

T

= 0°C to +70°C

amb

V

SYMBOL PARAMETER TEST CONDITION

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

f

MAX

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

Propagation delay Dn to Qn

Propagation delay E to Qn

Output enable time to High or Low level

Output disable time from High or Low level

Waveform 3

Waveform 2 Waveform 6

Waveform 7 Waveform 6

Waveform 7 Maximum clock frequency Waveform 1 45 MHz Propagation delay

CP to Qn Output enable time

to High or Low level Output disable time

from High or Low level

74ALS574A

Waveform 1

Waveform 6

Waveform 7

Waveform 6

Waveform 7

= +5.0V ± 10%

CC

C

= 50pF, RL = 500Ω

L

MIN MAX

2.0

4.0

10.0

12.0

2.0

4.0

11.0

1.0

2.0

3.0

4.0

11.0

12.0

2.0

4.0

11.0

1.0

2.0

11.0

9.0

UNIT

ns

AC SETUP CHARACTERISTICS

LIMITS

T

= 0°C to +70°C

amb

V

SYMBOL PARAMETER TEST CONDITION

tsu(H) t

(L)

su

th(H) t

(L)

h

Setup time, High or Low Dn to E

Hold time, High or Low Dn to E

74ALS573B

Waveform 4

tw(H) E Pulse width, High Waveform 1 10.0 ns

tsu(H) t

(L)

su

th(H)

t

(L)

h

tw(H)

t

(L)

w

Setup time, High or Low Dn to CP

Hold time, High or Low Dn to CP

CP Pulse width, High or Low

74ALS574A

Waveform 5

= +5.0V ± 10%

CC

C

= 50pF, RL = 500Ω

L

MIN MAX

6.0

1.0

8.0

12.0

UNIT

ns

1991 Feb 08

7

Philips Semiconductors Product specification

74ALS573B/74ALS574ALatch/flip-flop

AC WAVEFORMS

For all waveforms, VM = 1.3V. The shaded areas indicate when the input is permitted to change for predictable output performance.

1/f

max

CP

Qn

V

M

tw(H)

PLH

V

M

tw(L)t

V

M

V

M

t

PHL

V

M

SF00258

Waveform 1. Propagation Delay for Clock Input to Output,

Clock Pulse Widths, and Maximum Clock Frequency

Dn

Qn

V

M

t

PLH

V

M

t

PHL

V

M

SF00260

Waveform 3. Propagation Delay for Data to Output

Dn

E

V

M

(H) th(H)

t

su

V

M

V

M

V

tsu(L) th(L)

V

M

V

M

tw(H)

EV

Qn

M

t

PHL

V

M

V

M

V

t

PLH

M

V

M

Waveform 2. Propagation Delay for Enable to Output and

Enable Pulse Width

Dn

CP

V

M

(H) th(H)

t

su

V

M

V

M

V

tsu(L) th(L)

V

M

V

M

SF00259

SF00261

Waveform 4. Data Setup Time and Hold T imes

OE

Qn

V

M

t

PZH

V

M

t

PHZ

V

M

VOH -0.3V

SC00099

Waveform 6. 3-State Output Enable Time to High Level and

Output Disable Time from High Level

1991 Feb 08

SF00262

Waveform 5. Data Setup Time and Hold T imes

OE

Qn

0V

V

M

t

PZL

V

M

t

PLZ

V

M

V

OL

3.5V

+0.3V

SC00100

Waveform 7. 3-State Output Enable Time to Low Level and

Output Disable Time from Low Level

8

Philips Semiconductors Product specification

74ALS573B/74ALS574ALatch/flip-flop

TEST CIRCUIT AND WAVEFORMS

V

CC

PULSE

GENERATOR

V

IN

R

T

D.U.T.

V

OUT

R

L

C

R

L

Test Circuit for 3-State Outputs

SWITCH POSITION

TEST SWITCH

t

PLZ

, t

PZL

closed

All other open

DEFINITIONS:

R

= Load resistor;

L

see AC electrical characteristics for value.

= Load capacitance includes jig and probe capacitance;

C

L

see AC electrical characteristics for value.

R

= Termination resistance should be equal to Z

T

pulse generators.

OUT

7.0V

of

NEGATIVE PULSE

POSITIVE PULSE

Family

74ALS

90%

10%

Amplitude

t

w

V

M

10%

)

t

f

THL (tf

t

)

TLH (tr

90%

V

M

t

TLH (tr

t

THL (tf

t

w

Input Pulse Definition

INPUT PULSE REQUIREMENTS

V

Rep.Rate

M

3.5V

1.3V

1MHz

V

10%

)

90%

t

w

500ns

M

V

M

t

TLHtTHL

2.0ns 2.0ns

90%

10%

AMP (V)

0.3V

AMP (V)

0.3V

SC00072

1991 Feb 08

9

Philips Semiconductors Product specification

74ALS573B/74ALS574ALatch/flip–flop

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

1991 Feb 08

10

Philips Semiconductors Product specification

74ALS573B/74ALS574ALatch/flip–flop

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

1991 Feb 08

11

Philips Semiconductors Product specification

74ALS573B/74ALS574ALatch/flip–flop

SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1

1991 Feb 08

12

Philips Semiconductors Product specification

74ALS573B/74ALS574ALatch/flip–flop

DEFINITIONS

Data Sheet Identification Product Status Definition

Objective Specification

Preliminary Specification

Product Specification

Formative or in Design

Preproduction Product

Full Production

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

LIFE SUPPORT APPLICA TIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected

to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.

 Copyright Philips Electronics North America Corporation 1997

 

1991 Feb 08

13

Datasheet 74ALS573B, 74ALS574A Datasheet (Philips)

Specifications and Main Features

Frequently Asked Questions

User Manual