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74ALS563AD
Datasheet (Philips)
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Datasheet 74ALS564AN, 74ALS564AD, 74ALS563AD Datasheet (Philips)

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Page 1
INTEGRATED CIRCUITS
74ALS563A/74ALS564A
Latch flip/flop
Product specification IC05 Data Handbook
 
1996 Jul 01
Page 2
74ALS563A/74ALS564ALatch/flip-flop
74ALS563A Octal transparent latch, inverting (3-State) 74ALS564A Octal D flip-flop, inverting (3-State)

FEA TURES

•74ALS563A is broadside pinout and inverting version of
74ALS373
•74ALS564A is broadside pinout and inverting version of
74ALS374
•Inputs and outputs on opposite side of package allow easy
interface to microprocessors
•Useful as an input or output port for microprocessors
•3-State outputs for bus interfacing
•Common output enable
•74ALS573A and 74ALS574A are non-inverting version of
74ALS563B and 74ALS564A respectively
TYPE
74ALS563A 6.0ns 12mA 74ALS564A 6.0ns 15mA
TYPICAL
PROPAGATION DELAY

ORDERING INFORMATION

ORDER CODE
DESCRIPTION COMMERCIAL RANGE
20-pin plastic DIP 74ALS563AN, 74ALS564AN SOT146-1
20-pin plastic SOL 74ALS563AD, 74ALS564AD SOT163-1
V
= 5V ±10%,
CC
T
= 0°C to +70°C
amb
TYPICAL
SUPPLY CURRENT
(TOTAL)
DRAWING
NUMBER

DESCRIPTION

The 74ALS563A is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE
The 74ALS563A is a complementary version of the 74ALS373 and has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors.
The data on the D inputs is transferred to the latch outputs when the enable (E) input is High. The latch remains transparent to the data input while E is High, and stores the inverted data that is present one setup time before the High-to-Low enable transition.
The 74ALS564A is a complementary version of the 74ALS373 and has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors.
It is an 8-bit edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by clock (CP) and output enable (OE
The register is fully edge triggered. The state of the D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output.
The active-Low output enable (OE independent of the latch operation. When OE transparent data appears at the output.
When OE which means they will neither drive nor load the bus.
is High, the outputs are in high impedance “off” state,
) control gates.
) controls all eight 3-State buffers
) control gates.
is Low, latched or

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION
D0 – D7 Data inputs 1.0/2.0 20µA/0.2mA
E (74ALS563A) Enable input 1.0/1.0 20µA/0.1mA
OE Output enable input (active-Low) 1.0/1.0 20µA/0.1mA
CP (74ALS564A) Clock pulse input (active rising edge) 1.0/2.0 20µA/0.2mA
Q0 – Q7 Data outputs 130/240 2.6mA/24mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
1996 Jul 01 853–1306 01670
2
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Page 3
74ALS563A/74ALS564ALatch/flip-flop

PIN CONFIGURATION – 74ALS563A

1
OE
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10 11
GND
20 19 18 17 16 15 14 13 12

LOGIC SYMBOL – 74ALS563A

345678
2
11 E
1
D0 D1Q1D2
OE
Q0
Q2 Q3D3Q4D4Q5
D5
V
CC
Q0 Q
1 Q2 Q
3 Q
4 Q
5 Q
6 Q
7 E
D7
Q6D6Q7

PIN CONFIGURATION – 74ALS564A

SC00111
1
OE
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10 11
GND
20
V
CC
Q0
19 18
Q
1
17
Q2
16
Q
3
15
Q
4
14
Q
5
13
Q
6
12
Q
7
CP
SF01052

LOGIC SYMBOL – 74ALS564A

345678
9
11 CP
1
2
D0 D1Q1D2
OE
Q0
D5
Q2 Q3D3Q4D4Q5
9
D7
Q6D6Q7
VCC=Pin 20 GND=Pin 10

IEC/IEEE SYMBOL – 74ALS563A

1 11
2 3 4
5 6 7 8 9
EN1 EN2
2D
1
141516171819
1213
SC00112
VCC=Pin 20 GND=Pin 10
141516171819
1213
SF01053

IEC/IEEE SYMBOL – 74ALS564A

1
11
19 18 17 16 15 14
13 12
SC00113
2 3 4
5 6 7 8 9
EN1
2D
C2
1
19 18 17 16 15 14
13 12
SF01054
1996 Jul 01
3
Page 4
OPERATING MODE
Enable and read register
Latch and read register
Disable outputs
74ALS563A/74ALS564ALatch/flip-flop

LOGIC DIAGRAM – 74ALS563A

D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
V
= Pin 20
CC
GND = Pin 10
E
OE
D
Q
E
11
1
D
Q
E
19
Q0
D
Q
E
18
Q1
D
Q
E
17
Q2
D
Q
E
16
Q3
15
Q4

FUNCTION T ABLE – 74ALS563A

INPUTS
OE E Dn
OUTPUTS
REGISTER
L H L L H L H H H L L ↓ l L H L ↓ h H L L L X NC NC Hold H L X NC Z H H Dn Dn Z
H = High voltage level h = High state must be present one setup time before the High-to-Low enable transition L = Low voltage level l = Low state must be present one setup time before the High-to-Low enable transition NC= No change X = Don’t care Z = High impedance “off” state ↓ = High-to-Low enable transition
INTERNAL
Q0 – Q7
D
Q
E
D
E
14
Q5
D
Q
Q6
Q
E
13
12
Q7
SC00116
p
1996 Jul 01
4
Page 5
OPERATING MODE
Load and read register
Disable outputs
74ALS563A/74ALS564ALatch/flip-flop

LOGIC DIAGRAM – 74ALS564A

VCC = Pin 20 GND = Pin 10
CP
OE
D0
2
D CP
11
1
D1
3
Q
D CP
19
Q0
D2
4
Q
D CP
18
Q1
D3
5
Q
D CP
17
Q2
D4
6
Q
16
Q3
D CP
D5
Q
15
Q4

FUNCTION T ABLE – 74ALS564A

INPUTS
OE CP Dn
OUTPUTS
REGISTER
L ↑ l L H L ↑ h H L L ↑ X NC NC Hold H ↑ X NC Z H ↑ Dn Dn Z
H = High voltage level h = High state must be present one setup time before the Low-to-High clock transition L = Low voltage level l = Low state must be present one setup time before the Low-to-High clock transition NC= No change X = Don’t care Z = High impedance “off” state ↑ = Low-to-High clock transition
= Not Low-to-High clock transition
↑
INTERNAL
Q0 – Q7
7
D CP
D6
8
Q
14
Q5
D CP
D7
9
D
Q
Q6
Q
CP
13
12
Q7
SC00117
p

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage –0.5 to +7.0 V Input voltage –0.5 to +7.0 V Input current –30 to +5 mA Voltage applied to output in High output state –0.5 to V Current applied to output in Low output state 48 mA Operating free-air temperature range 0 to +70 °C Storage temperature range –65 to +150 °C
PARAMETER RATING UNIT
CC
V
1996 Jul 01
5
Page 6
SYMBOL
PARAMETER
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
1
UNIT
VOHHigh-level output voltage
CC
,
IL
,
VOLLow-level output voltage
CC
,
IL
,
I
V
MAX, V
4V
ICCSupply current (total)
74ALS563A/74ALS564ALatch/flip-flop

RECOMMENDED OPERATING CONDITIONS

LIMITS
MIN NOM MAX
V
CC
V
V
I
IK
I
OH
I
OL
T
amb

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)
V
I
I
IH
I
OZH
I
OZL
I
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
Supply voltage 4.5 5.0 5.5 V High-level input voltage 2.0 V
IH
Low-level input voltage 0.8 V
IL
Input clamp current –18 mA High-level output current –2.6 mA Low-level output current 24 mA Operating free-air temperature range 0 +70 °C
LIMITS
MIN TYP2MAX
p
p
Input clamp voltage VCC = MIN, II = I
IK
Input current at maximum input voltage VCC = MAX, VI = 7.0V 0.1 mA
I
VCC = ±10%, VIL = MAX, VIH = MIN
VCC = MIN, VIL = MAX, VIH = MIN
IK
IOH = –0.4mA V
IOH = MAX 2.4 3.2 V
I
= 12mA 0.25 0.40 V
OL
I
= 24mA 0.35 0.50 V
OL
– 2 V
CC
–0.73 –1.5 V
High-level input current VCC = MAX, VI = 2.7V 20 µA Low-level input
IL
current Off-state output current,
High-level voltage applied Off-state output current,
Low-level voltage applied Output current
O
pp
3
= 5V, T
CC
74ALS563A 74ALS564A
74ALS563A
74ALS564A
= 25°C.
amb
CC
=
= 0.
I
VCC = MAX, VI = 2.7V 20 µA
VCC = MAX, VI = 0.4V –20 µA VCC = MAX, VO = 2.25V –30 –112 mA
I
CCH
I
CCL
I
CCZ
I
CCH
I
CCL
I
CCZ
VCC = MAX
VCC = MAX
7 12 mA 13 21 mA 15 24 mA 11 18 mA 17 27 mA 18 28 mA
–0.1 mA –0.2 mA
OS
.
1996 Jul 01
6
Page 7
74ALS563A
74ALS563A/74ALS564ALatch/flip-flop

AC ELECTRICAL CHARACTERISTICS

LIMITS
T
= 0°C to +70°C
amb
V
SYMBOL PARAMETER TEST CONDITION
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay Dn to Q
n
Propagation delay E to Q
n
Output enable time to High or Low level
Output disable time from High or Low level
Waveform 3
Waveform 2 Waveform 6
Waveform 7 Waveform 6
Waveform 7 Maximum clock frequency Waveform 1 45 MHz Propagation delay
CP to Q
n
Output enable time to High or Low level
Output disable time from High or Low level
74ALS564A
Waveform 1
Waveform 6
Waveform 7
Waveform 6
Waveform 7
= +5.0V ± 10%
CC
C
= 50pF, RL = 500Ω
L
MIN MAX
2.0
3.0
4.0
4.0
10.0
10.0
13.0
13.0
1.0
3.0
11.0
1.0
2.0
3.0
4.0
11.0
12.0
12.0
1.0
3.0
11.0
1.0
2.0
11.0
9.0
9.0
9.0
9.0
UNIT
ns
ns
ns
ns
ns
ns
ns

AC SETUP REQUIREMENTS

LIMITS
T
= 0°C to +70°C
amb
V
SYMBOL PARAMETER TEST CONDITION
tsu(H) t
(L)
su
th(H) t
(L)
h
Setup time, High or Low Dn to E
Hold time, High or Low Dn to E
74ALS563A
Waveform 4
Waveform 4
tw(H) E Pulse width, High Waveform 1 10.0 ns
tsu(H) t
(L)
su
th(H)
t
(L)
h
tw(H)
t
(L)
w
Setup time, High or Low Dn to CP
Hold time, High or Low Dn to CP
CP Pulse width, High or Low
74ALS564A
Waveform 5
Waveform 5
Waveform 5
= +5.0V ± 10%
CC
C
= 50pF, RL = 500Ω
L
MIN MAX
6.0
6.0
6.0
6.0
6.0
6.0
1.0
1.0
7.0
11.0
UNIT
ns
ns
ns
ns
ns
1996 Jul 01
7
Page 8
74ALS563A/74ALS564ALatch/flip-flop

AC WAVEFORMS

For all waveforms, VM = 1.3V. The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
max
CP
Qn
V
M
tw(H)
PLH
V
M
tw(L)t
V
M
V
M
t
PHL
V
M
SF00258
Waveform 1. Propagation Delay for Clock Input to Output,
Clock Pulse Widths, and Maximum Clock Frequency
Dn
Qn
V
M
t
PLH
V
M
t
PHL
V
V
M
M
SF00260
Waveform 3. Propagation Delay for Data to Output
Dn
E
V
M
(H) th(H)
t
su
V
M
V
M
V
tsu(L) th(L)
V
M
V
M
M
tw(H)
EV
Qn
M
t
PHL
V
M
V
M
V
t
PLH
M
V
M
SF00259
Waveform 2. Propagation Delay for Enable to Output and
Enable Pulse Width
Dn
CP
V
M
(H) th(H)
t
su
V
M
V
M
V
tsu(L) th(L)
V
M
V
M
M
SF00261
Waveform 4. Data Setup Time and Hold Times
OE
Qn, Qn
V
M
t
PZH
V
M
t
PHZ
V
M
VOH -0.3V
SC00114
Waveform 6. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
1996 Jul 01
SF00262
Waveform 5. Data Setup Time and Hold Times
OE
Qn, Qn
0V
V
M
t
PZL
V
M
t
PLZ
V
M
V
OL
3.5V
+0.3V
SC00115
Waveform 7. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
8
Page 9
74ALS563A/74ALS564ALatch/flip-flop

TEST CIRCUIT AND WAVEFORMS

V
PULSE
GENERATOR
CC
V
IN
R
T
D.U.T.
V
OUT
R
L
C
R
L
L
7.0V
Test Circuit for 3-State Outputs
SWITCH POSITION
TEST SWITCH
t
PLZ
, t
PZL
closed
All other open
DEFINITIONS:
R
= Load resistor;
L
see AC electrical characteristics for value.
CL= Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
OUT
of
NEGATIVE PULSE
POSITIVE PULSE
Family
74ALS
90%
10%
V
M
10%
90%
V
M
Input Pulse Definition
Amplitude
3.5V
t
w
V
M
10%
)
t
THL (tf
t
TLH (tr
f
)
t
)
TLH (tr
t
)
THL (tf
90%
V
M
t
w
INPUT PULSE REQUIREMENTS
V
M
1.3V
Rep.Rate
1MHz
t
w
500ns
AMP (V)
90%
0.3V
AMP (V)
10%
0.3V
t
TLHtTHL
2.0ns 2.0ns
SC00072
1996 Jul 01
9
Page 10
Latch flip–flop

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

1996 Jul 01
10
Page 11
Latch flip–flop

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

1996 Jul 01
11
Page 12
Latch flip–flop

DEFINITIONS

Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
LIFE SUPPORT APPLICA TIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
 
1996 Jul 01
12
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