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74als373
DATASHEETS (Philips)
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Datasheet 74als373 DATASHEETS (Philips)

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Page 1
INTEGRATED CIRCUITS
74ALS373/74ALS374
Latch/flip–flop
Product specification IC05 Data Handbook
 
1991 Feb 08
Page 2
74ALS373/74ALS374Latch/flip-flop
74ALS373 Octal transparent latch (3-State) 74ALS374 Octal D flip-flop (3-State)

FEA TURES

•8-bit transparent latch – 74ALS373
•8-bit positive edge triggered register – 74ALS374
•3-State output buffers
•Common 3-State output register
•Independent register and 3-State buffer operation
TYPE
74ALS373 6.0ns 14mA
TYPE
74ALS374 50MHz 17mA
TYPICAL
PROPAGATION DELAY
TYPICAL
f
MAX

ORDERING INFORMATION

ORDER CODE
DESCRIPTION COMMERCIAL RANGE
20-pin plastic DIP 74ALS373N, 74ALS374N SOT146-1
20-pin plastic SOL 74ALS373D, 74ALS374D SOT163-1
20-pin plastic SSOP
Type II
V
= 5V ±10%,
CC
T
= 0°C to +70°C
amb
74ALS373DB, 74ALS374DB SOT339-1
TYPICAL
SUPPLY CURRENT
(TOTAL)
TYPICAL
SUPPLY CURRENT
(TOTAL)
DRAWING
NUMBER

DESCRIPTION

The 74ALS373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE
The data on the D inputs is transferred to the latch outputs when the enable (E) input is High. The latch remains transparent to the data input while E is High, and stores the data that is present one setup time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors.
The active-Low output enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, latched or transparent data appears at the output.
When OE is High, the outputs are in High impedance “off” state, which means they will neither drive nor load the bus.
The 74ALS374 is an 8-bit edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of the D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors.
The active-Low output enable (OE) controls all eight 3-State buffers independent of the register operation. When OE is Low, the data in the register appears at the outputs. When OE is High, the outputs are in High impedance “off” state, which means they will neither drive nor load the bus.
) control gates.

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION
D0 – D7 Data inputs 1.0/1.0 20µA/0.1mA
E (74ALS373) Enable input (active-High) 1.0/1.0 20µA/0.1mA
OE Output enable inputs (active-Low) 1.0/1.0 20µA/0.1mA
CP (74ALS374) Clock pulse input (active rising edge) 1.0/1.0 20µA/0.1mA
Q0 – Q7 3-State outputs 130/240 2.6mA/24mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
1991 Feb 08 853–1243 01670
2
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Page 3
74ALS373/74ALS374Latch/flip-flop

PIN CONFIGURATION – 74ALS373

1
OE
2
Q0
3
D0
4
D1
5
Q1
6
Q2
7
D2
8
D3
9
Q3
10 11
GND
V
20 19
Q7
18
D7
17
D6
16
Q6
15
Q5
14
D5
13
D4
12
Q4 E

LOGIC SYMBOL – 74ALS373

3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
11
E OE
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

PIN CONFIGURATION – 74ALS374

CC
SF00250
1 2
Q0
3
D0
4
D1
5
Q1
6
Q2
7
D2
8
D3
9
Q3
10 11
GND
V
20OE
CC
19
Q7
18
D7
17
D6
16
Q6
15
Q5
14
D5
13
D4
12
Q4 CP
SF00253

LOGIC SYMBOL – 74ALS374

3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
11
CP OE
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
= Pin 20
V
CC
GND = Pin 10

IEC/IEEE SYMBOL – 74ALS373

1 11
3 4 7 8 13 14 17 18
EN1
EN2
2D
1
2 5 6 9 12 15 16 19
= Pin 20
V
CC
SF00251
GND = Pin 10
SF00254

IEC/IEEE SYMBOL – 74ALS374

1 11
2 5
6 9
12 15 16 19
SF00252
3 4 7 8 13 14 17 18
EN1
2D
C1
1
2 5
6 9
12 15 16 19
SC00098
1991 Feb 08
3
Page 4
INTERNAL REGISTER
OPERATING MODE
Enable and read register
Latch and read register
Disable outputs
74ALS373/74ALS374Latch/flip-flop
LOGIC DIAGRAM – 74ALS373
D0
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
V
= Pin 20
CC
GND = Pin 10
E
OE
D
Q
E
11
1
Q0
D
Q
E
2
Q1
D
Q
E
5
Q2
D
Q
E
6
Q3
D
E
9
D
Q
E
12
Q4

FUNCTION T ABLE – 74ALS373

INPUTS
OE E Dn
L H L L L L H H H H L ↓ l L L L ↓ h H H
L L X NC NC Hold H L X NC Z H H Dn Dn Z
H = High-voltage level h = High state must be present one setup time before the High-to-Low enable transition L = Low-voltage level l = Low state must be present one setup time before the High-to-Low enable transition NC= No change X = Don’t care Z = High impedance “off” state ↓ = High-to-Low enable transition
OUTPUTS
Q0 – Q7
Q5
D
E
15
Q
D
Q
Q6
Q
E
16
19
Q7
SF00256
p
1991 Feb 08
4
Page 5
INTERNAL REGISTER
OPERATING MODE
Load and read register
Disable outputs
74ALS373/74ALS374Latch/flip-flop

LOGIC DIAGRAM – 74ALS374

VCC = Pin 20 GND = Pin 10
CP
OE
D0
3
D CP
11
1
D1
4
Q0
D CP
2
Q
D2
7
Q1
D CP
5
Q
D3
8
Q2
D CP
6
Q
D4
13
Q
9
Q3
D CP
D5
14
D
Q
CP
12
Q4

FUNCTION T ABLE – 74ALS374

INPUTS
OE CP Dn
L ↑ l L L
L ↑ h H H
L ↑ X NC NC Hold H ↑ X NC Z H ↑ Dn Dn Z
H = High-voltage level h = High state must be present one setup time before the Low-to-High clock transition L = Low-voltage level l = Low state must be present one setup time before the Low-to-High clock transition NC= No change X = Don’t care Z = High impedance “off” state ↑ = Low-to-High clock transition
= Not Low-to-High clock transition
↑
OUTPUTS
Q0 – Q7
D6
17
Q
15
Q5
D CP
D7
18
D
Q
Q6
Q
CP
16
Q7
19
SF00257
p

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
1991 Feb 08
PARAMETER RATING UNIT
Supply voltage –0.5 to +7.0 V Input voltage –0.5 to +7.0 V Input current –30 to +5 mA Voltage applied to output in High output state –0.5 to V
CC
V Current applied to output in Low output state 48 mA Operating free-air temperature range 0 to +70 °C Storage temperature range –65 to +150 °C
5
Page 6
SYMBOL
PARAMETER
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
1
UNIT
VOHHigh-level output voltage
CC
,
IL
,
VOLLow-level output voltage
CC
,
IL
,
I
V
MAX, V
4V
ICCSupply current (total)
74ALS373/74ALS374Latch/flip-flop

RECOMMENDED OPERATING CONDITIONS

LIMITS
MIN NOM MAX
V
CC
V V
I
IK
I
OH
I
OL
T
amb

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)
V
I
I
IH
I
OZH
I
OZL
I
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
Supply voltage 4.5 5.0 5.5 V High-level input voltage 2.0 V
IH
Low-level input voltage 0.8 V
IL
Input clamp current –18 mA High-level output current –2.6 mA Low-level output current 24 mA Operating free-air temperature range 0 +70 °C
LIMITS
MIN TYP2MAX
p
p
Input clamp voltage VCC = MIN, II = I
IK
Input current at maximum input voltage VCC = MAX, VI = 7.0V 0.1 mA
I
VCC = ±10%, VIL = MAX, VIH = MIN
VCC = MIN, VIL = MAX, VIH = MIN
IK
IOH = –0.4mA V
IOH = MAX 2.4 3.2 V
I
= 12mA 0.25 0.40 V
OL
I
= 24mA 0.35 0.50 V
OL
– 2 V
CC
–0.73 –1.2 V
High-level input current VCC = MAX, VI = 2.7V 20 µA Low-level input
IL
current Off-state output current,
High-level voltage applied Off-state output current,
Low-level voltage applied Output current
O
pp
3
= 5V, T
CC
74ALS373 74ALS374
74ALS373
74ALS374
= 25°C.
amb
CC
=
= 0.
I
VCC = MAX, VI = 2.7V 20 µA
VCC = MAX, VI = 0.4V –20 µA VCC = MAX, VO = 2.25V –30 –112 mA
I
CCH
I
CCL
I
CCZ
I
CCH
I
CCL
I
CCZ
VCC = MAX
VCC = MAX
7 16 mA 14 25 mA 17 27 mA
11 19 mA 19 29 mA 20 31 mA
–0.1 mA –0.2 mA
OS
.
1991 Feb 08
6
Page 7
74ALS373
74ALS373/74ALS374Latch/flip-flop

AC ELECTRICAL CHARACTERISTICS

LIMITS
T
= 0°C to +70°C
amb
V
SYMBOL PARAMETER TEST CONDITION
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay Dn to Qn
Propagation delay E to Qn
Output enable time to High or Low level
Output disable time from High or Low level
Waveform 3
Waveform 2 Waveform 6
Waveform 7 Waveform 6
Waveform 7 Maximum clock frequency Waveform 1 50 MHz Propagation delay
CP to Qn Output enable time
to High or Low level Output disable time
from High or Low level
74ALS374
Waveform 1
Waveform 6
Waveform 7
Waveform 6
Waveform 7
= +5.0V ± 10%
CC
C
= 50pF, RL = 500Ω
L
MIN MAX
2.0
2.0
3.0
3.0
2.0
3.0
2.0
2.0
3.0
4.0
12.0
14.0
14.0
14.0
14.0
14.0
10.0
12.0
12.0
14.0
3.0
3.0
2.0
3.0
11.0
10.0
12.0
9.0
UNIT
ns
ns
ns
ns
ns
ns
ns

AC SETUP REQUIREMENTS

LIMITS
T
= 0°C to +70°C
amb
V
SYMBOL PARAMETER TEST CONDITION
tsu(H) t
(L)
su
th(H) t
(L)
h
Setup time, High or Low Dn to E
Hold time, High or Low Dn to E
74ALS373
Waveform 4
Waveform 4
tw(H) E Pulse width, High Waveform 2 10.0 ns
tsu(H) t
(L)
su
th(H)
t
(L)
h
tw(H)
t
(L)
w
Setup time, High or Low Dn to CP
Hold time, High or Low Dn to CP
CP Pulse width, High or Low
74ALS374
Waveform 5
Waveform 5
Waveform 1
= +5.0V ± 10%
CC
C
= 50pF, RL = 500Ω
L
MIN MAX
6.0
6.0
6.0
6.0
6.0
6.0
1.0
1.0
10.0
10.0
UNIT
ns
ns
ns
ns
ns
1991 Feb 08
7
Page 8
74ALS373/74ALS374Latch/flip-flop

AC WAVEFORMS

For all waveforms, VM = 1.3V. The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
max
CP
Qn
V
M
tw(H)
PLH
V
M
tw(L)t
V
M
V
M
t
PHL
V
M
SF00258
Waveform 1. Propagation Delay for Clock Input to Output,
Clock Pulse Widths, and Maximum Clock Frequency
Dn
Qn
V
M
t
PLH
V
M
t
PHL
V
V
M
M
SF00260
Waveform 3. Propagation Delay for Data to Output
Dn
E
V
M
(H) th(H)
t
su
V
M
V
M
V
tsu(L) th(L)
V
M
V
M
M
tw(H)
EV
Qn
M
t
PHL
V
M
V
M
V
t
PLH
M
V
M
SF00259
Waveform 2. Propagation Delay for Enable to Output and
Enable Pulse Width
Dn
CP
V
M
(H) th(H)
t
su
V
M
V
M
V
tsu(L) th(L)
V
M
V
M
M
SF00261
Waveform 4. Data Setup Time and Hold Times
OE
Qn
V
M
t
PZH
V
M
t
PHZ
V
M
VOH -0.3V
SC00099
Waveform 6. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
1991 Feb 08
SF00262
Waveform 5. Data Setup Time and Hold Times
OE
Qn
0V
V
M
t
PZL
V
M
t
PLZ
V
M
V
OL
3.5V
+0.3V
SC00100
Waveform 7. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
8
Page 9
74ALS373/74ALS374Latch/flip-flop

TEST CIRCUIT AND WAVEFORMS

V
CC
PULSE
GENERATOR
V
IN
R
T
D.U.T.
V
OUT
R
L
C
R
L
L
Test Circuit for 3-State Outputs
SWITCH POSITION
TEST SWITCH
t
PLZ
, t
PZL
closed
All other open
DEFINITIONS:
R
= Load resistor;
L
see AC electrical characteristics for value.
= Load capacitance includes jig and probe capacitance;
C
L
see AC electrical characteristics for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
OUT
7.0V
of
NEGATIVE PULSE
POSITIVE PULSE
Family
74ALS
90%
10%
Amplitude
t
w
V
M
10%
)
V
90%
M
t
THL (tf
t
TLH (tr
f
)
t
TLH (tr
t
THL (tf
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
V
Rep.Rate
M
3.5V
1.3V
1MHz
V
10%
)
)
90%
t
w
500ns
M
V
M
t
TLHtTHL
2.0ns 2.0ns
90%
10%
AMP (V)
0.3V
AMP (V)
0.3V
SC00072
1991 Feb 08
9
Page 10
74ALS373/74ALS374Latch/flip–flop

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

1991 Feb 08
10
Page 11
74ALS373/74ALS374Latch/flip–flop

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

1991 Feb 08
11
Page 12
74ALS373/74ALS374Latch/flip–flop

SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1

1991 Feb 08
12
Page 13
74ALS373/74ALS374Latch/flip–flop

DEFINITIONS

Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
LIFE SUPPORT APPLICA TIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
 
1991 Feb 08
13
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