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74als273
DATASHEETS (Philips)
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Datasheet 74als273 DATASHEETS (Philips)

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Page 1
INTEGRATED CIRCUITS
74ALS273
Octal D–type flip–flop
Product specification IC05 Data Handbook
 
1991 Feb 08
Page 2
74ALS273Octal D-type flip-flop

FEA TURES

•Eight edge-triggered D-type flip-flops
•Buffered common clock
•Buffered asynchronous master reset
•See 74ALS377 for clock enable version
•See 74ALS373 for transparent latch version
•See 74ALS374 for 3-State version

DESCRIPTION

The 74ALS273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR simultaneously .
The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced Low independently of clock or data inputs by a Low voltage level on the MR
The device is useful for applications where the true output only is required and the CP and MR
TYPE
74ALS273 95MHz 16mA
) inputs load and reset all flip-flops
input.
are common to all flip-flops.
TYPICAL
TYPICAL f
MAX
SUPPLY CURRENT
(TOTAL)

PIN CONFIGURATION

20
1
MR
2
Q0
3
D0
4
D1
5
Q1
6
Q2
7
D2
8
D3
9
Q3 Q4
10 11
GND
V
CC
Q7
19
D7
18
D6
17
Q6
16
Q5
15
D5
14
D4
13 12
CP

ORDERING INFORMA TION

ORDER CODE
DESCRIPTION COMMERCIAL RANGE
V
= 5V ±10%,
CC
T
= 0°C to +70°C
amb
20-pin plastic DIP 74ALS273N SOT146-1
20-pin plastic SO 74ALS273D SOT163-1
20-pin plastic SSOP
Type II
74ALS273DB SOT339-1
DRAWING
NUMBER
SF00346

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION
D0 – D7 Data inputs 1.0/2.0 20µA/0.2mA
CP Clock pulse input (active rising edge) 1.0/1.0 20µA/0.1mA
MR Master Reset input (active-Low) 1.0/1.0 20µA/0.1mA
Q0 – Q7 3-State outputs 130/240 2.6mA/24mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.

LOGIC SYMBOL

11
1
V
= Pin 20
CC
GND = Pin 10
CP MR
3 4 7 8 13 14 1817
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
SF00347

IEC/IEEE SYMBOL

74ALS (U.L.)
HIGH/LOW
1 11
32 4
7 8 13 14 17 18
R
C1
1D
LOAD VALUE
HIGH/LOW
5 6 9 12 15 16 19
SF00348
1991 Feb 08 853–1398 01670
2
Page 3
OPERATING MODE
SYMBOL
PARAMETER
UNIT
74ALS273Octal D-type flip-flop

LOGIC DIAGRAM

V
= Pin 20
CC
GND = Pin 10
CP
MR
D0
3
11
DQ
1
CP
RD
Q0
D1
2
4
DQ
CP
RD
Q1
D2
5
7
DQ
CP
RD
Q2
D3
8
6
DQ
CP
RD
D4
13
DQ
CP
RD
9
Q3

FUNCTION TABLE

INPUTS OUTPUTS
MR CP Dn Qn
L X X L Reset (clear) H ↑ h H Load “1” H ↑ l L Load “0”
H = High-voltage level h = High state must be present one setup time before the Low-to-High clock transition L = Low-voltage level l = Low state must be present one setup time before the Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition
Q4
12
D5
14
DQ
CP
RD
Q5
D6
15
17
DQ
CP
RD
Q6
D7
16
18
DQ
CP
RD
19
Q7
SF00349

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage –0.5 to +7.0 V Input voltage –0.5 to +7.0 V Input current –30 to +5 mA Voltage applied to output in High output state –0.5 to V Current applied to output in Low output state 48 mA Operating free-air temperature range 0 to +70 °C Storage temperature range –65 to +150 °C
PARAMETER RATING UNIT

RECOMMENDED OPERATING CONDITIONS

V
T
CC
V V
I
IK
I
OH
I
OL
amb
Supply voltage 4.5 5.0 5.5 V High-level input voltage 2.0 V
IH
Low-level input voltage 0.8 V
IL
Input clamp current –18 mA High-level output current –2.6 mA Low-level output current 24 mA Operating free-air temperature range 0 +70 °C
CC
LIMITS
MIN NOM MAX
V
1991 Feb 08
3
Page 4
SYMBOL
PARAMETER
TEST CONDITIONS
1
UNIT
VOHHigh-level output voltage
CC
,
IL
,
VOLLow-level output voltage
CC
,
IL
,
IILLow-level input current
V
MAX, V
4V
ICCSupply current (total)
V
MAX
74ALS273Octal D-type flip-flop

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
MIN TYP
p
p
V
I
I
IH
I
Input clamp voltage VCC = MIN, II = I
IK
Input current at maximum input voltage VCC = MAX, VI = 7.0V 0.1 mA
I
High-level input current VCC = MAX, VI = 2.7V 20 µA
MR, CP
I
CCH
I
CCL
O
p
Output current
pp
3
VCC±10%, VIL = MAX, VIH = MIN
VCC = MIN, VIL = MAX, VIH = MIN
IK
Dn
CC
=
= 0.
I
VCC = MAX, VO = 2.25V –30 –112 mA
=
CC
IOH = –0.4mA V
IOH = MAX 2.4 3.2 V
I
= 12mA 0.25 0.40 V
OL
I
= 24mA 0.35 0.50 V
OL
– 2 V
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
= 5V, T
CC
amb
= 25°C.
2
MAX
–0.73 –1.5 V
–0.1 mA –0.2 mA
12 18 mA 21 29 mA
OS
.

AC ELECTRICAL CHARACTERISTICS

LIMITS
T
= 0°C to +70°C
amb
V
SYMBOL PARAMETER TEST CONDITION
= +5.0V ± 10%
CC
C
= 50pF, RL = 500Ω
L
MIN MAX
f
MAX
t
PLH
t
PHL
t
PHL
Maximum clock frequency Waveform 1 65 MHz Propagation delay
CP to Qn Propagation delay
MR
to Qn
Waveform 1
Waveform 2 4.0 12.0 ns
2.0
3.0
8.0
11.0

AC SETUP REQUIREMENTS

LIMITS
T
= 0°C to +70°C
amb
V
SYMBOL PARAMETER TEST CONDITION
tsu(H)
t
(L)
su
th(H) t
(L)
h
tw(H)
t
(L)
w
Setup time, High or Low Dn to CP
Hold time, High or Low Dn to CP
CP pulse width, High or Low
Waveform 3
Waveform 3
Waveform 1 tw(L) MR pulse width, Low Waveform 2 7.0 ns t
REC
Recovery time, MR
to CP
Waveform 2 12.0 ns
= +5.0V ± 10%
CC
C
= 50pF, RL = 500Ω
L
MIN MAX
5.0
5.0
0.0
0.0
6.0
8.0
UNIT
ns
UNIT
ns
ns
ns
1991 Feb 08
4
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74ALS273Octal D-type flip-flop

AC WAVEFORMS

For all waveforms, VM = 1.3V.
1/f
max
CP
V
M
tw(H)
PHL
V
M
tw(L)t
V
M
t
PLH
Dn
V
V
M
M
th(H)tsu(H)
V
V
M
M
th(L)tsu(L)
Qn
V
M
V
M
Waveform 1. Propagation Delay for Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
MR
CP
Qn
V
M
tw(L)
t
PHL
V
M
t
REC
V
M
V
M
Waveform 2. Master Reset Pulse Width, Master Reset to
Output Delay, and Master Reset to Clock Recovery T ime

TEST CIRCUIT AND WAVEFORMS

V
CC
PULSE
GENERATOR
V
IN
D.U.T.
V
OUT
SF00294
SC00065
NEGATIVE PULSE
CP
90%
V
M
Waveform 3. Data Setup and Hold Times
t
w
TLH (tr
V
10%
)
V
M
10%
)
t
THL (tf
f
t
90%
M
V
M
SC00064
AMP (V)
0.3V
R
T
C
R
L
L
Test Circuit for Totem-pole Outputs
DEFINITIONS:
R
= Load resistor;
L
see AC electrical characteristics for value.
CL= Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
R
= T ermination resistance should be equal to Z
T
pulse generators.
1991 Feb 08
OUT
of
POSITIVE PULSE
5
10%
Family
74ALS
t
TLH (tr
90%
V
M
Input Pulse Definition
Amplitude
3.5V
)
t
)
THL (tf
90%
V
M
t
w
10%
INPUT PULSE REQUIREMENTS
V
M
1.3V
Rep.Rate
1MHz
500ns
t
w
t
TLHtTHL
2.0ns 2.0ns
AMP (V)
0.3V
SC00005
Page 6
74ALS273Octal D–type flip–flop

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

1991 Feb 08
6
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74ALS273Octal D–type flip–flop

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

1991 Feb 08
7
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74ALS273Octal D–type flip–flop

SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1

1991 Feb 08
8
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74ALS273Octal D–type flip–flop

DEFINITIONS

Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
LIFE SUPPORT APPLICA TIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
 
1991 Feb 08
9
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