Datasheet 74als240a DATASHEETS (Philips)

Page 1
INTEGRATED CIRCUITS
74ALS240A/74ALS240A–1
Octal inverter buffer (3–State)
Product specification IC05 Data Handbook
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1991 Feb 08
Page 2
Octal inverter buffer (3-State)

FEA TURES

•Octal bus interface
•3-State buffer outputs sink 24mA and source 15mA
•The -1 version sinks 48 mA

DESCRIPTION

The 74ALS240A is an octal buffer that is ideal for driving bus lines or buffer memory address registers. The outputs are all capable of sinking 24mA and sourcing up to 15mA, producing very good capacitive drive characteristics. The device features two output enables, OE
The 74ALS240A-1 sinks 48 mA IOL if the VCC is limited to
5.0V ±0.25V.
74ALS240A-1 4.5ns 15mA
a and OEb, each controlling four of the 3-State outputs.
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
74ALS240A 4.5ns 15mA

PIN CONFIGURATION

1
OEa
2
Ia0
3
Y
b0
4
Ia1
b1
5
Y
Ia2
6
b2
Y
7
Ia3
8
Y
b3
9
GND
10 11

ORDERING INFORMA TION

ORDER CODE
COMMERCIAL RANGE
DESCRIPTION
20-pin plastic DIP
20-pin plastic SOL
20-pin plastic SSOP
Type II
V
CC
T
amb
74ALS240AN,
74ALS240A-1N
74ALS240AD,
74ALS240A-1D
74ALS240ADB,
74ALS240A-1DB
74ALS240A/
74ALS240A-1
V
20
CC
19
OEb
18
a0
Y
17
Ib0
a1
16
Y Ib1
15
a2
Y
14
Ib2
13
Y
a3
12
Ib3
= 5V ±10%,
= 0°C to +70°C
SF00320
DRAWING
NUMBER
SOT146-1
SOT163-1
SOT339-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION
Ian, Ibn Data inputs 1.0/1.0 20µA/0.1mA
OEa, OEb Output Enable inputs (active-Low) 1.0/1.0 20µA/0.1mA
Yan, Ybn Data outputs 750/240 15mA/24mA Yan, Ybn Data outputs (-1 version) 750/480 15mA/48mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.

LOGIC SYMBOL

119OEa
VCC = Pin 20 GND = Pin 10
2 4 6 8 17 15 13 11
Ia0 Ia1 Ia2 Ia3 Ib0 Ib1 Ib2 Ib3
OEb
Ya0 Ya1 Ya2 Ya3 Yb0 Yb1 Yb2 Yb3
181614123579
SF00321

IEC/IEEE SYMBOL

74ALS (U.L.)
HIGH/LOW
1
19
17 15
13
11
EN1 EN2
2 4 6 8
2D
1
2
LOAD VALUE
HIGH/LOW
18 16 14 12
3 5 7 9
SF00322
1991 Feb 08 853–1244 01670
2
Page 3
I
Current applied to output in Low output state
SYMBOL
UNIT
IOLLow-level output current
Octal inverter buffer (3-State)

LOGIC DIAGRAM

OE
Ib0
Ib1
Ib2
Ib3
17
15
13
11
10
b
3
5
7
9
SF00323
Yb0
Yb1
Y
Y
b2
b3
Ia0
Ia1
Ia2
Ia3
OE
a
VCC = Pin 20 GND = Pin 10
2
4
6
8
1
18
Y
a0
16
Ya1
14
Y
a2
12
Y
a3

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
OUT
T
amb
T
stg
Supply voltage –0.5 to +7.0 V Input voltage –0.5 to +7.0 V Input current –30 to +5 mA Voltage applied to output in High output state –0.5 to V
pp
p
Operating free-air temperature range 0 to +70 °C Storage temperature range –65 to +150 °C
PARAMETER RATING UNIT
p

FUNCTION TABLE

OEa Ia OEb Ib Ya Yb
L L L L H H L H L H L L
H X H X Z Z
H = High voltage level L = Low voltage level X = Don’t care Z = High impedance “off” state
All versions 48 mA
-1 version 96 mA
74ALS240A/
74ALS240A-1
INPUTS OUTPUTS
CC
V

RECOMMENDED OPERATING CONDITIONS

PARAMETER
V
CC
V V
I
IK
I
OH
T
amb
NOTE:
1. The 48mA limit applies only under the condition of V
Supply voltage 4.5 5.0 5.5 V High-level input voltage 2.0 V
IH
Low-level input voltage 0.8 V
IL
Input clamp current –18 mA High-level output current –15 mA
p
Operating free-air temperature range 0 +70 °C
CC
= 5.0V ±5%.
LIMITS
MIN NOM MAX
All versions 24 mA
-1 version 48
1
mA
1991 Feb 08
3
Page 4
SYMBOL
PARAMETER
TEST CONDITIONS
1
UNIT
CC
,
IL
,
VOHHigh level out ut voltage
All versions
CC
,
IL
,
VOLLow level out ut voltage
Octal inverter buffer (3-State)

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)
MIN TYP
IOH = –0.4mA V
IOH = –3mA 2.4 3.2 V
IOH = –15mA 2.0
I
= 12mA 0.25 0.40 V
OL
I
= 24mA 0.35 0.50 V
OL
I
= 48mA 0.35 0.50 V
OL
V
I
OZH
I
OZL
I
I I
I
IH
I
CC
VCC±10%, VIL = MAX,
-
p
VIH = MIN VCC = MIN, VIL = MAX,
V
= MIN
IH
VCC = MIN, VIL = MAX,
-
p
-1 version
Input clamp voltage VCC = MIN, II = I
IK
Input current at maximum input voltage VCC = MAX, VI = 7.0V 0.1 mA
I
VIH = MIN VCC = 4.75V, VIL = MAX,
V
= MIN
IH
IK
High-level input current VCC = MAX, VI = 2.7V 20 µA Low-level input current VCC = MAX, VI = 0.4V –0.1 mA
IL
Off-state output current, High-level voltage applied
Off-state output current, Low-level voltage applied
Output current
O
Supply current (total)
3
I
CCH
I
CCL
I
CCZ
VCC = MAX, VI = 2.7V 20 µA
VCC = MAX, VI = 0.4V –20 µA VCC = MAX, VO = 2.25V –30 –112 mA
VCC = MAX
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
= 5V, T
CC
amb
= 25°C.
CC
74ALS240A-1
LIMITS
2
MAX
– 2 V
–0.73 –1.5 V
2.5 11 mA
19.5 23 mA 23 30
OS
74ALS240A/
.

AC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER TEST CONDITION
1991 Feb 08
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay In to Yn
Output Enable time to High or Low level
Output disable time from High or Low level
LIMITS
T
= 0°C to +70°C
amb
V
= +5.0V ± 10%
CC
C
= 50pF, RL = 500Ω
L
UNIT
MIN MAX
Waveform 1 Waveform 2
Waveform 3 Waveform 2
Waveform 3
2.0
2.0
2.0
3.0
2.0
3.0
9.0
9.0
10.0
12.0
10.0
12.0
ns
ns
ns
4
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Octal inverter buffer (3-State)

AC WAVEFORMS

For all waveforms, VM = 1.3V.
Ian, Ibn
Waveform 1. Propagation Delay for Non-Inverting Output
n
OE
n
Y
Waveform 2. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
V
M
t
PHL
Yn
V
M
t
PZH
V
M
V
M
t
PLH
V
V
M
M
V
M
t
PHZ
VOH –0.3V
SF00328
0V
SC00077
74ALS240A/
74ALS240A-1
OE
n
n
Y
V
M
t
PZL
V
Waveform 3. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
V
M
t
PLZ
M
VOL +0.3V
SC00078
3.5V

TEST CIRCUIT AND WAVEFORMS

V
CC
V
PULSE
GENERATOR
IN
R
T
Test Circuit for 3-State Outputs
SWITCH POSITION
TEST SWITCH
t
PLZ
, t
PZL
closed
All other open
DEFINITIONS:
R
= Load resistor;
L
see AC electrical characteristics for value.
= Load capacitance includes jig and probe capacitance;
C
L
see AC electrical characteristics for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
D.U.T.
V
OUT
C
L
t
7.0V
R
L
R
L
NEGATIVE PULSE
POSITIVE PULSE
90%
10%
V
M
10%
t
THL (tf
t
TLH (tr
90%
V
M
w
V
M
10%
)
f
)
t
)
TLH (tr
t
)
THL (tf
90%
V
M
t
w
90%
10%
AMP (V)
0.3V
AMP (V)
0.3V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
V
Rep.Rate
M
3.5V
1.3V
1MHz
t
w
500ns
t
TLHtTHL
2.0ns 2.0ns
SC00072
OUT
Family
Amplitude
74ALS
of
1991 Feb 08
5
Page 6
Octal inverter buffer (3–State)

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

74ALS240A/74ALS240A–1
1991 Feb 08
6
Page 7
Octal inverter buffer (3–State)

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

74ALS240A/74ALS240A–1
1991 Feb 08
7
Page 8
Octal inverter buffer (3–State)

SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1

74ALS240A/74ALS240A–1
1991 Feb 08
8
Page 9
Octal inverter buffer (3–State)
74ALS240A/74ALS240A–1

DEFINITIONS

Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
LIFE SUPPORT APPLICA TIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors 811 East Arques Avenue
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381
 
1991 Feb 08
9
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