Page 1
INTEGRATED CIRCUITS
74ALS161B/74ALS163B
4-bit binary counter
Product specification 1991 Feb 08
IC05 Data Handbook
Page 2
Philips Semiconductors Product specification
74ALS161B/74ALS163B4-bit binary counter
74ALS161B 4-bit binary counter, asynchronous reset
74ALS163B 4-bit binary counter, synchronous reset
FEA TURES
•Synchronous counting and loading
•Two count enable inputs for n-bit cascading
•Positive edge-triggered clock
•Asynchronous reset (74ALS161B)
•Synchronous reset (74ALS163B)
•High speed synchronous expansion
•Typical count rate of 140MHz
TYPICAL
TYPE
74ALS161B 140MHz 10mA
74ALS163B 140MHz 10mA
TYPICAL f
MAX
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
16-pin plastic DIP 74ALS161BN, 74ALS163BN SOT38-4
16-pin plastic SO 74ALS161BD, 74ALS163BD SOT109-1
16-pin plastic SSOP
Type II
V
= 5V ±10%,
CC
T
= 0°C to +70°C
amb
74ALS161BDB,
74ALS163BDB
SUPPLY CURRENT
(TOTAL)
DRAWING
NUMBER
SOT338-1
DESCRIPTION
Synchronous presettable 4-bit binary counters (74ALS161B,
74ALS163B) feature an internal carry look-ahead and can be used
for high speed counting. Synchronous operation is provided by
having all flip-flops clocked simultaneously on the positive-going
edge of the clock. The clock input is buffered.
The outputs of the counters may be preset to High or Low level. A
Low level at the parallel enable (PE
action and causes the data at the D0 – D3 inputs to be loaded into
the counter on the positive-going edge of the clock (provided that
the setup and hold requirements for PE
regardless of the levels at count enable (CEP, CET) inputs.
A Low level at the master reset (MR
of the flip-flops (Q0 – Q3) in 74ALS161B to Low levels, regardless of
the levels at CP, PE
asynchronous clear function).
For the 74ALS163B the clear function is synchronous. A Low level
at the synchronous reset (SR
flip-flops (Q0 – Q3) to Low levels after the next positive-going
transition on the clock (CP) input ( provided that the setup and hold
time requirements for SR
the levels at CP, PE
feature enables the designer to modify the maximum count with only
one external NAND gate (see Figure 1).
The carry look-ahead simplifies serial cascading of the counters.
Both count enable (CEP and CET) inputs must be High to count.
The CET input is fed forward to enable the TC output. The TC
output thus enabled will produce a High output pulse of a duration
approximately equal to the High level output of Q0. This pulse can
be used to enable the next cascaded stage (see Figure 2).
The TC output is subjected to decoding spikes due to internal race
conditions, Therefore, it is not recommended for use as clock or
asynchronous reset for flip-flops, registers, or counters.
, CET and CEP inputs (thus providing an
are met). This action occurs regardless of
, CET and CEP inputs. The synchronous reset
) input disables the counting
are met). Preset takes place
) input sets all the four outputs
) input sets all four outputs of the
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
D0 – D3 Data inputs 1.0/1.0 20µA/0.1mA
CEP Count enable parallel input (active-Low) 1.0/1.0 20µA/0.1mA
CET Count enable trickle input (active-Low) 1.0/1.0 20µA/0.1mA
CP Clock input (active rising edge) 1.0/1.0 20µA/0.1mA
PE Parallel enable input (active-Low) 1.0/1.0 20µA/0.1mA
MR Asynchronous master reset input (active-Low) for 74ALS161B 1.0/1.0 20µA/0.1mA
SR Asynchronous reset input (active-Low) for 74ALS163B 1.0/1.0 20µA/0.1mA
Q0 – Q3 Flip-flop outputs 20/80 0.4mA/8mA
TC T erminal count output (active-Low) 20/80 0.4mA/8mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
1991 Feb 08 853–1350 01670
2
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Page 3
Philips Semiconductors Product specification
74ALS161B/74ALS163B4-bit binary counter
STATE DIAGRAM
0 1 2 3
15
14
13
12 11 10 9
APPLICATIONS
CLOCK
4
5
6
7
8
SF00664
V
CC
D3D0
D1 D2
PE
CEP
CET
CP
SR
Q0 Q1 Q2 Q3
TC74ALS163B
Figure 1. Maximum Count Modifying Scheme
Terminal Count = 6
H H = Enable count
or
L L = Disable count
CP
PE
CEP
74ALS163B
CET
CP
SR
Q0 Q1 Q2 Q3
D1 D2 D3D0
TC
PE
CEP
CET
CP
SR
Q0 Q1 Q2 Q3
Figure 2. Synchronous Multistage Counting Scheme
SC00086
D1 D2 D3D0
74ALS163B 74ALS163B 74ALS163B 74ALS163B
TC
PE
CEP
CET
CP
SR
Q0 Q1 Q2 Q3
D1 D2 D3D0
TC
PE
CEP
CET
CP
SR
Q0 Q1 Q2 Q3
D1 D2 D3D0
TC
PE
CEP
CET
CP
SR
Q0 Q1 Q2 Q3
D1 D2
D3D0
TC
SC00087
1991 Feb 08
3
Page 4
Philips Semiconductors Product specification
74ALS161B/74ALS163B4-bit binary counter
PIN CONFIGURATION – 74ALS161B
MR
CP
CEP
1
2
D0
3
D1
4
D2
5
6
D3
16
15
14
13
12
11
107
98GND PE
V
TC
Q0
Q1
Q2
Q3
CET
LOGIC SYMBOL – 74ALS161B
34
9
7
10
2
1MR
PE
CEP
CET
CP
Q0 Q1
D1 D2
Q2 Q3
56
D3D0
TC 15
PIN CONFIGURATION – 74ALS163B
1
CC
SF00656
SR
CP
CEP
2
D0
3
D1
4
D2
5
6
D3
16
15
14
13
12
11
107
98GND PE
V
TC
Q0
Q1
Q2
Q3
CET
CC
SF00657
LOGIC SYMBOL – 74ALS163B
34
9
7
10
2
1SR
PE
CEP
CET
CP
Q0 Q1
D1 D2
56
D3D0
TC 15
Q2 Q3
= Pin 16
CC
GND = Pin 8
14 13
12 11V
IEC/IEEE SYMBOL – 74ALS161B
1
9
7
10
2
3
4
5
6
R
M1
G3
G4
C2 /1,3,4+
1
,2 D
CTR DIV 16
4 CT=15
12 11V
SF00659
SF00658
= Pin 16
CC
GND = Pin 8
14 13
IEC/IEEE SYMBOL – 74ALS163B
1
9
7
10
2
14
13
12
11
15
SF00660
3
4
5
6
2R
M1
G3
G4
C2 /1,3,4+
1
,2 D
CTR DIV 16
4 CT=15
14
13
12
11
15
SF00661
1991 Feb 08
4
Page 5
Philips Semiconductors Product specification
OPERATING MODE
Parallel load
Hold (do nothing)
74ALS161B/74ALS163B4-bit binary counter
LOGIC DIAGRAM – 74ALS161B
2
CP
1
MR
9
PE
10
CET
7
CEP
3
D0
4
D1
R
DCPQ
R
DCPQ
14
Q
Q0
Q
5
D2
D3
VCC = Pin 16
GND = Pin 8
6
R
DCPQ
R
DCPQ
Q
Q
MODE SELECTION FUNCTION TABLE – 74ALS161B
INPUTS OUTPUTS
MR CP CEP CET PE Dn Qn TC
L X X X X X L L Reset (clear)
H ↑ X X l l L L
H ↑ X X l h H (a)
H ↑ h h h X count (a) Count
h X l X h X qn (a)
h X X l h X qn L
H = High-voltage level
h = High state must be present one setup time before the Low-to-High clock transition
L = Low-voltage level
l = Low state must be present one setup time before the Low-to-High clock transition
qn = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition
X = Don’t care
(a) = The output is High when CET is High and the counter is at terminal count (HHHH)
↑ = Low-to-High clock transition
13
Q1
12
Q2
11
Q3
15
TC
SF00662
1991 Feb 08
5
Page 6
Philips Semiconductors Product specification
OPERATING MODE
Parallel load
Hold (do nothing)
74ALS161B/74ALS163B4-bit binary counter
LOGIC DIAGRAM – 74ALS163B
2
CP
1
SR
9
PE
10
CET
7
CEP
3
D0
DCPQ
14
Q
4
D1
DCPQ
Q0
Q
5
D2
DCPQ
Q
6
D3
DCPQ
Q
VCC = Pin 16
GND = Pin 8
MODE SELECTION FUNCTION TABLE – 74ALS163B
INPUTS OUTPUTS
SR CP CEP CET PE Dn Qn TC
l ↑ X X X X L L Reset (clear)
h ↑ X X l l L L
h ↑ X X l h H (a)
h ↑ h h h X count (a) Count
h X l X h X qn (a)
h X X l h X qn L
H = High-voltage level
h = High state must be present one setup time before the Low-to-High clock transition
L = Low-voltage level
l = Low state must be present one setup time before the Low-to-High clock transition
qn = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition
X = Don’t care
(a) = The output is High when CET is High and the counter is at terminal count (HHHH)
↑ = Low-to-High clock transition
13
Q1
12
Q2
11
Q3
15
TC
SF00663
1991 Feb 08
6
Page 7
Philips Semiconductors Product specification
SYMBOL
PARAMETER
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
1
UNIT
VOHHigh-level output voltage
CC
,
IL
,
I
4mA
V
2
V
VOLLow-level output voltage
CC
,
IL
,
74ALS161B/74ALS163B4-bit binary counter
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
V
V
I
T
T
CC
V
I
IN
OUT
OUT
amb
stg
Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
IN
Input current –30 to +5 mA
Voltage applied to output in High output state –0.5 to V
Current applied to output in Low output state 16 mA
Operating free-air temperature range 0 to +70 °C
Storage temperature range –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
T
V
CC
V
V
I
IK
I
OH
I
OL
amb
Supply voltage 4.5 5.0 5.5 V
High-level input voltage 2.0 V
IH
Low-level input voltage 0.8 V
IL
Input clamp current –18 mA
High-level output current –0.4 mA
Low-level output current 8 mA
Operating free-air temperature range 0 +70 °C
PARAMETER RATING UNIT
CC
V
LIMITS
MIN NOM MAX
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
MIN TYP2MAX
p
p
V
I
I
IH
I
IL
I
O
I
CC
Input clamp voltage VCC = MIN, II = I
IK
Input current at minimum input voltage VCC = MAX, VI = 7.0V 0.1 mA
I
High-level input current VCC = MAX, VI = 2.7V 20 µA
Low-level input current VCC = MAX, VI = 0.4V –0.1 mA
Output current
3
Supply current (total) VCC = MAX 10 21 mA
VCC = ±10%, VIL = MAX,
VIH = MIN
VCC = MIN, VIL = MAX,
VIH = MIN
IK
= –0.
OH
I
= 4mA 0.25 0.40 V
OL
I
= 8mA 0.35 0.50 V
OL
VCC = MAX, VO = 2.25V –30 –112 mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
= 5V, T
CC
amb
= 25°C.
CC
–
–0.73 –1.5 V
OS
.
1991 Feb 08
7
Page 8
Philips Semiconductors Product specification
74ALS161B/74ALS163B4-bit binary counter
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
= 0°C to +70°C
amb
V
SYMBOL PARAMETER TEST CONDITION
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PHL
Maximum clock frequency Waveform 1 100 MHz
Propagation delay
CP to Qn
Propagation delay
CP to TC
Propagation delay
CET to TC
Propagation delay
MR
to Qn
Propagation delay
MR
to TC
74ALS161B Waveform 3 8.0 15.0 ns
74ALS163B Waveform 3 11.0 19.0 ns
Waveform 1
Waveform 1
Waveform 2
= +5.0V ± 10%
CC
C
= 50pF, RL = 500Ω
L
MIN MAX
4.0
6.0
6.0
8.0
3.0
3.0
13.0
16.0
16.0
16.0
10.0
10.0
UNIT
ns
ns
ns
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
= 0°C to +70°C
amb
V
SYMBOL PARAMETER TEST CONDITION
tsu(H)
t
(L)
su
th(H)
t
(L)
h
tsu(H)
t
(L)
su
th(H)
t
(L)
h
tsu(H)
t
(L)
su
th(H)
t
(L)
h
tw(H)
t
(L)
w
tw(H)
t
(L)
w
Setup time, High or Low
Dn to CP
Hold time, High or Low
Dn to CP
Setup time, High or Low
PE
or SR to CP
Hold time, High or Low
PE
or SR to CP
Setup time, High or Low
CET or CEP to CP
Hold time, High or Low
CET or CEP to CP
CP Pulse width (load),
High or Low
CP Pulse width (count),
High or Low
Waveform 6
Waveform 6
Waveform 5 or 6
Waveform 6
Waveform 4
Waveform 4
Waveform 1
Waveform 1
tw(L) MR or SR Pulse width, Low Waveform 3 5.0 ns
t
REC
Recovery time, CR or SR to CP Waveform 3 10.0 ns
= +5.0V ± 10%
CC
C
= 50pF, RL = 500Ω
L
MIN MAX
8.0
8.0
0.0
0.0
10.0
10.0
0.0
0.0
10.0
10.0
0.0
0.0
5.0
5.0
5.0
5.0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
1991 Feb 08
8
Page 9
Philips Semiconductors Product specification
74ALS161B/74ALS163B4-bit binary counter
AC WAVEFORMS
For all waveforms, VM = 1.3V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
MAX
CP
Qn, TC
V
t
M
tw(H)
PLH
V
M
tw(L)
V
M
V
M
t
PHL
V
M
SC00088
Waveform 1. Propagation Delay for Clock Input to Output,
Clock PUlse Width, and Maximum Clock Frequency
tw(L)
MR
CP
Qn, TC
V
M
t
PHL
V
M
t
REC
V
M
V
M
SF00669
Waveform 3. Master Reset Pulse Width,
Master Reset to Output Delay,
and Master Reset to Clock Recovery Time
CET
TC
V
M
t
PLH
V
M
V
M
t
PHL
V
M
Waveform 2. Propagation Delay for CET to TC Output
CEP
CET
CP
V
MVM
V
V
M
M
tsu(H) tsu(L)th(H) th(L)
V
M
V
M
SC00089
Waveform 4. CEP and CET Setup and Hold Times
SF00668
SR
V
M
M
V
V
M
M
V
tsu(L) tsu(H)th(L) th(H)
CP
V
M
Waveform 5. Synchronous Reset Setup and Hold Times
1991 Feb 08
V
M
SC00090
V
V
M
M
t
t
su
h
V
M
V
V
M
M
PE
Dn
V
M
tsu(L) tsu(H)th(L) th(H)
CP
V
M
Waveform 6. Data and Parallel Enable Setup and Hold Times
9
V
M
SC00091
Page 10
Philips Semiconductors Product specification
74ALS161B/74ALS163B4-bit binary counter
TEST CIRCUIT AND WAVEFORMS
V
CC
PULSE
GENERATOR
V
IN
R
T
D.U.T.
V
OUT
C
R
L
L
Test Circuit for Totem-pole Outputs
DEFINITIONS:
R
= Load resistor;
L
see AC electrical characteristics for value.
CL= Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
OUT
of
NEGATIVE
PULSE
POSITIVE
PULSE
90%
10%
Family
74ALS
V
M
10%
t
THL (tf
t
TLH (tr
90%
V
M
Input Pulse Definition
Amplitude
3.5V
t
w
10%
)
f
)
t
)
TLH (tr
t
)
THL (tf
90%
t
w
90%
V
M
V
M
10%
INPUT PULSE REQUIREMENTS
V
M
1.3V
Rep.Rate
1MHz
500ns
t
w
t
TLHtTHL
2.0ns 2.0ns
AMP (V)
0.3V
AMP (V)
0.3V
SC00005
1991 Feb 08
10
Page 11
Philips Semiconductors Product specification
4-bit binary counter
74ALS161B
74ALS163B
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
1991 Feb 08
11
Page 12
Philips Semiconductors Product specification
4-bit binary counter
74ALS161B
74ALS163B
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
1991 Feb 08
12
Page 13
Philips Semiconductors Product specification
4-bit binary counter
74ALS161B
74ALS163B
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
1991 Feb 08
13
Page 14
Philips Semiconductors Product specification
4-bit binary counter
74ALS161B
74ALS163B
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
1991 Feb 08
14
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