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74als112a
DATASHEETS (Philips)
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Datasheet 74als112a DATASHEETS (Philips)

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Page 1
INTEGRATED CIRCUITS
74ALS112A
Dual J-K negative edge-triggered flip-flop
Product specification 1996 June 27 IC05 Data Handbook
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Page 2
Philips Semiconductors Product specification

DESCRIPTION

PIN CONFIGURATION

The 74ALS112A, dual negative edge-triggered JK-type flip-flop features individual J, K, clock (CP inputs, true (Qn) and complementary (Q
D and RD inputs, when Low, set or reset the outputs as shown
The S in the function table regardless of the level at the other inputs.
A High level on the clock (CP data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP according to the function table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CP
n.
TYPE
74ALS112A 50MHz 3.0mA
n), set (SD), and reset (RD)
n) outputs.
n) input enables the J and K inputs and
n is High and the flip-flop will perform
TYPICAL
f
MAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
1
CP0
2
K0
J0
3
S
4
D0
5
Q0
6
0
Q
1
Q

ORDERING INFORMA TION

ORDER CODE
16 15 14 13 12 11 107
98GND Q1
V R R
CP K1 J1 SD1
CC
D0 D1
1
DESCRIPTION COMMERCIAL RANGE
V
= 5V ±10%,
CC
T
= 0°C to +70°C
amb
16-pin plastic DIP 74ALS1 12AN SOT38-4
16-pin plastic SO 74ALS1 12AD SOT109-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION
74ALS (U.L.)
HIGH/LOW
CP0, CP1 Clock Pulse input (active falling edge) 1.0/1.0 20µA/0.1mA
J0, J1 J inputs 1.0/2.0 20µA/0.2mA
K0, K1 K inputs 1.0/2.0 20µA/0.2mA SD0, SD1 Set inputs (active-Low) 1.0/2.0 20µA/0.2mA RD0, RD1 Reset inputs (active-Low) 1.0/2.0 20µA/0.2mA
Q0, Q1, Q0, Q1 Data outputs 20/80 0.4mA/8mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOAD VALUE
HIGH/LOW
SF00103
DRAWING
NUMBER

LOGIC SYMBOL

212
311
J1 K0
CP0 SD0 RD0 CP1 SD1 RD1
Q0 Q0 Q1 Q1
56 97
VCC = Pin 16 GND = Pin 8
1
4 15 13 10 14
1996 Jun 27 853-1846 16995
K1J0
SF00104

IEC/IEEE SYMBOL

2
3 1
2
15
4
11 13
12 14 10
1J
C1
1K
R S
2J
C2
2K
R S
5
6
9
7
SF00105
Page 3
Philips Semiconductors Product specification
OPERATING MODE
74ALS112ADual J-K negative edge-triggered flip-flop

LOGIC DIAGRAM

5, 9
Qn
4, 10
S
Dn
2, 12
Kn
VCC = Pin 16 GND = Pin 8
CP
1, 13 n

FUNCTION TABLE

INPUTS OUTPUTS
SD RD CP J K Q Q
L H X X X H L Asynchronous Set
H L X X X L H Asynchronous Reset
L L X X X H* H* Undetermined * H H ↓ h h q q T oggle H H ↓ h l H L Load “1” (Set) H H ↓ l h L H Load “0” (Reset) H H ↓ l l q q Hold “no change” H H H X X q q Hold “no change”
H = High voltage level h = High state must be present one setup time prior to High-to-Low clock transition L = Low voltage level l = Low state must be present one setup time prior to High-to-Low clock transition q = Lower case indicate the state of the referenced output prior to the High-to-Low clock transition X = Don’t care ↓ = High-to-Low clock transition * = Both outputs will be High while both S Asynchronous inputs: Low input to S
Simultaneous Low on both S
D and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously
D sets Q to High level, Low input to RD sets Q to Low level. Set and reset are independent of clock.
D and RD makes both Q and Q High.
6, 7
15, 14
3, 11
n
Q
R
Dn
Jn
SF00106
1996 Jun 27
3
Page 4
Philips Semiconductors Product specification
SYMBOL
PARAMETER
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
1
UNIT
VOLLow-level output voltage
3
74ALS112ADual J-K negative edge-triggered flip-flop

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
V
I
T
V
I
OUT
OUT
amb
T
Supply voltage
CC
Input voltage –0.5 to +7.0 V
IN
Input current –30 to +5 mA
IN
Voltage applied to output in High output state –0.5 to V Current applied to output in Low output state 16 mA Operating free-air temperature range 0 to +70 °C Storage temperature range –65 to +150 °C
stg

RECOMMENDED OPERATING CONDITIONS

T
V
V V
I
I
OH
I
OL
amb
Supply voltage 4.5 5.0 5.5 V
CC
High-level input voltage 2.0 V
IH
Low-level input voltage 0.8 V
IL
Input clamp current –18 mA
Ik
High-level output current –0.4 mA Low-level output current 8 mA Operating free-air temperature range 0 +70 °C
PARAMETER RATING UNIT
–0.5 to +7.0 V
CC
V
LIMITS
MIN NOM MAX

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
MIN TYP2MAX
V
OH
High-level output voltage
p
V
I
I
IH
Input clamp voltage VCC = MIN, II = I
IK
Input current at maximum input voltage VCC = MAX, VI = 7.0V 0.1 mA
I
High-level input current VCC = MAX, VI = 2.7V 20 µA
VCC = ±10%, V
= MAX, VIH = MIN
IL
IOH = –0.4mA V
VCC = MIN, VIL = MAX, I VIH = MIN I
IK
= 4mA 0.25 0.40 V
OL
= 8mA 0.35 0.50 V
OL
CPn –0.1 mA
I
IL
Low-level input current
SDn, RDn,
VCC = MAX, VI = 0.4V
Jn, Kn
I
O
I
CC
Output current
VCC = MAX, VO = 2.25V –30 –112 mA
Supply current (total) VCC = MAX 2.5 4.5 mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
3. The output conditions have been chosen to produce a current that closely approximates one half of the true short–circuit output current, I
= 5V, T
CC
amb
= 25°C.
– 2 V
CC
–0.73 –1.5 V
–0.2 mA
OS
.
1996 Jun 27
4
Page 5
Philips Semiconductors Product specification
74ALS112ADual J-K negative edge-triggered flip-flop

AC ELECTRICAL CHARACTERISTICS

LIMITS
T
= 0°C to +70°C
amb
V
SYMBOL PARAMETER TEST CONDITION
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
Maximum clock frequency Waveform 1 35 MHz Propagation delay
CP
n to Qn or Qn
Propagation delay S
Dn or RD to Qn or Qn
Waveform 1
Waveform 2, 3

AC SETUP REQUIREMENTS

SYMBOL PARAMETER TEST CONDITION
t
(H)
t
t
t
t t
su
su
h
t
h
w
w
w
t
(H)
(L)
REC
Setup time, High or Low Jn, Kn to CP
(L)
Hold time, High or Low Jn, Kn to CP
(H)
CPn Pulse width high or Low
(L)
SDn or RDn Pulse width
(L)
Low Recovery time,
S
Dn or RDn to CPn
n
n
Waveform 1
Waveform 1
Waveform 1
Waveform 2, 3 6.0 ns
Waveform 2, 3 8.0 ns
= +5.0V ± 10%
CC
C
= 50pF, RL = 500Ω
L
MIN MAX
2.0
4.0
1.5
3.5
10.0
10.5
8.0
9.5
LIMITS
T
= 0°C to +70°C
amb
V
= +5.0V ± 10%
CC
C
= 50pF, RL = 500Ω
L
MIN MAX
8.0
8.0
0.0
0.0
11.0
8.0
UNIT
ns
ns
UNIT
ns
ns
ns
1996 Jun 27
5
Page 6
Philips Semiconductors Product specification
74ALS112ADual J-K negative edge-triggered flip-flop

AC WAVEFORMS

For all waveforms, VM = 1.3V. The sahded areas indicate when the input is permitted to change for predictable output performance.
Jn, Kn
tsu(L) th(L)
CPn
Qn
Qn
V
V
M
M
1/f
max
V
M
V
M
V
M
t
PLH
t
PHL
tw(L)
V
M
V
M
tsu(H) th(H)
t
(H)
w
V
M
V
M
t
PHL
V
M
t
PLH
V
M
Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, Clock Pulse Width, and Maximum Clock Frequency
Jn, Kn
SDn
CPn
Qn
Qn
t
PLH
t
PHL
tw(L)
V
M
t
REC
V
M
V
M
V
M
V
M
Jn, Kn
RDn
CPn
Qn
Qn
t
PHL
t
PLH
tw(L)
V
M
t
REC
V
M
V
M
V
M
V
M
SC00136
Waveform 2. Propagation Delay for Set to Output,
Set Pulse Width, and Recovery Time for Set to Clock
1996 Jun 27
SC00049
SC00050
Waveform 3. Propagation Delay for Reset to Output,
Reset Pulse Width, and Recovery Time for Reset to Clock
6
Page 7
Philips Semiconductors Product specification
74ALS112ADual J-K negative edge-triggered flip-flop

TEST CIRCUIT AND WAVEFORMS

V
CC
PULSE
GENERATOR
V
IN
R
T
D.U.T.
V
OUT
C
R
L
L
Test Circuit for Totem-pole Outputs
DEFINITIONS:
R
= Load resistor;
L
see AC electrical characteristics for value.
CL= Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
OUT
of
NEGATIVE PULSE
POSITIVE PULSE
90%
10%
Family
74ALS
V
M
10%
t
THL (tf
t
TLH (tr
90%
V
M
Input Pulse Definition
Amplitude
3.5V
t
w
V
10%
)
f
)
t
)
TLH (tr
t
)
THL (tf
90%
t
w
90%
M
V
M
10%
INPUT PULSE REQUIREMENTS
V
M
1.3V
Rep.Rate
1MHz
500ns
t
w
t
TLHtTHL
2.0ns 2.0ns
AMP (V)
0.3V
AMP (V)
0.3V
SC00005
1996 Jun 27
7
Page 8
Philips Semiconductors Product specification
74ALS112ADual J-K negative edge-triggered flip-flop

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

1996 Jun 27
8
Page 9
Philips Semiconductors Product specification
74ALS112ADual J-K negative edge-triggered flip-flop

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

1996 Jun 27
9
Page 10
Philips Semiconductors Product specification
74ALS112ADual J-K negative edge-triggered flip-flop

DEFINITIONS

Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
LIFE SUPPORT APPLICA TIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
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1996 Jun 27
10
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