Datasheet 74als109a DATASHEETS (Philips)

INTEGRATED CIRCUITS

74ALS109A

Dual J-K

positive edge-triggered flip-flop

with set and reset

Product specification 1991 Feb 08 IC05 Data Handbook

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Philips Semiconductors Product specification

Dual J-K

positive edge triggered flip-flop

with set and reset

DESCRIPTION

The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input. The J and K

are edge-triggered inputs which control the state changes of the flip-flops as described in the function table. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. The J and K be stable just one setup time prior to the Low-to-High transition of the clock for predictable operation. The JK as a D flip-flop by tying J and K input is level sensitive, the positive transition of the clock pulse between the 0.8V and 2.0V levels should be equal to or less than the clock to output delay time for reliable operation.

TYPE

74ALS109A 150MHz 3.0mA

ORDERING INFORMATION

DESCRIPTION COMMERCIAL RANGE

16-pin plastic DIP 74ALS109AN SOT38-4

16-pin plastic SO 74ALS109AD SOT109-1

, clock, set, and reset inputs; also true and

inputs must

design allows operation

inputs together. Although the clock

TYPICAL

f

MAX

TYPICAL

SUPPLY CURRENT

(TOTAL)

ORDER CODE

DRAWING

V

= 5V ±10%,

CC

T

= 0°C to +70°C

amb

NUMBER

PIN CONFIGURATION

R

1

D0

2

J0

K

3

0

4

CP0

5

S

D0

6

0

Q

0

Q

74ALS109A

16

V

CC

D1

15

R J1

14 13

1

K

12

CP1

11

SD1

107

Q1

98GND Q1

SF00135

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION

74ALS (U.L.)

HIGH/LOW

J0, J1 J inputs 1.0/2.0 20µA/0.2mA

K0, K1 K inputs 1.0/2.0 20µA/0.2mA CP0, CP1 Clock inputs (active rising edge) 1.0/2.0 20µA/0.2mA SD0, SD1 Set inputs (active-Low) 1.0/4.0 20µA/0.4mA RD0, RD1 Reset inputs (active-Low) 1.0/4.0 20µA/0.4mA

Q0, Q1, Q0, Q1 Data outputs 20/80 0.4mA/8mA

NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.

LOGIC SYMBOL

4 5 1

12

11

15

VCC = Pin 16 GND = Pin 8

CP0 SD0 RD0 CP1 SD1 RD1

2 14 3 13

J1

K0

J0

Q0 Q0 Q1 Q1

6 7 10 9

K1

SF00136

IEC/IEEE SYMBOL

2 4

3 1 5

14 12

13 15 11

1J

C1

1K

R S

2J

C2

2K

R S

LOAD VALUE

HIGH/LOW

6

7

10

9

SF00137

1991 Feb 08 853–1275 01670

2

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

Dual J-K

positive edge triggered flip-flop

with set and reset

LOGIC DIAGRAM

5, 11

SD

1, 15

R

D

4, 12

CP

2, 14

J

3, 13

K

V

= Pin 16

CC

GND = Pin 8

6, 10

7, 9

SC00042

74ALS109A

FUNCTION TABLE

INPUTS OUTPUTS

SD RD CP J K Q Q

L H X X X H L Asynchronous set

Q

H L X X X L H Asynchronous reset

L L X X X H* H* Undetermined*

H H ↑ h l q q Toggle

Q

H H ↑ l l L H Load “0” H H ↑ h h H L Load “1” H H ↑ l h q q Hold “no change” H H L l h q q Hold “no change”

H = High voltage level h = High state must be present one setup time prior to

Low-to-High clock transition L = Low voltage level l = Low state must be present one setup time prior to

Low-to-High clock transition q = Lower case indicate the state of the referenced output prior to

the Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition * = The output levels in this configuration are not guaranteed to

meet the minimum levels for V

maximum. Furthermore, this configuration is nonstable;

V

IN

that is, it will not remain when either set or reset returns to its

if the set and reset are near

OH

inactive (High) level.

OPERATING

MODE

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)

SYMBOL

V

CC

V

IN

I

IN

V

OUT

I

OUT

T

amb

T

stg

Supply voltage Input voltage –0.5 to +7.0 V

Input current Voltage applied to output in high output state –0.5 to V

Current applied to output in Low output state 16 mA Operating free-air temperature range 0 to +70 °C Storage temperature range –65 to +150 °C

PARAMETER RATING UNIT

RECOMMENDED OPERATING CONDITIONS

V

T

V V

I

OH

I

OL

amb

CC

Ik

Supply voltage 4.5 5.0 5.5 V High-level input voltage 2.0 V

IH

Low-level input voltage 0.8 V

IL

Input clamp current –18 mA High-level output current –0.4 mA Low-level output current 8 mA Operating free-air temperature range 0 +70 °C

–0.5 to +7.0 V

–30 to +5 mA

CC

LIMITS

MIN NOM MAX

V

1991 Feb 08

3

Philips Semiconductors Product specification

SYMBOL

PARAMETER

TEST CONDITIONS

1

UNIT

VOLLow-level output voltage

CC

,

IL

,

I

V

MAX, V

0V

IIHHigh–level input current

V

MAX, V

7V

IILLow–level input current

V

MAX, V

4V

Dual J-K with set and reset

positive edge triggered flip-flop

74ALS109A

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

LIMITS

MIN TYP2MAX

V

High-level output voltage

OH

p

V

I

CC

Input clamp voltage VCC = MIN, II = I

IK

Input current at maximum input

I

voltage

p

Output current

O

Supply current (total)

p

3

4

Jn, Kn, CPn

SDn, RDn

Jn, Kn, CPn

SDn, RDn

Jn, Kn, CPn

SDn, RDn

VCC = ±10%, V

= MAX, VIH = MIN

IL

VCC = MIN, VIL = MAX, VIH = MIN

IK

CC

=

= 7.

I

= 2.

I

= 0.

I

IOH = –0.4mA V

I

= 4mA 0.25 0.40 V

OL

I

= 8mA 0.35 0.50 V

OL

VCC = MAX, VO = 2.25V –30 –112 mA VCC = MAX 3.0 4.0 mA

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

3. The output conditions have been chosen to produce a current that closely approximates one half of the true short–circuit output current, I

4. Measure I

with the clock input grounded and all outputs open, then with Q and Q outputs High in turn.

CC

= 5V, T

CC

amb

= 25°C.

– 2 V

CC

–0.73 –1.5 V

0.1 mA

0.2 mA 20 µA 40 µA

–0.2 mA –0.4 mA

OS

.

AC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER TEST CONDITION

f

MAX

t

PLH

t

PHL

t

PLH

t

PHL

Maximum clock frequency Waveform 1 80 MHz Propagation delay

CPn to Qn or Q

n

Propagation delay S

Dn or RD to Qn or Qn

Waveform 1

Waveform 2, 3

AC SETUP REQUIREMENTS

SYMBOL PARAMETER TEST CONDITION

t

(H)

su

t

su

t

h

t

(L)

h

t

w

t

w

t

w

t

rec

Setup time, High or Low Jn, K

(L)

(H)

Hold time, High or Low Jn, K

(H)

CPn Pulse width High or Low

(L)

SDn or RDn Pulse width

(L)

Low

n to CPn

Waveform 1

Waveform 2, 3 6.0 ns

Recovery time, SDn or RDn to CPn Waveform 2, 3 6.0 ns

LIMITS

T

= 0°C to +70°C

amb

V

= +5.0V ± 10%

CC

C

= 50pF, RL = 500Ω

L

MIN MAX

3.0

1.0

3.0

14.0

8.0

10.0

LIMITS

T

= 0°C to +70°C

amb

V

= +5.0V ± 10%

CC

C

= 50pF, RL = 500Ω

L

MIN MAX

6.0

0.0

6.0

UNIT

ns

UNIT

ns

1991 Feb 08

4

Philips Semiconductors Product specification

Dual J-K

positive edge triggered flip-flop

with set and reset

AC WAVEFORMS

For all waveforms, VM = 1.3V. The shaded areas indicate when the input is permitted to change for predictable output performance.

Jn,

n

K

CPn

Qn

Waveform 1. Propagation Delay for Data to Output,

Data Setup Time and Hold Times, Clock Width,

V

M

tsu(L) th(L)

1/f

max

V

M

t

PLH

PHL

tw(H)

V

M

V

M

V

M

and Maximum Clock Frequency

V

tsu(H) th(H)

t

(L)

w

V

M

V

M

t

PHL

V

M

t

PLH

V

M

SC00043

74ALS109A

Jn, Kn

t

PLH

t

PHL

tw(L)

V

M

t

REC

V

M

V

M

V

M

SDn

CPn

Qn

V

M

Waveform 2. Propagation Delay for Set to Output,

Set Pulse Width and Recovery Time for Set to Clock

SC00044

Jn, Kn

t

PLH

t

PHL

tw(L)

V

M

t

REC

V

M

V

M

V

M

SC00045

RDn

CPn

Qn

V

M

Waveform 3. Propagation Delay for Reset to Output,

Reset Pulse Width and Recovery Time for Reset to Clock

1991 Feb 08

5

Philips Semiconductors Product specification

Dual J-K

positive edge triggered flip-flop

with set and reset

TEST CIRCUIT AND WAVEFORMS

V

CC

V

PULSE

GENERATOR

IN

R

T

Test Circuit for Totem-pole Outputs

DEFINITIONS:

R

= Load resistor;

L

see AC electrical characteristics for value.

CL= Load capacitance includes jig and probe capacitance;

see AC electrical characteristics for value.

R

= Termination resistance should be equal to Z

T

pulse generators.

D.U.T.

V

OUT

C

R

L

OUT

of

NEGATIVE PULSE

POSITIVE PULSE

90%

10%

Family

74ALS

V

M

10%

t

THL (tf

t

TLH (tr

90%

V

M

Input Pulse Definition

Amplitude

3.5V

74ALS109A

t

w

10%

)

f

)

t

)

TLH (tr

t

)

THL (tf

90%

t

w

INPUT PULSE REQUIREMENTS

V

Rep.Rate

M

1.3V

1MHz

500ns

V

M

V

M

t

w

90%

10%

t

TLHtTHL

2.0ns 2.0ns

AMP (V)

0.3V

AMP (V)

0.3V

SC00005

1991 Feb 08

6

Philips Semiconductors Product specification

Dual J-K positive edge-triggered flip-flop with set and reset

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

74ALS109A

1991 Feb 08

7

Philips Semiconductors Product specification

Dual J-K positive edge-triggered flip-flop with set and reset

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

74ALS109A

1991 Feb 08

8

Philips Semiconductors Product specification

Dual J-K positive edge-triggered flip-flop with set and reset

DEFINITIONS

74ALS109A

Data Sheet Identification Product Status Definition

Objective Specification

Preliminary Specification

Product Specification

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

LIFE SUPPORT APPLICA TIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected

to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

Formative or in Design

Preproduction Product

Full Production

This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.

 Copyright Philips Electronics North America Corporation 1997

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1991 Feb 08

9