Datasheet 74AHCT1G86, 74AHC1G86 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

74AHC1G86; 74AHCT1G86

2-input EXCLUSIVE-OR gate

Product specification
File under Integrated Circuits, IC06

1999 Sep 20

Philips Semiconductors Product specification

2-input EXCLUSIVE-OR gate 74AHC1G86; 74AHCT1G86

FEATURES

• Symmetrical output impedance

• High noise immunity

• ESD protection:

HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V

• Low power dissipation

• Balanced propagation delays

• Very small 5-pin package

• Output capability: standard.

DESCRIPTION

The 74AHC1G/AHCT1G86 is a
high-speed Si-gate CMOS device.

The 74AHC1G/AHCT1G86 provides
the 2-input EXCLUSIVE-OR function.

FUNCTION TABLE

See note 1.

QUICK REFERENCE DATA

Ground = 0 V; T

=25°C; tr=tf≤3.0 ns.

amb

SYMBOL PARAMETER CONDITIONS

t

PHL/tPLH

C

I

C

PD

propagation delay
inA, inB to outY

input capacitance 1.5 1.5 pF
power dissipation

capacitance

CL=15pF;
VCC=5V

CL=50pF;
f = 1 MHz;
notes 1 and 2

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW).

PD

P

D=CPD

× V

2

× fi+(CL×V

CC

2

× fo) where:

CC

fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC= supply voltage in Volts.

2. The condition is VI= GND to VCC.

TYPICAL

UNIT

AHC1G AHCT1G

3.4 3.5 ns

911pF

INPUTS OUTPUT

inA inB outY

LLL

LHH
HLH
HHL

Note

1. H = HIGH voltage level;
L = LOW voltage level.

ORDERING INFORMATION

PACKAGES

TYPE NUMBER

TEMPERATURE

RANGE

PINS PACKAGE MATERIAL CODE MARKING

74AHC1G86GW −40 to +85 °C 5 SC-88A plastic SOT353 AH
74AHCT1G86GW 5 SC-88A plastic SOT353 CH

1999 Sep 20 2

Philips Semiconductors Product specification

2-input EXCLUSIVE-OR gate 74AHC1G86; 74AHCT1G86

PINNING

PIN SYMBOL DESCRIPTION

1 inA data input
2 inB data input
3 GND ground (0 V)
4 outY data output
5V

CC

DC supply voltage

handbook, halfpage

handbook, halfpage

inA
inB

GND

1
2

86

3

MNA037

V

5

outY

4

Fig.1 Pin configuration.

1
2

= 1

MNA039

CC

4

handbook, halfpage

handbook, halfpage

inA

inB

inA

1

inB

2

outY

MNA038

Fig.2 Logic symbol.

4

outY

MNA040

Fig.3 IEC logic symbol.

1999 Sep 20 3

Fig.4 Logic diagram.

Philips Semiconductors Product specification

2-input EXCLUSIVE-OR gate 74AHC1G86; 74AHCT1G86

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS

UNIT

MIN. TYP. MAX. MIN. TYP. MAX.

74AHC1G 74AHCT1G

V

CC

V

I

V

O

T

amb

DC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
input voltage 0 − 5.5 0 − 5.5 V
output voltage 0 − V
operating ambient

temperature

see DC and AC
characteristics per

−40 +25 +85 −40 +25 +85 °C

0 − V

CC

CC

V

device

t

(∆t/∆f) input rise and fall times

r,tf

except for
Schmitt trigger inputs

VCC= 3.3 ±0.3 V −−100 −−−ns/V

=5±0.5 V −−20 −−20

V

CC

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground=0V).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

V

I

I

IK

I

OK

I

O

I

CC

T

stg

P

D

DC supply voltage −0.5 +7.0 V
input voltage −0.5 +7.0 V
DC input diode current VI< −0.5 −−20 mA
DC output diode current VO< −0.5 or VO>VCC+ 0.5 V; note 1 −±20 mA
DC output source or sink current −0.5V<VO<VCC+ 0.5 V −±25 mA
DC VCC or GND current −±75 mA
storage temperature −65 +150 °C
power dissipation per package temperature range: −40 to +85 °C; note 2 − 200 mW

Notes

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. Above 55 °C the value of PD derates linearly with 2.5 mW/K.

1999 Sep 20 4

Philips Semiconductors Product specification

2-input EXCLUSIVE-OR gate 74AHC1G86; 74AHCT1G86

DC CHARACTERISTICS
Family 74AHC1G

Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).

SYMBOL PARAMETER

V

IH

V

IL

V

OH

HIGH-levelinputvoltage 2.0 1.5 −−1.5 − V

LOW-level input voltage 2.0 −− 0.5 − 0.5 V

HIGH-level output
voltage; all outputs

HIGH-level output
voltage

V

OL

LOW-level output
voltage; all outputs

LOW-level output
voltage

I

I

I

CC

input leakage current VI=VCCor GND 5.5 −− 0.1 − 1.0 µA
quiescent supply

current

C

I

input capacitance − 1.5 10 − 10 pF

TEST CONDITIONS T

OTHER VCC (V)

MIN. TYP. MAX. MIN. MAX.

3.0 2.1 −−2.1 −

5.5 3.85 −−3.85 −

3.0 −− 0.9 − 0.9

5.5 −− 1.65 − 1.65

VI=VIHor VIL;
IO= −50 µA

2.0 1.9 2.0 − 1.9 − V

3.0 2.9 3.0 − 2.9 −

4.5 4.4 4.5 − 4.4 −

V

I=VIH

or VIL;

3.0 2.58 −−2.48 − V

IO= −4.0 mA
V

I=VIH

or VIL;

4.5 3.94 −−3.8 −

IO= −8.0 mA
VI=VIHor VIL;

IO=50µA

2.0 − 0 0.1 − 0.1 V

3.0 − 0 0.1 − 0.1

4.5 − 0 0.1 − 0.1

V

I=VIH

or VIL;

3.0 −− 0.36 − 0.44 V

IO= 4.0 mA
V

I=VIH

or VIL;

4.5 −− 0.36 − 0.44

IO= 8.0 mA

VI=VCCor GND;

5.5 −− 1.0 − 10 µA

IO=0

(°C)

amb

25 −40 to +85

UNIT

1999 Sep 20 5

Philips Semiconductors Product specification

2-input EXCLUSIVE-OR gate 74AHC1G86; 74AHCT1G86

Family 74AHCT1G

Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).

SYMBOL PARAMETER

V

IH

V

IL

V

OH

HIGH-level input voltage 4.5 to 5.5 2.0 −−2.0 − V
LOW-level input voltage 4.5 to 5.5 −−0.8 − 0.8 V
HIGH-level output

voltage; all outputs
HIGH-level output

voltage

V

OL

LOW-level output
voltage; all outputs

LOW-level output voltage V

I
I

∆I

I
CC

CC

input leakage current VI=VIHor V
quiescent supply current VI=VCCor GND;

additional quiescent
supply current per input
pin

C

I

input capacitance − 1.5 10 − 10 pF

TEST CONDITIONS T

OTHER VCC (V)

MIN. TYP. MAX. MIN. MAX.

VI=VIHor VIL;

4.5 4.4 4.5 − 4.4 − V

IO= −50 µA
V

I=VIH

or VIL;

4.5 3.94 −−3.8 − V

IO= −8.0 mA
VI=VIHor VIL;

4.5 − 0 0.1 − 0.1 V

IO=50µA

I=VIH

or VIL;

4.5 −−0.36 − 0.44 V

IO= 8.0 mA

IL

5.5 −−0.1 − 1.0 µA

5.5 −−1.0 − 10 µA

IO=0
VI= 3.4 V;

5.5 −−1.35 − 1.5 mA
other inputs at
VCCor GND; IO=0

(°C)

amb

25 −40 to +85

UNIT

1999 Sep 20 6

Philips Semiconductors Product specification

2-input EXCLUSIVE-OR gate 74AHC1G86; 74AHCT1G86

AC CHARACTERISTICS
Type 74AHC1G86

Ground = 0 V; tr=tf≤3.0 ns.

SYMBOL PARAMETER

VCC= 3.0 to 3.6 V; note 1

t

PHL/tPLH

propagation delay
inA, inB to outY

V

= 4.5 to 5.5 V; note 2

CC

t

PHL/tPLH

propagation delay
inA, inB to outY

Notes

1. Typical values at V

CC

= 3.3 V.

2. Typical values at VCC= 5.0 V.

74AHCT1G86

Ground = 0 V; tr=tf≤3.0 ns.

SYMBOL PARAMETER

TEST CONDITIONS T

amb

(°C)

25 −40 to +85

WAVEFORMS C

L

MIN. TYP. MAX. MIN. MAX.

see Figs 5 and 6 15 pF − 4.0 11.0 1.0 13 ns

50 pF − 5.8 14.5 1.0 16.5 ns

see Figs 5 and 6 15 pF − 3.4 6.8 1.0 8.0 ns

50 pF − 4.9 8.8 1.0 10.0 ns

TEST CONDITIONS T

amb

(°C)

25 −40 to +85

WAVEFORMS C

L

MIN. TYP. MAX. MIN. MAX.

UNIT

UNIT

VCC= 4.5 to 5.5 V; note 1

t

PHL/tPLH

propagation delay
inA, inB to outY

Note

1. Typical values at V

CC

see Figs 5 and 6 15 pF − 3.5 6.9 1.0 8.0 ns

50 pF − 5.0 7.9 1.0 9.0 ns

= 5.0 V.

1999 Sep 20 7

Philips Semiconductors Product specification

2-input EXCLUSIVE-OR gate 74AHC1G86; 74AHCT1G86

AC WAVEFORMS

handbook, halfpage

inA, inB input

V

M

outY output

FAMILY

VI INPUT

REQUIREMENTS

AHC1G GND to V

CC

V

M

INPUT

V

M

OUTPUT

50% VCC50% V

AHCT1G GND to 3.0 V 1.5 V 50% V

Fig.5 The input (inA, inB) to output (outY) propagation delays.

handbook, halfpage

PULSE

GENERATOR

V

t

PHL

V

M

CC
CC

V

CC

I

D.U.T.

R

T

V

O

t

PLH

MNA041

C

50 pF

L

MNA034

Definitions for test circuit:
CL= load capacitance including jig and probe capacitance

(see “AC characteristics” for values).

= termination resistance should be equal to the output

R

T

impedance Z

of the pulse generator.

o

Fig.6 Load circuitry for switching times.

1999 Sep 20 8

Philips Semiconductors Product specification

2-input EXCLUSIVE-OR gate 74AHC1G86; 74AHCT1G86

PACKAGE OUTLINE

Plastic surface mounted package; 5 leads SOT353

D

y

45

132

e

1

e

b

p

wBM

A

A

1

E

H

E

detail X

Q

L

p

AB

X

v M

A

c

0 1 2 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

mm

A

1.1

0.8

OUTLINE
VERSION

SOT353

max

0.1

1

b

cD

p

0.30

0.20

IEC JEDEC EIAJ

0.25

0.10

2.2

1.8

(2)

E

1.35

1.3

1.15

REFERENCES

e

e

1

0.65

1999 Sep 20 9

H

2.2

2.0

L

Qywv

p

E

0.45

0.15

0.25

0.15

0.2 0.10.2

EUROPEAN

PROJECTION

ISSUE DATE

97-02-28SC-88A

Philips Semiconductors Product specification

2-input EXCLUSIVE-OR gate 74AHC1G86; 74AHCT1G86

SOLDERING
Introduction to soldering surface mount packages

Thistextgivesaverybriefinsighttoa complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
totheprinted-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswithleadsonfoursides,thefootprintmust
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Sep 20 10

Philips Semiconductors Product specification

2-input EXCLUSIVE-OR gate 74AHC1G86; 74AHCT1G86

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, SQFP not suitable suitable

SOLDERING METHOD

HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Sep 20 11

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1999

Internet: http://www.semiconductors.philips.com

68

Printed in The Netherlands 245002/01/pp12 Date of release: 1999 Sep 20 Document order number: 9397 750 06111