Datasheet 74AHCT1G07, 74AHC1G07 Datasheet (Philips)

Page 1
INTEGRATED CIRCUITS
DATA SH EET
74AHC1G07; 74AHCT1G07
Buffer with open-drain output
Product specification File under Integrated Circuits, IC06
2000 May 02
Page 2
Buffer with open-drain output
FEATURES
High noise immunity
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V
Low power dissipation
SOT353 package
Output capability standard (open drain).
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf≤3.0 ns.
amb
SYMBOL PARAMETER CONDITIONS
t
PZL
t
PLZ
C C
I PD
propagation delay inA to outY CL= 15 pF; VCC= 5 V 2.5 2.8 ns propagation delay inA to outY CL= 15 pF; VCC= 5 V 4.2 3.9 ns input capacitance 1.5 1.5 pF power dissipation capacitance CL= 50 pF; f = 1 MHz;
notes 1 and 2
DESCRIPTION
The74AHC1G/AHCT1G07isahigh-speedSi-gateCMOS device.
The 74AHC1G/AHCT1G07 provides the non-inverting buffer.
The output of the 74AHC1G/AHCT1G07 devices is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. For digital operation this device must have a pull-up resistor to establish a logic HIGH-level.
74AHC1G07;
74AHCT1G07
TYPICAL
UNIT
AHC1G AHCT1G
5.0 6.5 pF
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
PD=CPD× V
= input frequency in MHz;
f
i
2
× fi+(CL×V
CC
CC
fo= output frequency in MHz; CL= output load capacitance in pF; VCC= supply voltage in Volts.
2. The condition is VI= GND to VCC.
FUNCTION TABLE
See note 1.
INPUT OUTPUT
inA outY
HZ
Note
1. H = HIGH voltage level; L = LOW voltage level; Z = high impedance OFF-state.
2
× fo) where:
2000 May 02 2
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Buffer with open-drain output
74AHC1G07;
74AHCT1G07
ORDERING AND PACKAGE INFORMATION
PACKAGES
TYPE NUMBER
74AHC1G07GW 40 to +125 °C 5 SC-88A plastic SOT353 AS 74AHCT1G07GW 5 SC-88A plastic SOT353 CS
PINNING
SYMBOL PIN DESCRIPTION
n.c. 1 not connected inA 2 data input GND 3 ground (0 V) outY 4 data output V
CC
TEMPERATURE
RANGE
5 DC supply voltage
PINS PACKAGE MATERIAL CODE MARKING
handbook, halfpage
n.c.
inA
GND
1 2
07
3
MNA588
V
5
outY
4
Fig.1 Pin configuration.
CC
handbook, halfpage
inA outY
2
MNA589
Fig.2 Logic symbol.
4
2000 May 02 3
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Buffer with open-drain output
handbook, halfpage
2
inA
MNA590
Fig.3 IEC logic symbol.
4
outY
handbook, halfpage
74AHC1G07;
74AHCT1G07
outY
inA
GND
Fig.4 Logic diagram.
MNA591
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS
V
CC
V
I
V
O
DC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V input voltage 0 5.5 0 5.5 V output voltage active mode 0 V
high-impedance mode 0 6.0 0 6.0 V
T
amb
operating ambient temperature
see DC and AC characteristics per device
t
, t
r
f
(t/f)
input rise and fall times ratios (except for Schmitt-trigger inputs)
VCC= 3.3 ±0.3 V −−100 −−−ns/V V
=5±0.5 V −−20 −−20 ns/V
CC
74AHC 74AHCT
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
0 V
CC
CC
V
40 +25 +85 40 +25 +85 °C
40 +25 +125 40 +25 +125 °C
2000 May 02 4
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Buffer with open-drain output
74AHC1G07;
74AHCT1G07
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CC
V
I
I
IK
I
OK
V
O
I
O
I
CC
T
stg
P
D
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 55 °C the value of P
DC supply voltage 0.5 +7.0 V input voltage 0.5 +7.0 V DC input diode current VI< 0.5 V; note 1 −−20 mA DC output clamping diode
VO< 0.5 V; note 1 −±20 mA
current output voltage active mode; note 1 0.5 VCC+ 0.5 V
high-impedance mode; note 1 0.5 7.0 V DC output sink current VO> 0.5 V −±25 mA DC VCC or GND current −±75 mA storage temperature 65 +150 °C power dissipation per package for temperature range:
200 mW
40 to +125 °C; note 2
derates linearly with 2.5 mW/K.
D
2000 May 02 5
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Buffer with open-drain output
DC CHARACTERISTICS 74AHC1G family
Over recommended operating conditions; voltages are referenced to GND (ground=0V).
amb
(°C)
SYMBOL PARAMETER
V
IH
HIGH-level input voltage
V
IL
LOW-level input voltage
V
OL
LOW-level output voltage
I
I
input leakage current
I
OZ
3-state output OFF-state current
I
CC
quiescent supply current
C
I
input capacitance −−1.5 10 10 10 pF
TEST CONDITIONS T
25 40 to +85 40 to +125
OTHER VCC(V)
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
2.0 1.5 −−1.5 1.5 V
3.0 2.1 −−2.1 2.1 V
5.5 3.85 −−3.85 3.85 V
2.0 −−0.5 0.5 0.5 V
3.0 −−0.9 0.9 0.9 V
5.5 −−1.65 1.65 1.65 V
VI=VIHor VIL; IO=50µA
2.0 0 0.1 0.1 0.1 V
3.0 0 0.1 0.1 0.1 V
4.5 0 0.1 0.1 0.1 V
V
I=VIH
or VIL;
3.0 −−0.36 0.44 0.55 V
IO=4mA V
I=VIH
or VIL;
4.5 −−0.36 0.44 0.55 V
IO=8mA VI=VCCor GND 5.5 −−0.1 1.0 2.0 µA
VI=VIHor VIL;
5.5 −−±0.25 −±2.5 −±10.0 µA
VO=VCCor GND VI=VCCor GND;
5.5 −−1.0 10 20 µA
IO=0
74AHC1G07;
74AHCT1G07
UNIT
2000 May 02 6
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Buffer with open-drain output
74AHCT1G family
Over recommended operating conditions; voltages are referenced to GND (ground=0V).
SYMBOL PARAMETER
V
IH
HIGH-level input voltage
V
IL
LOW-level input voltage
V
OL
LOW-leveloutput voltage
I
I
input leakage current
I
OZ
3-state output OFF-state current
I
CC
quiescent supply current
I
CC
additional quiescent supply current per input pin
C
I
input capacitance
TEST CONDITIONS T
25 40 to +85 40 to +125
OTHER VCC(V)
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
4.5 to 5.5 2.0 −−2.0 2.0 V
4.5 to 5.5 −−0.8 0.8 0.8 V
VI=VIHor VIL;
4.5 0 0.1 0.1 0.1 V
IO=50µA V
I=VIH
or VIL;
4.5 −−0.36 0.44 0.55 V
IO=8mA VI=VCCor GND 5.5 −−0.1 1.0 2.0 µA
VI=VIHor VIL;
5.5 −−±0.25 −±2.5 −±10.0 µA
VO=VCCor GND
VI=VCCor GND;
5.5 −−1.0 10 20 µA
IO=0 VI= 3.4 V;
4.5 to 5.5 −−1.35 1.5 1.5 mA other inputs at VCCor GND; IO=0
−−1.5 10 10 10 pF
amb
(°C)
74AHC1G07;
74AHCT1G07
UNIT
2000 May 02 7
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Buffer with open-drain output
AC CHARACTERISTICS Type 74AHC1G07
GND = 0 V; tr=tf≤3.0 ns.
TEST CONDITIONS T
SYMBOL PARAMETER
VCC= 3.0 to 3.6 V; note 1
t t t t
PZL PLZ PZL PLZ
propagation delay inA to outY
propagation delay inA to outY
VCC= 4.5 to 5.5 V; note 2 t
t t t
PZL PLZ PZL PLZ
propagation delay inA to outY
propagation delay inA to outY
WAVEFORMS C
see Figs 5 and 6 15 pF 3.5 5.6 1.0 6.3 1.0 7.0 ns
see Figs 5 and 6 50 pF 5.0 8.0 1.0 9.0 1.0 10.0 ns
see Figs 5 and 6 15 pF 2.5 3.9 1.0 4.6 1.0 4.9 ns
see Figs 5 and 6 50 pF 3.6 5.5 1.0 6.5 1.0 7.0 ns
74AHC1G07;
74AHCT1G07
(°C)
amb
25 40 to +85 40 to +125
L
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
5.8 7.9 1.0 8.4 1.0 8.9 ns
8.3 11.5 1.0 12.0 1.0 12.5 ns
4.2 5.1 1.0 5.6 1.0 6.1 ns
6.0 7.5 1.0 8.0 1.0 8.5 ns
UNIT
Notes
1. Typical values at V
CC
= 3.3 V.
2. Typical values at VCC= 5.0 V.
Type 74AHCT1G07
GND = 0 V; tr=tf≤3.0 ns.
SYMBOL PARAMETER
VCC= 4.5 to 5.5 V; note 1
t t t t
PZL PLZ PZL PLZ
propagation delay inA to outY
propagation delay inA to outY
Note
1. Typical values at V
CC
= 5.0 V.
TEST CONDITIONS T
25 40 to +85 40 to +125
WAVEFORMS C
L
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
amb
(°C)
UNIT
see Figs 5 and 6 15 pF 2.8 4.6 1.0 5.3 1.0 5.6 ns
3.9 5.6 1.0 6.1 1.0 6.6 ns
see Figs 5 and 6 50 pF 4.0 6.5 1.0 7.5 1.0 8.0 ns
5.5 8.0 1.0 8.5 1.0 9.0 ns
2000 May 02 8
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Buffer with open-drain output
AC WAVEFORMS
handbook, full pagewidth
inA input
outY output
FAMILY
AHC1G GND to V
VI INPUT
REQUIREMENTS
CC
AHCT1G GND to 3.0 V 1.5 V 50% V
V
I
GND
V
CC
V
OL
(1)
V
M
INPUT
50% VCC50% V
(1)
V
M
t
PLZ
(2)
V
M
OUTPUT
CC CC
VOL + 0.3 V
t
PZL
74AHC1G07;
74AHCT1G07
(2)
V
M
MNA592
handbook, full pagewidth
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
open V
CC
GND
Fig.5 The input inA to output outY propagation delays.
S1
V
CC
V
CC
V
PULSE
GENERATOR
Definitions for test circuit: CL= Load capacitance including jig and probe capacitance (see Chapter “AC characteristics”). RT= Termination resistance should be equaltothe output impedance Z0of the pulse generator.
I
R
D.U.T.
T
V
O
RL = 1000
C
L
MNA232
open GND
Fig.6 Load circuitry for switching times.
2000 May 02 9
Page 10
Buffer with open-drain output
74AHC1G07;
74AHCT1G07
PACKAGE OUTLINE
Plastic surface mounted package; 5 leads SOT353
D
y
E
H
E
AB
45
X
v M
A
132
e
1
DIMENSIONS (mm are the original dimensions)
A
UNIT
mm
A
1.1
0.8
max
0.1
1
b
p
0.30
0.25
0.20
0.10
b
p
e
cD
2.2
1.8
A
wBM
0 1 2 mm
scale
E
1.35
1.15
(2)
1.3
e
0.65
H
E
1
2.2
0.45
2.0
0.15
e
A
1
detail X
L
Qywv
p
0.25
0.15
0.2 0.10.2
Q
L
p
c
OUTLINE
VERSION
SOT353
IEC JEDEC EIAJ
REFERENCES
2000 May 02 10
EUROPEAN
PROJECTION
ISSUE DATE
97-02-28SC-88A
Page 11
Buffer with open-drain output
SOLDERING Introduction to soldering surface mount packages
Thistextgivesaverybriefinsighttoacomplextechnology. A more in-depth account of soldering ICs can be found in our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011). There is no soldering method that is ideal for all surface
mount IC packages. Wave solderingis not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used.
Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied totheprinted-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C.
Wave soldering
Conventional single wave soldering is not recommended forsurfacemountdevices(SMDs)orprinted-circuitboards with a high component density, as solder bridging and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically developed.
74AHC1G07;
74AHCT1G07
If wave soldering is used the following conditions must be observed for optimal results:
Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
Forpackageswithleadsonfoursides,thefootprintmust be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
2000 May 02 11
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Buffer with open-drain output
74AHC1G07;
74AHCT1G07
Suitability of surface mount IC packages for wave and reflow soldering methods
PACKAGE
BGA, LFBGA, SQFP, TFBGA not suitable suitable HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable
(3)
PLCC LQFP, QFP, TQFP not recommended SSOP, TSSOP, VSO not recommended
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
, SO, SOJ suitable suitable
temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
The package footprint must incorporate solder thieves downstream and at the side corners.
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
SOLDERING METHOD
WAVE REFLOW
(2)
(3)(4) (5)
suitable
suitable suitable
(1)
.
2000 May 02 12
Page 13
Buffer with open-drain output
74AHC1G07;
74AHCT1G07
DATA SHEET STATUS
DATA SHEET STATUS
Objective specification Development This data sheet contains the design target or goal specifications for
Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be
Product specification Production This data sheet contains final specifications. Philips Semiconductors
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
DEFINITIONS Short-form specification The data in a short-form
specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.
Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device attheseoratanyotherconditionsabovethosegiveninthe Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make norepresentationorwarrantythatsuchapplicationswill be suitable for the specified use without further testing or modification.
PRODUCT
STATUS
DEFINITIONS
product development. Specification may change in any manner without notice.
published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
DISCLAIMERS Life support applications These products are not
designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to resultin personal injury. Philips Semiconductorscustomersusingorsellingtheseproducts for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes  Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for theuseofanyoftheseproducts,conveysnolicenceortitle under any patent, copyright, or mask work right to these products,andmakesnorepresentations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
(1)
2000 May 02 13
Page 14
Buffer with open-drain output
74AHC1G07;
74AHCT1G07
NOTES
2000 May 02 14
Page 15
Buffer with open-drain output
74AHC1G07;
74AHCT1G07
NOTES
2000 May 02 15
Page 16
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2000
Internet: http://www.semiconductors.philips.com
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Printed in The Netherlands 613507/01/pp16 Date of release: 2000 May 02 Document order number: 9397 750 07041
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