Datasheet 74AHC1G00, 74AHCT1G00 Datasheet (Philips)

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INTEGRATED CIRCUITS

DATA SH EET

74AHC1G00; 74AHCT1G00

2-input NAND gate

Product specification
Supersedes data of 2002 Feb 27

2002 May 27

Philips Semiconductors Product specification

2-input NAND gate 74AHC1G00; 74AHCT1G00

FEATURES

• Symmetrical output impedance

• High noise immunity

• ESD protection:

– HBM EIA/JESD22-A114-A exceeds 2000 V

DESCRIPTION

The74AHC1G/AHCT1G00isahigh-speedSi-gateCMOS
device.

The 74AHC1G/AHCT1G00 provides the 2-input NAND
function.

– MM EIA/JESD22-A115-A exceeds 200 V
– CDM EIA/JESD22-C101 exceeds 1000 V.

• Low power dissipation

• Balanced propagation delays

• Very small 5-pin package

• Output capability: standard

• Specified from −40 to +125 °C.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf≤3.0 ns.

amb

SYMBOL PARAMETER CONDITIONS

t

PHL/tPLH

C

I

C

PD

propagation delay A and B to Y CL= 15 pF; VCC= 5 V 3.5 3.6 ns
input capacitance 1.5 1.5 pF
power dissipation capacitance CL= 50 pF; f = 1 MHz;

notes 1 and 2

TYPICAL

UNIT

AHC1G AHCT1G

17 18 pF

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW).

PD

PD=CPD× V

2

× fi+(CL×V

CC

CC

fi= input frequency in MHz;

= output frequency in MHz;

f

o

CL= output load capacitance in pF
VCC= supply voltage in Volts.

2. The condition is VI= GND to VCC.

2

× fo) where:

2002 May 27 2

Philips Semiconductors Product specification

2-input NAND gate 74AHC1G00; 74AHCT1G00

FUNCTION TABLE

See note 1.

INPUTS OUTPUT

ABY

LLH

LHH
HLH
HHL

Note

1. H = HIGH voltage level;
L = LOW voltage level.

ORDERING INFORMATION

PACKAGES

TYPE NUMBER

74AHC1G00GW −40to +125 °C 5 SC-88A plastic SOT353 AA
74AHCT1G00GW −40 to +125 °C 5 SC-88A plastic SOT353 CA
74AHC1G00GV −40 to +125 °C 5 SC-74A plastic SOT753 A00
74AHCT1G00GV −40 to +125 °C 5 SC-74A plastic SOT753 C00

TEMPERATURE

RANGE

PINS PACKAGE MATERIAL CODE MARKING

PINNING

PIN SYMBOL DESCRIPTION

1 B data input B
2 A data input A
3 GND ground (0 V)
4 Y data output Y
5V

CC

supply voltage

2002 May 27 3

Philips Semiconductors Product specification

2-input NAND gate 74AHC1G00; 74AHCT1G00

handbook, halfpage

B

GND

1

A

2
3

5

00

4

MNA096

Fig.1 Pin configuration.

V

CC

Y

handbook, halfpage

1

B

2

A

MNA097

4

Y

Fig.2 Logic symbol.

handbook, halfpage

1
2

&

4

MNA098

Fig.3 IEC logic symbol.

2002 May 27 4

handbook, halfpage

B

A

Fig.4 Logic diagram.

Y

MNA099

Philips Semiconductors Product specification

2-input NAND gate 74AHC1G00; 74AHCT1G00

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS

UNIT

MIN. TYP. MAX. MIN. TYP. MAX.

74AHC1G 74AHCT1G

V

CC

V

I

V

O

T

amb

t

r,tf

(∆t/∆f)

supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
input voltage 0 − 5.5 0 − 5.5 V
output voltage 0 − V
operating ambient

temperature
input rise and fall

times

see DC and AC

−40 +25 +125 −40 +25 +125 °C

characteristics per device
VCC= 3.3 ±0.3 V −−100 −−−ns/V
V

=5±0.5 V −−20 −−20 ns/V

CC

0 − V

CC

CC

V

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

V

I

I

IK

I

OK

I

O

I

CC

T

stg

P

D

supply voltage −0.5 +7.0 V
input voltage −0.5 +7.0 V
input diode current VI< −0.5 V −−20 mA
output diode current VO< −0.5 V or VO>VCC+ 0.5 V; note 1 −±20 mA
output source or sink current −0.5V<VO<VCC+ 0.5 V −±25 mA
VCC or GND current −±75 mA
storage temperature −65 +150 °C
power dissipation per package for temperature range from −40 to +125 °C − 250 mW

Note

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2002 May 27 5

Philips Semiconductors Product specification

2-input NAND gate 74AHC1G00; 74AHCT1G00

DC CHARACTERISTICS
Family 74AHC1G

At recommended operating conditions; voltages are referenced to GND (ground=0V).

SYMBOL PARAMETER

V

IH

HIGH-level input
voltage

V

IL

LOW-level input
voltage

V

OH

HIGH-leveloutput
voltage

V

OL

LOW-level output
voltage

I

LI

input leakage
current

I

CC

quiescent supply
current

C

I

input capacitance − 1.5 10 − 10 − 10 pF

TEST CONDITIONS T

OTHER

V

CC

(V)

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

25 -40 to +85 -40 to +125

amb

(°C)

UNIT

2.0 1.5 −−1.5 − 1.5 − V

3.0 2.1 −−2.1 − 2.1 − V

5.5 3.85 −−3.85 − 3.85 − V

2.0 −− 0.5 − 0.5 − 0.5 V

3.0 −− 0.9 − 0.9 − 0.9 V

5.5 −− 1.65 − 1.65 − 1.65 V

VI=VIHor VIL;

2.0 1.9 2.0 − 1.9 − 1.9 − V

IO= −50 µA
V

I=VIH

or VIL;

3.0 2.9 3.0 − 2.9 − 2.9 − V

IO= −50 µA
V

I=VIH

or VIL;

4.5 4.4 4.5 − 4.4 − 4.4 − V

IO= −50 µA
V

I=VIH

or VIL;

3.0 2.58 −−2.48 − 2.40 − V

IO= −4.0 mA
V

I=VIH

or VIL;

4.5 3.94 −−3.8 − 3.70 − V

IO= −8.0 mA
VI=VIHor VIL;

2.0 − 0 0.1 − 0.1 − 0.1 V

IO=50µA
V

I=VIH

or VIL;

3.0 − 0 0.1 − 0.1 − 0.1 V

IO=50µA
V

I=VIH

or VIL;

4.5 − 0 0.1 − 0.1 − 0.1 V

IO=50µA
V

I=VIH

or VIL;

3.0 −− 0.36 − 0.44 − 0.55 V

IO= 4.0 mA
V

I=VIH

or VIL;

4.5 −− 0.36 − 0.44 − 0.55 V

IO= 8.0 mA
VI=VCCor GND 5.5 −− 0.1 − 1.0 − 2.0 µA

VI=VCCor GND;

5.5 −− 1.0 − 10 − 40 µA

IO=0

2002 May 27 6

Philips Semiconductors Product specification

2-input NAND gate 74AHC1G00; 74AHCT1G00

Family 74AHCT1G

At recommended operating conditions; voltages are referenced to GND (ground=0V).

SYMBOL PARAMETER

V

IH

HIGH-level input
voltage

V

IL

LOW-level input
voltage

V

OH

HIGH-leveloutput
voltage

V

OL

LOW-level output
voltage

I

LI

input leakage
current

I

CC

quiescent supply
current

∆I

CC

additional
quiescent supply
current per input
pin

C

I

input capacitance − 1.5 10 − 10 − 10 pF

TEST CONDITIONS T

25 −40 to +85 −40 to +125

OTHER VCC (V)

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

4.5 to 5.5 2.0 −−2.0 − 2.0 − V

4.5 to 5.5 −−0.8 − 0.8 − 0.8 V

VI=VIHor VIL;

4.5 4.4 4.5 − 4.4 − 4.4 − V

IO= −50 µA
V

I=VIH

or VIL;

4.5 3.94 −−3.8 − 3.70 − V

IO= −8.0 mA
VI=VIHor VIL;

4.5 − 0 0.1 − 0.1 − 0.1 V

IO=50µA
V

I=VIH

or VIL;

4.5 −−0.36 − 0.44 − 0.55 V

IO= 8.0 mA
VI=VIHor V

VI=VCCor GND;

5.5 −−0.1 − 1.0 − 2.0 µA

IL

5.5 −−1.0 − 10 − 40 µA

IO=0
VI= 3.4 V;

5.5 −−1.35 − 1.5 − 1.5 mA
other inputs at
VCCor GND;
IO=0

amb

(°C)

UNIT

2002 May 27 7

Philips Semiconductors Product specification

2-input NAND gate 74AHC1G00; 74AHCT1G00

AC CHARACTERISTICS
Type 74AHC1G00

GND = 0 V; tr=tf≤3.0 ns.

SYMBOL PARAMETER

VCC= 3.0 to 3.6 V; note 1

t

PHL/tPLH

propagation delay
A and B to Y

V

= 4.5 to 5.5 V; note 2

CC

t

PHL/tPLH

propagation delay
A and B to Y

Notes

1. Typical values at V

CC

= 3.3 V.

2. Typical values at VCC=5V.

Type 74AHCT1G00

GND = 0 V; tr=tf≤3.0 ns.

SYMBOL PARAMETER

TEST CONDITIONS T

WAVEFORMS

C

(pF)

L

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

25 −40 to +85 −40 to +125

amb

(°C)

UNIT

see Figs 5 and 6 15 − 4.5 7.9 1.0 9.5 1.0 10.5 ns

50 − 6.5 11.4 1.0 13.0 1.0 14.5 ns

see Figs 5 and 6 15 − 3.5 5.5 1.0 6.5 1.0 7.0 ns

50 − 4.9 7.5 1.0 8.5 1.0 9.5 ns

TEST CONDITIONS T

WAVEFORMS

C

(pF)

L

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

25 −40 to +85 −40 to +125

amb

(°C)

UNIT

VCC= 4.5 to 5.5 V; note 1

t

PHL/tPLH

propagation delay
A and B to Y

Note

1. Typical values at V

CC

see Figs 5 and 6 15 − 3.6 6.2 1.0 7.1 1.0 8.0 ns

50 − 5.0 7.9 1.0 9.0 1.0 10.0 ns

=5V.

2002 May 27 8

Philips Semiconductors Product specification

2-input NAND gate 74AHC1G00; 74AHCT1G00

AC WAVEFORMS

handbook, halfpage

A, B input

V

M

Y output

FAMILY

VI INPUT

REQUIREMENTS

AHC1G GND to V

CC

V

M

INPUT

V

M

OUTPUT

50% VCC50% V

AHCT1G GND to 3.0 V 1.5 V 50% V

Fig.5 The inputs (A and B) to output (Y) propagation delays.

CC
CC

t

PHL

V

M

t

PLH

MNA106

handbook, halfpage

V

PULSE

GENERATOR

Definitions for test circuit:
CL= Load capacitance including jig and probe capacitance (see Chapter “AC characteristics”).
RT= Termination resistance should be equal to the output impedance Z0 of the pulse generator.

I

V

CC

D.U.T.

R

T

Fig.6 Load circuitry for switching times.

2002 May 27 9

V

O

C

L

MNA101

Philips Semiconductors Product specification

2-input NAND gate 74AHC1G00; 74AHCT1G00

PACKAGE OUTLINES

Plastic surface mounted package; 5 leads SOT353

D

y

45

132

e

1

e

b

p

wBM

A

A

1

E

H

E

detail X

Q

L

p

AB

X

v M

A

c

0 1 2 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

mm

A

1.1

0.8

OUTLINE

VERSION

SOT353

max

0.1

1

b

cD

p

0.30

0.20

IEC JEDEC EIAJ

0.25

0.10

2.2

1.8

(2)

E

1.35

1.3

1.15

REFERENCES

e

e

1

0.65

2002 May 27 10

H

2.2

2.0

L

Qywv

p

E

0.45

0.15

0.25

0.15

0.2 0.10.2

EUROPEAN

PROJECTION

ISSUE DATE

97-02-28SC-88A

Philips Semiconductors Product specification

2-input NAND gate 74AHC1G00; 74AHCT1G00

Plastic surface mounted package; 5 leads SOT753

D

y

E

H

E

AB

X

v M

A

45

Q

A

A

1

c

132

L

p

3.1

2.7

b

p

wBM

0 1 2 mm

scale

H

e

E

1.7

0.95

1.3

REFERENCES

E

3.0

2.5

e

DIMENSIONS (mm are the original dimensions)

A

UNIT

mm

A

0.100

1.1

0.013

0.9

OUTLINE
VERSION

SOT753 SC-74A

b

cD

p

1

0.40

0.26

0.25

0.10

IEC JEDEC JEITA

2002 May 27 11

L

Qywv

p

0.6

0.33

0.2

0.23

0.2 0.10.2

detail X

EUROPEAN

PROJECTION

ISSUE DATE

02-04-16

Philips Semiconductors Product specification

2-input NAND gate 74AHC1G00; 74AHCT1G00

SOLDERING
Introduction to soldering surface mount packages

Thistextgivesaverybriefinsighttoacomplextechnology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for
certainsurfacemountICs,butitisnotsuitableforfinepitch
SMDs. In these situations reflow soldering is
recommended.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
totheprinted-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswithleadsonfoursides,thefootprintmust
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

2002 May 27 12

Philips Semiconductors Product specification

2-input NAND gate 74AHC1G00; 74AHCT1G00

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

(1)

SOLDERING METHOD

WAVE REFLOW

(2)

BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,

not suitable

(3)

suitable

HVSON, SMS

(4)

PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

, SO, SOJ suitable suitable

(4)(5)

suitable

(6)

suitable

Notes

1. Formoredetailedinformation on the BGA packages refer to the

“(LF)BGAApplicationNote

”(AN01026);ordera copy

from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.

4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

2002 May 27 13

Philips Semiconductors Product specification

2-input NAND gate 74AHC1G00; 74AHCT1G00

DATA SHEET STATUS

PRODUCT

DATA SHEET STATUS

Objective data Development This data sheet contains data from the objective specification for product

Preliminary data Qualification This data sheet contains data from the preliminary specification.

Product data Production This data sheet contains data from the product specification. Philips

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

(1)

STATUS

(2)

DEFINITIONS

development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.

Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.

Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.

DEFINITIONS
Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseoratanyotherconditionsabovethosegiveninthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythatsuchapplicationswill be
suitable for the specified use without further testing or
modification.

DISCLAIMERS
Life support applications  These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to resultin personal injury. Philips
Semiconductorscustomersusingorsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseofanyoftheseproducts,conveysnolicenceortitle
under any patent, copyright, or mask work right to these
products,andmakesnorepresentations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

2002 May 27 14

Philips Semiconductors Product specification

2-input NAND gate 74AHC1G00; 74AHCT1G00

NOTES

2002 May 27 15

Philips Semiconductors – a w orldwide compan y

Contact information

For additional information please visit http://www.semiconductors.philips.com. Fax: [phone]
For sales offices addresses send e-mail to: [e-mail].

© Koninklijke Philips Electronics N.V. 2002
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Printed in The Netherlands 613508/05/pp16 Date of release:2002 May 27 Document order number: 9397 750 09699

SCA74