Datasheet 74AHCT08PW, 74AHCT08D, 74AHC08PW, 74AHC08D Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

74AHC08; 74AHCT08

Quad 2-input AND gate

Product specification
Supersedes data of 1998 Dec 18
File under Integrated Circuits, IC06

1999 Sep 24

Philips Semiconductors Product specification

Quad 2-input AND gate 74AHC08; 74AHCT08

FEATURES

• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V

• Balanced propagation delays

• All inputs have Schmitt-trigger

actions

• Inputsacceptsvoltageshigherthan
V

CC

• For AHC only:
operates with CMOS input levels

• For AHCT only:
operates with TTL input levels

• Specified from

−40 to +85 and +125 °C.

DESCRIPTION

The 74AHC/AHCT08 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
No. 7A.

The 74AHC/AHCT08 provide the
2-input AND function.

FUNCTION TABLE

See note 1.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf≤3.0 ns.

amb

TYPICAL

SYMBOL PARAMETER CONDITIONS

AHC AHCT

t

PHL/tPLH

C

I

C

O

C

PD

propagation delay
nA, nB to nY

input capacitance VI=VCCor GND 3.0 3.0 pF
output capacitance 4.0 4.0 pF
power dissipation

capacitance

CL= 15 pF;
VCC=5V

CL= 50 pF;
f = 1 MHz;

3.5 5.0 ns

10 12 pF

notes 1 and 2

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW).

PD

PD=CPD× V

2

× fi+ ∑ (CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz;
fo= output frequency in MHz;
∑ (CL× V

2

× fo) = sum of outputs;

CC

CL= output load capacitance in pF;
VCC= supply voltage in Volts.

2. The condition is VI= GND to VCC.

PINNING

PIN SYMBOL DESCRIPTION

1, 4, 9 and 12 1A to 4A data inputs
2, 5, 10 and 13 1B to 4B data inputs
3, 6, 8 and 11 1Y to 4Y data outputs
7 GND ground (0 V)
14 V

CC

DC supply voltage

UNIT

INPUT OUTPUT

nA nB nY

LLL

LHL
HLL
HHH

Note

1. H = HIGH voltage level;
L = LOW voltage level.

1999 Sep 24 2

Philips Semiconductors Product specification

Quad 2-input AND gate 74AHC08; 74AHCT08

ORDERING INFORMATION

OUTSIDE NORTH

AMERICA

NORTH AMERICA

PINS PACKAGE MATERIAL CODE

PACKAGES

74AHC08D 74AHC08D 14 SO plastic SOT108-1
74AHC08PW 74AHC08PW DH 14 TSSOP plastic SOT402-1
74AHCT08D 74AHCT08D 14 SO plastic SOT108-1
74AHCT08PW 74AHCT08PW DH 14 TSSOP plastic SOT402-1

handbook, halfpage

1A
1B
1Y
2A
2B
2Y

GND

1
2
3
4

08

5
6
7

MNA220

V

14

CC

13

4B

12

4A

11

4Y

10

3B

9

3A

8

3Y

handbook, halfpage

A

B

Y

MNA221

handbook, halfpage

Fig.1 Pin configuration.

1

1A

2

1B

4

2A

5

2B

9

3A

10

3B

12

4A

13

4B

1Y

2Y

3Y

4Y

MNA222

3

6

8

11

Fig.3 Functional diagram.

handbook, halfpage

Fig.2 Logic diagram (one gate).

1
2

4
5

9

10

12
13

&

&

&

&

MNA223

3

6

8

11

Fig.4 IEC logic symbol.

1999 Sep 24 3

Philips Semiconductors Product specification

Quad 2-input AND gate 74AHC08; 74AHCT08

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS

UNIT

MIN. TYP. MAX. MIN. TYP. MAX.

74AHC 74AHCT

V

CC

V

I

V

O

T

amb

DC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
input voltage 0 − 5.5 0 − 5.5 V
output voltage 0 − V
operating ambient temperature

range

see DC and AC
characteristics per

−40 +25 +85 −40 +25 +85 °C

−40 +25 +125 −40 +25 +125 °C

0 − V

CC

CC

V

device

t

(∆t/∆f) input rise and fall rates VCC= 3.3 V ±0.3 V −−100 −−−ns/V

r,tf

=5V±0.5 V −−20 −−20

V

CC

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground= 0 V).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

V

I

I

IK

I

OK

I

O

I

CC

T

stg

P

D

DC supply voltage −0.5 +7.0 V
input voltage range −0.5 +7.0 V
DC input diode current VI< −0.5 V; note 1 −−20 mA
DC output diode current VO< −0.5 Vor VO>VCC+ 0.5 V; note 1 −±20 mA
DC output source or sink current −0.5V<VO<VCC+ 0.5 V −±25 mA
DC VCC or GND current −±75 mA
storage temperature range −65 +150 °C
power dissipation per package for temperature range:−40 to +125 °C; note 2 − 500 mW

Notes

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. For SO packages: above 70 °C the value of P

derates linearly with 8 mW/K.

D

For TSSOP packages: above 60 °C the value of PDderates linearly with 5.5 mW/K.

1999 Sep 24 4

Philips Semiconductors Product specification

Quad 2-input AND gate 74AHC08; 74AHCT08

DC CHARACTERISTICS
74AHC family

Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).

SYMBOL PARAMETER

V

IH

HIGH-level input
voltage

V

IL

LOW-level input
voltage

V

OH

HIGH-level output
voltage; all
outputs

HIGH-level output
voltage

V

OL

LOW-level output
voltage; all
outputs

LOW-level output
voltage

I

I

input leakage
current

I

OZ

3-state output
OFF current

I

CC

quiescent supply
current

C

I

input capacitance −−310−10 − 10 pF

TEST CONDITIONS T

25 −40 to +85 −40 to +125

amb

(°C)

UNIT

OTHER VCC(V)

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

2.0 1.5 −−1.5 − 1.5 − V

3.0 2.1 −−2.1 − 2.1 −

5.5 3.85 −−3.85 − 3.85 −

2.0 −− 0.5 − 0.5 − 0.5 V

3.0 −− 0.9 − 0.9 − 0.9

5.5 −− 1.65 − 1.65 − 1.65

VI=VIHor VIL;
IO= −50 µA

2.0 1.9 2.0 − 1.9 − 1.9 − V

3.0 2.9 3.0 − 2.9 − 2.9 −

4.5 4.4 4.5 − 4.4 − 4.4 −

V

I=VIH

or VIL;

3.0 2.58 −−2.48 − 2.40 − V

IO= −4.0 mA
V

I=VIH

or VIL;

4.5 3.94 −−3.8 − 3.70 −

IO= −8.0 mA
VI=VIHor VIL;

IO=50µA

2.0 − 0 0.1 − 0.1 − 0.1 V

3.0 − 0 0.1 − 0.1 − 0.1

4.5 − 0 0.1 − 0.1 − 0.1

V

I=VIH

or VIL;

3.0 −− 0.36 − 0.44 − 0.55 V

IO=4mA
V

I=VIH

or VIL;

4.5 −− 0.36 − 0.44 − 0.55

IO=8mA
VI=VCCor GND 5.5 −− 0.1 − 1.0 − 2.0 µA

VI=VIHor VIL;

5.5 −− ±0.25 −±2.5 −±10.0 µA

VO=VCCor GND
VI=VCCor GND;

5.5 −− 2.0 − 20 − 40 µA

IO=0

1999 Sep 24 5

Philips Semiconductors Product specification

Quad 2-input AND gate 74AHC08; 74AHCT08

74AHCT family

Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).

SYMBOL PARAMETER

V

IH

HIGH-level input
voltage

V

IL

LOW-level input
voltage

V

OH

HIGH-level output
voltage; all outputs

HIGH-level output
voltage

V

OL

LOW-level output
voltage; all outputs

LOW-level output
voltage

I

I

input leakage
current

I

OZ

3-state output
OFF current

I

CC

quiescent supply
current

∆I

CC

additional
quiescent supply
current per input
pin

C

I

input capacitance −−310−10 − 10 pF

TEST CONDITIONS T

25 −40 to +85 −40 to +125

OTHER VCC(V)

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

4.5 to 5.5 2.0 −−2.0 − 2.0 − V

4.5 to 5.5 −− 0.8 − 0.8 − 0.8 V

VI=VIHor VIL;

4.5 4.4 4.5 − 4.4 − 4.4 − V

IO= −50 µA
V

I=VIH

or VIL;

4.5 3.94 −−3.8 − 3.70 − V

IO= −8.0 mA
VI=VIHor VIL;

4.5 − 0 0.1 − 0.1 − 0.1 V

IO=50µA
V

I=VIH

or VIL;

4.5 −− 0.36 − 0.44 − 0.55 V

IO=8mA
VI=VIHor V

VI=VIHor VIL;

5.5 −− 0.1 − 1.0 − 2.0 µA

IL

5.5 −− ±0.25 −±2.5 −±10.0 µA
VO=VCCor GND
per input pin;
other inputs at
VCCor GND;
IO=0

VI=VCCor GND;

5.5 −− 2.0 − 20 − 40 µA
IO=0

VI=VCC− 2.1 V

4.5 to 5.5 −− 1.35 − 1.5 − 1.5 mA
other inputs at
VCCor GND;
IO=0

amb

(°C)

UNIT

1999 Sep 24 6

Philips Semiconductors Product specification

Quad 2-input AND gate 74AHC08; 74AHCT08

AC CHARACTERISTICS
Type 74AHC08

GND = 0 V; tr=tf≤3.0 ns.

SYMBOL PARAMETER

VCC= 3.0 to 3.6 V; note 1

t

PHL/tPLH

propagation delay
nA, nB to nY

V

= 4.5 to 5.5 V; note 2

CC

t

PHL/tPLH

propagation delay
nA, nB to nY

Notes

1. Typical values at V

CC

= 3.3 V.

2. Typical values at VCC= 5.0 V.

Type 74AHCT08

GND = 0 V; tr=tf≤3.0 ns.

SYMBOL PARAMETER

TEST CONDITIONS T

25 −40 to +85 −40 to +125

WAVEFORMS C

L

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

amb

(°C)

UNIT

see Figs 5 and 6 15 pF − 4.0 8.8 1.0 10.5 1.0 11.0 ns

50 pF − 5.6 12.3 1.0 14.0 1.0 15.5 ns

see Figs 5 and 6 15 pF − 3.0 5.9 1.0 7.0 1.0 7.5 ns

50 pF − 4.2 7.9 1.0 9.0 1.0 10.0 ns

TEST CONDITIONS T

25 −40 to +85 −40 to +125

WAVEFORMS C

L

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

amb

(°C)

UNIT

VCC= 4.5 to 5.5 V; note 1

t

PHL/tPLH

propagation delay
nA, nB to nY

Note

1. Typical values at V

CC

see Figs 5 and 6 15 pF − 3.2 6.9 1.0 8.0 1.0 9.0 ns

50 pF − 4.4 7.9 1.0 9.0 1.0 10.0 ns

= 5.0 V.

1999 Sep 24 7

Philips Semiconductors Product specification

Quad 2-input AND gate 74AHC08; 74AHCT08

AC WAVEFORMS

V

I

GND

V

OH

V

OL

(1)

M

V

OUTPUT

50% V

CC

FAMILY

VI INPUT

REQUIREMENTS

74AHC GND to V

CC

handbook, halfpage

nA, nB INPUT

nY OUTPUT

V

INPUT

50% V

74AHCT GND to 3.0 V 1.5 V 50% V

Fig.5 The input (nA, nB) to output (nY) propagation delays.

(1)

V

M

t

PHL

(1)

V

M

(1)

M

CC
CC

t

PLH

MNA224

handbook, full pagewidth

V

CC

V

I

R

D.U.T.

T

TEST S

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

open
V

CC

GND

PULSE

GENERATOR

1

Fig.6 Load circuitry for switching times.

1999 Sep 24 8

S

V

1

CC

open

V

O

1000 Ω

C

L

MNA225

GND

Philips Semiconductors Product specification

Quad 2-input AND gate 74AHC08; 74AHCT08

PACKAGE OUTLINES

SO14: plastic small outline package; 14 leads; body width 3.9 mm

D

c

y

Z

14

pin 1 index

1

e

8

A

2

7

w M

b

p

SOT108-1

E

H

E

A

1

L

detail X

A

X

v M

A

Q

(A )

L

p

A

3

θ

0 2.5 5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

OUTLINE
VERSION

SOT108-1

A

max.

1.75

0.069

A2A

A

1

0.25

0.10

0.010

0.004

1.45

1.25

0.057

0.049

3

0.25

0.01

IEC JEDEC EIAJ

076E06S MS-012AB

b

p

0.49

0.36

0.019

0.014

0.25

0.19

0.0100

0.0075

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

(1)E(1)

cD

8.75

8.55

0.35

0.34

REFERENCES

4.0

3.8

0.16

0.15

1.27

0.050

1999 Sep 24 9

eHELLpQZywv θ

1.05

0.041

1.0

0.4

0.039

0.016

0.7

0.25

0.6

0.028

0.01 0.004

0.024

EUROPEAN

PROJECTION

0.25 0.1

0.01

6.2

5.8

0.244

0.228

(1)

0.7

0.3

0.028

0.012

ISSUE DATE

95-01-23
97-05-22

o

8

o

0

Philips Semiconductors Product specification

Quad 2-input AND gate 74AHC08; 74AHCT08

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

D

c

y

Z

14

pin 1 index

8

17

w M

b

e

p

A

2

A

1

E

H

E

L

detail X

SOT402-1

A

X

v M

A

Q

(A )

3

A

θ

L

p

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A1A2A

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

A

max.

0.15

mm

1.10

OUTLINE
VERSION

SOT402-1 MO-153

0.05

0.95

0.80

IEC JEDEC EIAJ

0.25

b

3

p

0.30

0.19

(1)E(2) (1)

cD

0.2

5.1

4.5

0.1

REFERENCES

4.9

4.3

0.65

1999 Sep 24 10

eHELLpQZywv θ

6.6

6.2

0.75

0.50

0.4

0.3

EUROPEAN

PROJECTION

0.13 0.10.21.0

0.72

0.38

ISSUE DATE

94-07-12
95-04-04

o

8

o

0

Philips Semiconductors Product specification

Quad 2-input AND gate 74AHC08; 74AHCT08

SOLDERING
Introduction to soldering surface mount packages

Thistext gives a verybriefinsight to a complextechnology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages.Wave soldering isnot alwayssuitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit boardbyscreen printing, stencillingor
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating,soldering andcooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswith leads onfoursides,the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement andbefore soldering,the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemount devices (SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Sep 24 11

Philips Semiconductors Product specification

Quad 2-input AND gate 74AHC08; 74AHCT08

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, LFBGA, SQFP, TFBGA not suitable suitable

SOLDERING METHOD

HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable forSSOP andTSSOP packages with a pitch (e) equal to or larger than0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Sep 24 12

Philips Semiconductors Product specification

Quad 2-input AND gate 74AHC08; 74AHCT08

NOTES

1999 Sep 24 13

Philips Semiconductors Product specification

Quad 2-input AND gate 74AHC08; 74AHCT08

NOTES

1999 Sep 24 14

Philips Semiconductors Product specification

Quad 2-input AND gate 74AHC08; 74AHCT08

NOTES

1999 Sep 24 15

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New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

1999

Internet: http://www.semiconductors.philips.com

68

Printed in The Netherlands 245002/02/pp16 Date of release: 1999 Sep 24 Document order number: 9397 750 06287