Datasheet 74ACTQ02SCX, 74ACTQ02SC, 74ACTQ02PC, 74ACTQ02MTCX, 74ACTQ02MTC Datasheet (Fairchild Semiconductor)

© 1999 Fairchild Semiconductor Corporation DS010889 www.fairchildsemi.com

August 1990
Revised November 1999

74ACTQ02 Quad 2-Input NOR Gate

74ACTQ02
Quad 2-Input NOR Gate

General Description

The ACTQ02 contains four, 2-input NOR gates.
The ACTQ utilize Fairchild’s Quiet Series technology to

guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series features
GTO output control and unde rshoot corre ctor in add ition
to a split ground bus for superior ACMOS performance.

Features

■ ICC reduced by 50%

■ Guaranteed simultaneous switching noise level and

dynamic threshold performan ce

■ Improved latch-up immunity

■ Outputs source/sink 24 mA

■ ACTQ02 has TTL-compatibl e inputs

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

IEEE/IEC

Connection Diagram

Pin Descriptions

FACT, FACT Quiet Series, and GTO are trademarks of F airchild Semiconductor Corporation.

Order Number Package Number Package Description

74ACTQ02SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
74ACTQ02SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACTQ02PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Names Description

A

n

, B

n

Inputs

O

n

Outputs

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74ACTQ02

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, with­out exception, to ensure that the system design is reliable over its power
supply, temperature, and ou tput/inp ut loadi ng varia bles. Fairchild does no t
recommend operat ion of FACT circuits outside da t abook specifications.

DC Electrical Characteristics

Note 2: All outputs loaded; thresholds on input assoc iat ed with output under tes t.
Note 3: Maximum test duratio n 2. 0 ms, one output loaded at a time.
Note 4: Plastic DIP package
Note 5: Max number of output s d ef ined as (n). Data inputs are 0V to 3V. One output @ GND.
Note 6: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (V

ILD

),

0V to threshold (V

IHD

), f = 1 MHz.

Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I

IK

)

V

I

= −0.5V −20 mA

V

I

= VCC + 0.5V +20 mA

DC Input Voltage (V

I

) −0.5V to VCC + 0.5V

DC Output Diode Current (I

OK

)

V

O

= −0.5V −20 mA

V

O

= VCC + 0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to VCC + 0.5V

DC Output Source

or Sink Current (I

O

) ±50 mA

DC V

CC

or Ground Current

per Output Pin (I

CC

or I

GND

) ±50 mA

Storage Temperature (T

STG

) −65°C to +150°C

DC Latch-Up Source or

Sink Current ±300 mA

Junction Temperature (T

J

)

PDIP 140°C

Supply Voltage (V

CC

) 4.5V to 5.5V

Input Voltage (V

I

) 0V to V

CC

Output Voltage (VO) 0V to V

CC

Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t) 125 mV/ns

V

IN

from 0.8V to 2.0V

V

CC

@ 4.5V, 5.5V

Symbol Parameter

V

CC

(V)

TA = +25°CTA = −40°C to +85°C

Units Conditions

Typ Guaranteed Limits

V

IH

Minimum HIGH Level 4.5 1.5 2.0 2.0

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V

V

IL

Maximum LOW Level 4.5 1.5 0.8 0.8

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V

V

OH

Minimum HIGH Level 4.5 4.49 4.4 4.4

VI

OUT

= −50 µA

Output Voltage 5.5 5.49 5.4 5.4

V

IN

= VIL or V

IH

4.5 3.86 3.76 V IOH = −24 mA

5.5 4.86 4.76 IOH = −24 mA (Note 2)

V

OL

Maximum LOW Level 4.5 0.001 0.1 0.1

VI

OUT

= 50 µA

Output Voltage 5.5 0.001 0.1 0.1

VIN = VIL or V

IH

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 I

OL

= 24 mA (Note 2)

I

IN

Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAVI = VCC, GND

I

CCT

Maximum ICC/Input 5.5 1.6 1.5 mA VI = VCC − 2.1V

I

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

I

OHD

Output Current (Note 3) 5.5 −75 mA V

OHD

= 3.85V Min

I

CC

Maximum Quiescent Supply Current 5.5 2.0 20.0 µAVIN = VCC or GND

V

OLP

Quiet Output
|Maximum Dynamic V

OL

5.0 1.1 1.5 V

Figure 1, Figure 2
(Note 4)(Note 5)

V

OLV

Quiet Output
Minimum Dynamic V

OL

5.0 −0.6 −1.2 V

Figure 1, Figure 2
(Note 4)(Note 5)

V

IHD

Minimum HIGH Level
Dynamic Input Voltage

5.0 1.9 2.2 V (Note 4)(Note 6)

V

ILD

Maximum LOW Level
Dynamic Input Voltage

5.0 1.2 0.8 V (Note 4)(Note 6)

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74ACTQ02

AC Electrical Characteristics

Note 7: Voltage Range 5.0 is 5.0V ± 0.5V
Note 8: Skew is defined as t he absolute value of t he difference between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t

OSHL

) or LOW-to-HIGH (t

OSLH

). Parameter guaranteed by design.

Capacitance

V

CC

TA = +25°CT

A

= −40°C to +85°C

Symbol Parameter (V)

C

L

= 50 pF CL = 50 pF

Units

(Note 7) Min Typ Max Min Max

t

PLH

Propagation Delay Data to Output 5.0 2.0 5.0 7.5 2.0 8.0 ns

t

PHL

Propagation Delay Data to Output 5.0 2.0 5.0 7.5 2.0 8.0 ns

t

OSHL,

Output to Output

5.0 0.5 1.0 1.0 ns

t

OSLH

Skew (Note 8)

Symbol Parameter Typ Units Conditions

C

IN

Input Capacitance 4.5 pF VCC = OPEN

C

PD

Power Dissipation Capacitance 75 pF VCC = 5.0V

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74ACTQ02

FACT Noise Characteristics

The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristic s of FA CT.

Equipment:

Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope

Procedure:

1. Verify Test Fixture Loading: Standard Load 50 pF,
500Ω.

2. Deskew the HFS generator so that no two channels
have greater than 15 0 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs sw itch
simultaneously.

3. Terminate all inputs and outputs to ens ure pro per load ­ing of the outputs a nd that the input levels a re at the
correct voltage.

4. Set the HFS ge nerato r to togg le all bu t one out put at a
frequency of 1 MHz. Greater fre quencies will increa se
DUT heating and affect the results of the measure­ment.

FIGURE 1. Quiet Output Noise Voltage Waveforms

Note 9: V

OHV

and V

OLP

are measured with respect to ground refer-

ence.
Note 10: Input pulses have the following char acteristics: f = 1 M Hz,

t

r

= 3ns, tf = 3 ns, skew < 150 ps.

5. Set the HFS gene rator input lev els at 0V LOW a nd 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.

V

OLP/VOLV

and V

OHP/VOHV

:

• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the gr ound pin. Monitor th e o utp ut volt­ages using a 50Ω coaxi al cable p lugg ed into a standa rd
SMB type connector on the te st fixture. Do not use an
active FET probe.

• Measure V

OLP

and V

OLV

on the quiet output du ring the

worst case transition for ac tive and enable. V

OHP

and

V

OHV

on the quiet output during the worst case transition

for active and enable.

• Verify t hat the GND reference recorded on the oscillo­scope has not drifted to ensure the accuracy and repeat­ability of the measurements.

V

ILD

and V

IHD

:

• Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connec tor on
the test fixture. Do not use an active FET probe.

• First increase the input LOW voltage level , V

IL

, until the

output begins to oscillate or steps ou t a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V

IL

limits, or on output HIGH levels that

exceed V

IH

limits. The input LOW voltage level at which

oscillation occurs is defined as V

ILD

.

• Next decrease the input HIGH voltage level, V

IH

, until

the output begins to oscillate or step s out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V

IL

limits, or on output HIGH levels that

exceed V

IH

limits. The input HIGH voltage level at which

oscillation occurs is defined as V

IHD

.

• Verify t hat the GND reference recorded on the oscillo­scope has not drifted to ensure the accuracy and repeat­ability of the measurements.

FIGURE 2. Simultaneous Switching Test Circuit

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74ACTQ02

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body

Package Number M14A

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74ACTQ02

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

7 www.fairchildsemi.com

74ACTQ02 Quad 2-Input NOR Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the labe l ing, can be re a­sonably expected to result in a significant injury to the
user.

2. A critical compo nent in any com ponen t of a life s upp ort
device or system whose failure to perform can be rea­sonably expected to cause the failure of the l ife support
device or system, or to affect its safety or effectiveness.

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