Datasheet 74ACT373 Datasheet (SGS Thomson Microelectronics)

74ACT373

OCTAL D-TYPE LATCH

WITH 3 STATE OUTPUT NON INVERTING

■ HIGH SPEED: t

■ LOWPOWERDISSIPATION:

=8µA (MAX.)at TA=25oC

I

CC

■ COMPATIBLEWITH TTL OUTPUTS

V

=2V(MIN),VIL= 0.8V (MAX)

IH

■ 50Ω TRANSMISSIONLINE DRIVING

=6 ns (TYP.)atVCC=5V

PD

CAPABILITY

■ SYMMETRICAL OUTPUT IMPEDANCE:

|I

|=IOL=24mA(MIN)

OH

■ BALANCED PROPAGATIONDELAYS:

t

≅ t

PLH

PHL

■ OPERATINGVOLTAGERANGE:

V

(OPR)= 4.5V to 5.5V

CC

■ PIN AND FUNCTION COMPATIBLE WITH

74SERIES373

■ IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The ACT373 is an advanced high-speed CMOS
OCTAL D-TYPE LATCH with 3 STATE OUTPUT
NON INVERTING fabricated with sub-micron
silicon gate and double-layermetal wiring C

2

MOS
technology. It is ideal for low power applications
mantaining high speed operation similar to
equivalentBipolar Schottky TTL.

These 8 bit D-Type latch are controlledby a latch
enable input (LE) and an output enable input

B

(Plastic Package)

(Micro Package)

M

ORDER CODES :

74ACT373B 74ACT373M

(OE).
While the LE inputs is held at a high level, the Q

outputs will follow the data input precisely or
inversely. When the LE is taken low, the Q
outputs will be latched precisely or inversely at
the logic level of D input data. While the (OE)
input is low, the 8 outputs will be in a normallogic
state (high or low logic level) and while high level
the outputs will be in a high impedance state.

This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.

All inputs and outputs are equipped with
protectioncircuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.

PINCONNECTION AND IEC LOGIC SYMBOLS

April 1997

1/10

74ACT373

INPUTAND OUTPUTEQUIVALENTCIRCUIT PIN DESCRIPTION

PI N No SYM B O L NAME AN D FUNCT I ON

1 OE 3 State Output Enable

2, 5, 6,

9, 12, 15,

16, 19

3, 4, 7,

8, 13, 14,

17, 18

11 LE Latch Enable

10 GND Ground (0V)
20 V

TRUTH TABLE

INPUTS OUTPUTS

OE LE D Q

HXXZ
L L X NO CHANGE *
LHLL
LHHH

X:DON’T CARE
Z:HIGHIMPEDANCE
*:Q OUTPUTS ARE LATCHED AT THE TIMEWHENTHE LE INPUTIS TAKEN LOWLOGIC LEVEL.

Q0 to Q7 Data Inputs

D0 to D7 3 State Outputs

CC

Input (Active LOW)

Input

Positive Supply Voltage

LOGICDIAGRAMS

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74ACT373

ABSOLUTE MAXIMUM RATINGS

Symb o l Parameter Val u e Uni t

V

V

V

I

I

OK

I

orI

I

CC

T

T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.

RECOMMENDEDOPERATINGCONDITIONS

Symbol Parameter Valu e Unit

V

V

V

T

dt/dv Input Rise and Fall Time V

1) VINfrom0.8Vto2.0V

Supply Voltage -0.5 to +7 V

CC

DC Input Voltage -0.5 to VCC+ 0.5 V

I

DC Output Voltage -0.5 to VCC+ 0.5 V

O

DC Input Diode Current ± 20 mA

IK

DC Output Diode Current ± 20 mA
DC Output Current ± 50 mA

O

DC VCCor Ground Current ± 400 mA

GND

Storage Temperature -65 to +150

stg

Lead Temperature (10 sec) 300

L

Supply Voltage 4.5 to 5.5 V

CC

Input Voltage 0 to V

I

Output Voltage 0 to V

O

Operating Temperature: -40 to +85

op

= 4.5 to 5.5V (note 1) 8 ns/V

CC

CC
CC

o

C

o

C

V
V

o

C

3/10

74ACT373

DC SPECIFICATIONS

Symbol Parameter Test Condit ions Value Unit

=25oC-40to85

V

CC

(V)

High Level Input Voltage 4.5 VO= 0.1 V or

V

IH

5.5 2.0 1.5 2.0

Low Level Input Voltage 4.5 VO= 0.1 V or

V

IL

5.5 1.5 0.8 0.8

High Level Output

V

OH

Voltage

4.5

5.5 I

4.5 I

5.5 I

Low Level Output

V

OL

Voltage

4.5

5.5 I

4.5 I

5.5 I

Input Leakage Current

I

I

3 State Output Leakage

I

OZ

5.5

5.5 VI=VIHor V

Current
Max ICC/Input 5.5 VI=VCC-2.1 V 0.6 1.5 mA

I

CCT

Quiescent Supply

I

CC

5.5 VI=VCCor GND 8 80 µA

V

- 0.1 V

CC

- 0.1 V

V

CC

IO=-50 µA 4.4 4.49 4.4

(*)

=

V

I

V

IH

V

IL

(*)

V

I

V

IH

V

IL

=-50 µA 5.4 5.49 5.4

O

or

=-24 mA 3.86 3.76

O

=-24 mA 4.86 4.76

O

IO=50 µA 0.001 0.1 0.1

=

=50 mA 0.001 0.1 0.1

O

or

=24 mA 0.36 0.44

O

=24 mA 0.36 0.44

O

VI=VCCor GND ±0.1 ±1 µA

VO=VCCor GND

IL

T

A

Min. Typ. Max. Min . Max.

2.0 1.5 2.0

1.5 0.8 0.8

±0.5 ±5 µA

o

C

Current
Dynamic Output Current

I

OLD

OHD

(note 1, 2)

I

1) Maximum testduration 2ms, one output loaded at time

2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 Ω.
(*)All outputs loaded.

5.5 V

= 1.65 V max 75 mA

OLD

V

= 3.85 V min -75 mA

OHD

V

V

V

V

4/10

AC ELECTRICAL CHARACTERISTICS (CL= 50 pF, RL=500 Ω, Inputtr=tf=3ns)

74ACT373

Symbol Parameter Test Cond ition Value Unit

o

C

t

Propagation Delay Time

PLH

t

LE to Q

PHL

Propagation Delay Time

t

PLH

t

DtoQ

PHL

Output Enable Time 5.0

t

PZL

t

PZH

t

Output Disable Time 5.0

PLH

t

PHL

t

CK Pulse Width, HIGH

w

V

(V)

5.0

5.0

5.0

CC

=25oC-40to85

T

A

Min. Typ. Max. Min . Max.

(*)

(*)

(*)

(*)

(*)

6.0 10.0 11.5 ns

5.5 10.0 11.5 ns

6.0 9.5 10.5 ns

7.0 11.0 12.5 ns

1.0 7.0 8.0 ns

or LOW
Setup Time Q to CK

t

s

5.0

(*)

0.5 7.0 8.0 ns

HIGH or LOW
Hold Time Q to CK

t

h

5.0

(*)

0.5 0.0 1.0 ns

HIGH or LOW

(*) Voltagerangeis5V ± 0.5V

CAPACITIVE CHARACTERISTICS

Symbol Parameter Test Condit ions Value Unit

T

V

CC

(V)

C

Output Capacitance 5.0 10 pF

OUT

Input Capacitance

C

IN

Power Dissipation

C

PD

5.0

5.0 25 pF

=25oC-40to85

A

Min. Typ. Max. Min . Max.

5

Capacitance (note 1)

1) CPDis defined as the value ofthe IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to
Test Circuit). Average operating current can be obtained by the following equation. I

(opr) =CPD• VCC• fIN+ICC/n (per circuit)

CC

o

C

pF

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74ACT373

TEST CIRCUIT

TEST SWI TCH

t

PLH,tPHL

t

PZL,tPLZ

t

PZH,tPHZ

CL= 50 pF or equivalent (includes jig and probe capa citance)

= 500Ω or equivalent

R

L=R1

R

of pulse generator (typically 50Ω)

T=ZOUT

Open

2V

CC

Open

WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH,
Dn TOLE SETUPAND HOLD TIMES (f=1MHz;50% dutycycle)

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WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)

74ACT373

WAVEFORM 3: PROPAGATIONDELAY TIME (f=1MHz; 50% duty cycle)

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74ACT373

Plastic DIP20 (0.25) MECHANICAL DATA

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.254 0.010

B 1.39 1.65 0.055 0.065
b 0.45 0.018

b1 0.25 0.010

D 25.4 1.000

E 8.5 0.335
e 2.54 0.100

e3 22.86 0.900

F 7.1 0.280

I 3.93 0.155
L 3.3 0.130
Z 1.34 0.053

mm inch

8/10

P001J

SO20 MECHANICAL DATA

74ACT373

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 2.65 0.104

a1 0.10 0.20 0.004 0.007
a2 2.45 0.096

b 0.35 0.49 0.013 0.019

b1 0.23 0.32 0.009 0.012

C 0.50 0.020

c1 45° (typ.)

D 12.60 13.00 0.496 0.512

E 10.00 10.65 0.393 0.419
e 1.27 0.050

e3 11.43 0.450

F 7.40 7.60 0.291 0.299
L 0.50 1.27 0.19 0.050

M 0.75 0.029

S8°(max.)

mm inch

P013L

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74ACT373

Information furnished is believed to be accurateand reliable. However, SGS-THOMSONMicroelectronics assumes no responsability for the
consequencesof use of such information nor for any infringement of patents or otherrights of third parties which may resultsfrom its use. No
licenseis granted byimplication or otherwise underany patent orpatent rightsof SGS-THOMSON Microelectronics. Specifications mentioned
in this publicationare subject to change withoutnotice. This publication supersedes and replacesall information previously supplied.
SGS-THOMSONMicroelectronicsproducts are notauthorizedfor useascritical components in lifesupportdevices or systems withoutexpress
writtenapproval of SGS-THOMSONMicroelectonics.

 1997 SGS-THOMSONMicroelectronics- Printed in Italy - All Rights Reserved

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