Datasheet 74ACT323PC, 74ACT323CW Datasheet (Fairchild Semiconductor)

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June 1988 Revised October 1998

74ACT323 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins

74ACT323 8-Bit Universal Shift/Storage Register with

Synchronous Reset and Common I/O Pins

General Description

The ACT323 is an 8-bit universal shift/storage r egist er with 3-STATE outputs. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin count. Separate serial inputs and outputs are provided for Q

and Q7 to allow

easy cascading. Four operation modes are possible: hold (store), shift left, shift right and parallel load.

Features

■ ICC and IOZ reduced by 50%

■ Common parallel I/O for reduced pin count

■ Additional serial inputs and outputs for expansion

■ Four operating modes: shift left, shift right, load and

store

■ 3-ST ATE outputs for bus-oriented applications

■ Outputs source/sink 24 mA

■ TTL-compatible inputs

Ordering Code:

Device also available in Tape and Reel. Specify by appendin g s uf f ix let te r “X” to the ordering cod e.

Logic Symbols Connection Diagram

Pin Assignment

for DIP

Pin Descriptions

FACT is a tra demark of Fairchild Semico nductor Corporat ion.

Order Number Package Number Package Description

74ACT323PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Name Description

CP Clock Pulse Input DS

Serial Data Input for Right Shift

Serial Data Input for Left Shift

, S

Mode Select Inputs

Synchronous Reset Input

, OE23-STATE Output Enable Inputs

I/O

–I/O7Multiplexed Paralle l Data Inputs or

3-STATE Parallel Data Outputs

, Q

Serial Outputs

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74ACT323

Functional Description

The ACT323 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. The type of operation is determined by S

and S1 as shown

in the Mode Select Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inp uts in the paralle l load mode. Q

and Q

are also brought out on othe r pins for expansion in serial shifting of longer words.

A LOW signal on SR

overrides the Select inputs and allows

the flip-flops to be reset by the next rising edge of CP. All

other state changes are al so initi ated by the LOW-to-HIGH CP transition. Inputs can change when the clock is in either state provided only that th e recommend ed setup and h old times, relative to the rising edge of CP, are observed.

A HIGH signal on either O E

or OE2 disables the 3-STATE

buffers and puts the I/O pins in the high impedance state. In this condition the shift , load, hold and reset operati ons can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S

and S1 in preparation for a paral-

lel load operation.

Mode Select Table

H = HIGH Voltage Level L = LOW V oltage Lev el X = Immaterial



= LOW-to-HIGH Clock Transition

Inputs Response

S1S0CP

LXX



Synchronous Reset; Q0–Q7 = LOW

HHH



Parallel Load; I/On→Q

HLH Shift Right; DS0→Q0, Q0→Q1, etc. HH L



Shift Left; DS7→Q7, Q7→Q6, etc.

H L L X Hold

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74ACT323

Logic Diagram

Please note that this d iagram is provided only for the understanding of logic o perations and should no t b e us ed to estimate propagation delays.

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74ACT323

Absolute Maximum Ratings(Note 1)

Recommended Operating Conditions

Note 1: Absolute maximum ratings are thos e value s beyond wh ic h dam age

to the device may occur. The databook specif ications should b e met, wit hout exception, to ensure th at the system design is reliable over its power supply, temperature, and output/inp ut loading variables. Fairchild does no t recommend operat ion of FACT circuits outside databook specifications.

DC Electrical Characteristics

Note 2: All outputs loaded; thresholds on input associated w it h output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

Supply Voltage (VCC) −0.5V to +7.0V DC Input Diode Current (I

)

= −0.5V −20 mA

= VCC + 0.5V +20 mA

DC Input Voltage (V

) −0.5V to VCC + 0.5V

DC Output Diode Current (I

)

= −0.5V −20 mA

= VCC + 0.5V +20 mA

DC Output Voltage (V

) −0.5V to V

+ 0.5V

DC Output Source or

Sink Current (I

) ±50 mA

DC V

or Ground Current

Per Output Pin (I

or I

GND

) ±50 mA

Storage Temperature (T

STG

) −65°C to +150°C

Junction Temperature (T

)

PDIP 140°C

Supply Voltage (V

) 4.5V to 5.5V

Input Voltage (V

) 0V to V

Output Voltage (VO) 0V to V

Operating Temperature (TA) −40°C to +85°C Minimum Input Edge Rate (∆V/∆t)

from 0.8V to 2.0V

@ 4.5V, 5.5V 125 mV/ns

Symbol Parameter

TA = +25°C TA = −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

Minimum High Level 4.5 1.5 2.0 2.0 V V

OUT

= 0.1V

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V

Maximum Low Level 4.5 1.5 0.8 0.8 V V

OUT

= 0.1V

Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V

Minimum High Level 4.5 4.49 4.4 4.4 V I

OUT

= −50 µA

Output Voltage 5.5 5.49 5.4 5.4

VIN = V

or V

4.5 3.86 3.76 V IOH = −24 mA

5.5 4.86 4.76 IOH = −24 mA (Note 2)

Maximum Low Level 4.5 0.001 0.1 0.1 V I

OUT

= 50 µA

Output Voltage 5.5 0.001 0.1 0.1

VIN = V

or V

4.5 0.36 0.44 V IOL = −24 mA

5.5 0.36 0.44 IOL = −24 mA (Note 2)

Maximum Input 5.5 ±0.1 ±1.0 µAVI = VCC, GND Leakage Current

OZT

Maximum I/O 5.5 ±0.3 ±3.0 µAV

I/O

= VCC or GND

Leakage Current VIN = VIH, V

CCT

Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

OHD

Output Current (Note 3) 5.5 −75 mA V

OHD

= 3.85V Min

Maximum Quiescent 5.5 4.0 40.0 µAVIN = VCC or GND Supply Current

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74ACT323

AC Electrical Characteristics

Note 4: Voltage Range 5.0 is 5.0V ±0.5V

AC Operating Requirements

Note 5: Voltage Range 5.0 is 5.0V ±0.5V

Capacitance

TA = 25°CT

= −40°C to +85°C

Symbol Parameter (V)

CL = 50 pF CL = 50 pF

Units

(Note 4) Min Typ Max Min Max

max

Maximum Input Frequency 5.0 120 125 110 MHz

PLH

Propagation Delay 5.0 5.0 9.0 12.5 4.0 14.0 ns CP to Q0 or Q

PHL

Propagation Delay 5.0 5.0 9.0 13.5 4.5 15.0 ns CP to Q0 or Q

PLH

Propagation Delay 5.0 5.0 8.5 12.5 4.5 14.5 ns CP to I/O

PHL

Propagation Delay 5.0 6.0 10.0 14.5 5.0 16.0 ns CP to I/O

PZH

Output Enable Time 5.0 3.5 7.5 11.0 3.0 12.5 ns

PZL

Output Enable Time 5.0 3.5 7.5 11.5 3.0 13.0 ns

PHZ

Output Disable Time 5.0 4.0 8.5 12.5 3.0 13.5 ns

PLZ

Output Disable Time 5.0 3.0 8.0 11.5 2.5 12.5 ns

TA = 25°CT

= −40°C to +85°C

Symbol Parameter VCC

CL = 50 pF CL = 50 pF

Units

(V)

VCC = +5.0V VCC = +5.0V

(Note 5) Typ Guarante ed Minimum

Setup Time, HIGH or LOW 5.0 2.0 5.0 5.0 ns S0 or S1 to CP

Hold Time, HIGH or LOW 5.0 0 1.5 1.5 ns S0 or S1 to CP

Setup Time, HIGH or LOW 5.0 1.0 4.0 4.5 ns I/On, DS0, DS7 to CP

Hold Time, HIGH or LOW 5.0 0 1.0 1.0 ns I/On, DS0, DS 7 to CP

Setup Time, HIGH or LOW 5.0 1.0 2.5 2.5 ns SR to CP

Hold Time, HIGH or LOW 5.0 0 1.0 1.0 ns SR to CP

CP Pulse Width 5.0 2.0 4.0 4.5 ns HIGH or LOW

Symbol Parameter Typ Units Conditions

Input Capacitance 4.5 pF VCC = OPEN

Power Dissipation Capacitance 170 pF VCC = 5.0V

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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

74ACT323 8-Bit Univer sal Shift/Storage Register with Synchronous Reset and Common I/O Pins

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or system s ar e devices or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component in any c omponent of a life suppor t device or system whose failure to perform can be reasonably expected to cause the failure of the life suppor t device or system, or to affect its safety or effectiveness.

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Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N20A