Datasheet 74AC191SJX, 74AC191SJ, 74AC191SCX, 74AC191SC, 74AC191PC Datasheet (Fairchild Semiconductor)

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November 1988 Revised November 1999

74AC191 Up/Down Counter with Preset and Ripple Clock

General Description

The AC191 is a reversible modulo 16 binary counter. It features synchronous counting and asynchronous p resetting. The preset featur e allows the AC191 to be us ed in programmable divider s. The C ount Enabl e input , the Terminal Count output and the Rip ple Cloc k output m ake poss ible a variety of methods of implem enting m ultista ge coun ters. In the counting modes, state changes are i nitiated by the rising edge of the clock.

Features

■ ICC reduced by 50%

■ High speed—133 MHz typical count frequency

■ Synchronous counting

■ Asynchronous parallel load

■ Cascadable

■ Outputs source/sink 24 mA

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Pin Descriptions

FACT is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74AC191SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 74AC191SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC191MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC191PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Names Description

Count Enable Input

CP Clock Pulse Input P

0–P3

Parallel Data Inputs

Asynchronous Parallel Load Input

Up/Down Count Control Input

0–Q3

Flip-Flop Outputs

Ripple Clock Output

TC Terminal Count Output

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74AC191

RC T ruth T able

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial



= LOW-to-HIGH Transition



= Clock Pulse

Note 1: TC is generated internally

Functional Description

The AC191 is a synchronous up/down counter. The AC191 is organized as a 4-bit binary counter. It contains four edgetriggered flip-flops with internal gating and steering logic to provide individual preset, count-up and count-down operations.

Each circuit has an asynchronous parallel load capability permitting the counter to be preset to any desire d number. When the Parallel Load (PL

) input is LOW, information

present on the Parallel Load inputs (P

0–P3

) is loaded into

the counter and appears on the Q outputs . This operatio n overrides the counting functions, as indicated in the Mode Select Table.

A HIGH signal on the CE

input inhibits counting. When CE is LOW, internal state changes are initia ted synchro nously by the LOW-to-HIGH transition of the clock input. The direction of counti n g is d ete rmi n ed by th e U

/D input signal,

as indicated in the Mode Select Table. CE

and U/D can be changed with the clo ck in either state, provided only th at the recommended setup and hold times are observed.

Two types of outputs are pro vided as overflow/underflow indicators. The terminal count (TC) output is normally LOW. It goes HIGH when the circuits reach zero in the count down mode or 15 in the cou nt up mode . The TC output will then remain HIGH until a state change occurs, whether by counting o r presetting or u ntil U

/D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes.

The TC signal is also use d internally to enable the Ripple Clock (RC

) output. The RC output is normally HIGH. When

is LOW and TC is HIGH, RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multistage counters, as indi cated in Figure 1 a nd Figure 2. In Figure 1, each RC

output is used as the clock input for the next higher stage. T his configurati on is partic ularly advantageous when the clo ck so ur ce has a limited drive ca pa bil ity, since it drives only the first stage. To prevent counting in all stages it is only necessary to inhibit the first stage, since a HIGH signal on CE

inhibits the RC output pulse, as indi-

cated in the RC

Truth Table. A disadvantage of this config uration, in some applicat ions, is the timing skew between state changes in the f irst and last stages . This represents the cumulative delay of the clock as it ripples through the preceding stages.

A method of causing state changes to occur simultaneously in all stages is shown in Figur e 2. All clock inputs are driven in pa rallel and the RC

outputs propagate the carry/borrow signals in ripple fashion. In this configuration the LOW state duration of the clock must be long enough to allow the negative -go i ng edg e o f th e carry/borrow signal to

ripple through to the last stage before the clock goes HIGH. There is no such restriction on t he HIGH state duration of the clock, since the RC

output of any device goe s HIGH

shortly after its CP input goes HIGH. The configuration shown in Figure 3 avoids ripple delays

and their associat ed restrictio ns. The CE

input for a given stage is formed by combini ng the TC signals from all the preceding stages. Note that in order to inhibit countin g an enable signal must be in cluded in each carry gate. The simple inhibit scheme of Figure 1 and Figure 2 doesn't apply, because the TC output of a given stage is not affected by its own CE

Mode Select Table

State Diagram

Inputs Outputs

PL CE TC

(Note 1)

CP RC

H L H



H H X X H H X L X H L X X X H

Inputs Mode

CE U/D CP

H L L



Count Up

H L H



Count Down L X X X Preset (Asyn.) H H X X No Change (Hold)

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74AC191

Functional Description (continued)

FIGURE 1. N-Stage Counter Using Ripple Clock

FIGURE 2. Synchronous N-Stage Counter Using Ripple Carry/Borrow

FIGURE 3. Synchronous N-Stage Counter with Parallel Gated Carry/Borrow

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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74AC191

Absolute Maximum Ratings(Note 2) Recommended Operating

Conditions

Note 2: Absolute maximum ratings are those values beyond which dam-

age to the device may occu r. The databook specificati ons should be met , without exception, t o ensure that the system design is reliab le over its power supply, temperature, output/input loading variables. Fairchild does not recommend ope ration of FACT circuits outside d atabook specifications.

DC Electrical Characteristics

Note 3: All outputs loaded; thresholds on input assoc iat ed with output under tes t. Note 4: Maximum test duratio n 2. 0 ms, one output loaded at a time. Note 5: I

and ICC @ 3.0V are guaranteed to be less than or equa l to th e respective limit @ 5.5V VCC.

Supply Voltage (VCC) −0.5V to +7.0V DC Input Diode Current (I

)

= −0.5V −20 mA

= VCC + 0.5V +20 mA

DC Input Voltage (V

) −0.5V to VCC + 0.5V

DC Output Diode Current (I

)

= −0.5V −20 mA

= VCC + 0.5V +20 mA

DC Output Voltage (V

) −0.5V to VCC + 0.5V

DC Output Source

or Sink Current (I

) ±50 mA

DC V

or Ground Current

per Output Pin (I

or I

GND

) ±50 mA

Storage Temperature (T

STG

) −65°C to +150°C

Junction Temperature (T

)

PDIP 140°C

Supply Voltage (V

) 2.0V to 6.0V

Input Voltage (V

) 0V to V

Output Voltage (VO) 0V to V

Operating Temperature (TA) −40°C to +85°C Minimum Input Edge Rate (∆V/∆t)

from 30% to 70% of V

VCC @ 3.3V 4.5V, 5.5V 125 mV/ns

Symbol Parameter

TA = +25°C TA = −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

Minimum HIGH Level 3.0 1.5 2.1 2.1 V

OUT

= 0.1V

Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V

5.5 2.75 3.85 3.85

Maximum LOW Level 3.0 1.5 0.9 0.9 V

OUT

= 0.1V

Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V

5.5 2.75 1.65 1.65

Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 V I

OUT

= −50 µA

5.5 5.49 5.4 5.4

3.0 2.56 2.46 VIN = VIL or V

4.5 3.86 3.76 V IOH −12 mA

5.5 4.86 4.76 I

= −24 mA

.= −24 mA (Note 3)

Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 V I

OUT

= 50 µA

5.5 0.001 0.1 0.1

3.0 0.36 0.44 VIN = VIL or V

4.5 0.36 0.44 V IOL = 12 mA

5.5 0.36 0.44 IOL = 24 mA IOL = 24 mA (Note 3)

Maximum Input

5.5 ±0.1 ±1.0 µAVI = VCC, GND

(Note 5) Leakage Current I

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

OHD

Output Current (Note 4) 5.5 −75 mA V

OHD

= 3.85V Min

Maximum Quiescent

5.5 4.0 40.0 µA

VIN = V

(Note 5) Supply Current or GND

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74AC191

AC Electrical Characteristics

Note 6: Voltage Range 3.3 is 3.3V ± 0.3V

Voltage Range 5.0 is 5.0V ± 0.5V

Symbol Parameter

CL = 50 pF TA = −40°C to +85°C

Units

(V)

TA = +25°CC

= 50 pF

(Note 6) M in Typ Max Min Max

MAX

Maximum Count 3.3 70 105 65

MHz

Frequency 5.0 90 133 85

PLH

Propagation Delay 3.3 2.0 8.5 15.0 1.5 16.0

CP to Q

5.0 1.5 6.0 11.0 1.5 12.0

PHL

Propagation Delay 3.3 2.5 8.5 14.5 2.0 16.0

CP to Q

5.0 1.5 6.0 10.5 1.5 11.5

PLH

Propagation Delay 3.3 3.5 10.5 18.0 2.5 20.0

CP to TC 5.0 2.5 7.5 12.0 1.5 14.0

PHL

Propagation Delay 3.3 4.0 10.5 17.5 3.0 19.0

CP to TC 5.0 2.5 7.5 12.5 2.0 13.5

PLH

Propagation Delay 3.3 2.5 7.5 12.0 2.0 13.5

CP to RC

5.0 2.0 5.5 9.5 1.0 10.5

PHL

Propagation Delay 3.3 2.5 7.0 11.5 2.0 12.5

CP to RC

5.0 1.5 5.0 8.5 1.0 9.5

PLH

Propagation Delay 3.3 2.5 7.0 12.0 1.5 13.5

CE to RC 5.0 1.5 5.0 8.5 1.0 9.5

PHL

Propagation Delay 3.3 2.0 6.5 11.0 1.5 12.5

to RC 5.0 1.5 5.0 8.0 1.0 9.0

PLH

Propagation Delay 3.3 2.5 6.5 12.5 2.0 14.5

/D to RC 5.0 1.5 5.0 9.0 1.0 10.0

PHL

Propagation Delay 3.3 2.5 7.0 12.0 2.0 13.5

U /D to RC 5.0 1.5 5.0 8.5 1.0 10.0

PLH

Propagation Delay 3.3 2.0 7.0 11.5 1.5 13.5

/D to TC 5.0 1.5 5.0 8.5 1.0 9.5

PHL

Propagation Delay 3.3 2.0 6.5 11.0 1.5 12.5

/D to TC 5.0 1.5 5.0 8.5 1.0 9.5

PLH

Propagation Delay 3.3 2.5 8.0 13.5 2.0 15.5

Pn to Q

5.0 2.0 5.5 9.5 1.0 10.5

PHL

Propagation Delay 3.3 2.5 7.5 13.0 1.5 14.5

to Q

5.0 1.5 5.5 9.5 1.0 10.5

PLH

Propagation Delay 3.3 3.5 9.5 14.5 2.5 17.5

PL to Q

5.0 2.0 5.5 9.5 1.0 10.5

PHL

Propagation Delay 3.3 3.0 8.0 13.5 2.0 15.5

PL to Q

5.0 2.0 6.0 10.0 1.5 11.0

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74AC191

AC Operating Requirements

Note 7: Voltage Range 3.3 is 3.3V ± 0.3V

Voltage Range 5.0 is 5.0V ± 0.5V

Capacitance

TA = +25°CT

= −40°C to +85°C

Symbol Parameter (V)

C L = 50 pF CL = 50 pF

Units

(Note 7) Typ Guaranteed Minimum

Setup Time, HIGH or LOW 3.3 1.0 3.0 3.0

to PL 5.0 0.5 2.0 2.5

Hold Time, HIGH or LOW 3.3 −1.5 0.5 1.0

Pn to PL 5.0 −0.5 1.0 1.0

Setup Time, LOW 3.3 3.0 6.0 7.0

to CP 5.0 1.5 4.0 4.5

Hold Time, LOW 3.3 −4.0 −0.5 −0.5

to CP 5.0 −2.5 0 0

Setup Time, HIGH or LOW 3.3 4.0 8.0 9.0

U/D to CP 5.0 2.5 5.5 6.5

Hold Time, HIGH or LOW 3.3 −5.0 0 0

/D to CP 5.0 −3.0 0.5 0.5

PL Pulse Width, LOW 3.3 2.0 3.5 4.0

5.0 1.0 1.0 1.0

CP Pulse Width, LOW 3.3 2.0 3.5 4.0

5.0 2.0 3.0 4.0

rec

Recovery Time 3.3 −0.5 0 0

to CP 5.0 −1.0 0 0

Symbol P arameter Typ Units Conditions

Input Capacitance 4.5 pF VCC = OPEN

Power Dissipation Capacitance 75.0 pF VCC = 5.0V

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74AC191

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

Package Number M16A

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74AC191

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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74AC191

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Sm all Ou tline Pa ck age (TS SO P), JE DE C MO-153, 4.4mm Wide

Package Number MTC16

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74AC191 Up/Down Counter with Preset and Ripple Clock

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the user.

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