Datasheet 74AC175SJX, 74AC175SJ, 74AC175SCX, 74AC175SC, 74AC175PC Datasheet (Fairchild Semiconductor)

© 1999 Fairchild Semiconductor Corporation DS009936 www.fairchildsemi.com

November 1988
Revised November 1999

74AC175 • 74ACT175 Quad D-Type Flip-Flop

74AC175 • 74ACT175
Quad D-Type Flip-Flop

General Description

The AC/ACT175 is a hi g h-s pee d q uad D - type fli p- flop. The
device is useful for general flip-flop requirements where
clock and clear inputs are common. The information on the
D-type inputs is stored during the LOW-to-HIGH clock tran­sition. Both true and comple mented outputs of each flip­flop are provided. A Master Reset input resets all flip-flops,
independent of the Clock or D-type inputs, when LOW.

Features

■ ICC reduced by 50%

■ Edge-triggered D-type inputs

■ Buffered positive edge-triggered cl ock

■ Asynchronous common reset

■ True and complement output

■ Outputs source/sink 24 mA

■ ACT175 has TTL-compatible inputs

Ordering Code:

Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Pin Descriptions

FACT is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74AC175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74AC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC175PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74ACT175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT175PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Names Description

D

0–D3

Data Inputs
CP Clock Pulse Input
MR

Master Reset Input
Q

0–Q3

True Outputs
Q

0–Q3

Complement Outputs

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74AC175 • 74ACT175

Functional Description

The AC/ACT175 consists of four edge-triggered D-type flip­flops with individual D i nputs and Q and Q

outputs. The
Clock and Master Re set are common. The four f lip-flops
will store the state of their individual D inputs on th e LOW­to-HIGH clock (CP) transi tion, causing ind ividual Q and Q
outputs to follow. A LOW input on the Master Reset (MR)
will force all Q outputs LOW and Q

outputs HIGH indepen­dent of Clock or Data inputs. The AC/ACT175 is useful for
general logic applic ations where a common Master R eset
and Clock are acceptable.

Tr uth Table

H = HIGH Voltage Level
L = LOW Voltage Level
t

n

= Bit Time before Clock Pulse

t

n+1

= Bit Time after Clock Pulse

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Inputs Outputs

@ t

n

, MR = H@ t

n+1

D

n

Q

n

Q

n

LLH

HHL

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74AC175 • 74ACT175

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute max imum ratings are those values beyond w hich damage

to the device may occu r. The databook spe cificatio ns shou ld be met, wit h­out exception, to ensure that the system de sign is relia ble over its p ower
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specif ic at ions

DC Electrical Characteristics for AC

Note 2: All outputs loaded; thres holds on input associate d w it h output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: I

IN

and ICC @ 3.0V are guaranteed to be less than or equa l t o th e respective limit @ 5.5V VCC.

Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I

IK

)

V

I

= −0.5V −20 mA

V

I

= VCC + 0.5V +20 mA

DC Input Voltage (V

I

) −0.5V to VCC + 0.5V

DC Output Diode Current (I

OK

)

V

O

= −0.5V −20 mA

V

O

= VCC + 0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to VCC + 0.5V

DC Output S ource

or Sink Current (I

O

) ± 50 mA

DC V

CC

or Ground Current

per Output Pin (I

CC

or I

GND

) ± 50 mA

Storage Temperature (T

STG

) −65°C to +150°C

Junction Temperature (T

J

)

PDIP 140°C

Supply Voltage (V

CC

)
AC 2.0V to 6.0V
ACT 4.5V to 5.5V

Input Voltage (V

I

)0V to V

CC

Output Voltage (VO)0V to V

CC

Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t)

AC Devices
V

IN

from 30% to 70% of V

CC

VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate (∆V/∆t)

ACT Devices
V

IN

from 0.8V to 2.0V

V

CC

@ 4.5V, 5.5V 125 mV/ns

Symbol Parameter

V

CC

TA = +25°CT

A

= −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

V

IH

Minimum HIGH Level 3.0 1.5 2.1 2.1 V

OUT

= 0.1V

Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V

5.5 2.75 3.85 3.85

V

IL

Maximum LOW Level 3.0 1.5 0.9 0.9 V

OUT

= 0.1V

Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V

5.5 2.75 1.65 1.65

V

OH

Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V I

OUT

= −50 µA

5.5 5.49 5.4 5.4
VIN = VIL or V

IH

3.0 2.56 2.46 IOH = −12 mA

4.5 3.86 3.76 V I

OH

= −24 mA

5.5 4.86 4.76 I

OH

= −24 mA (Note 2)

V

OL

Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V I

OUT

= 50 µA

5.5 0.001 0.1 0.1
VIN = VIL or V

IH

3.0 0.36 0.44 IOL = 12 mA

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 2)

I

IN

(Note 4)

Maximum Input
Leakage Current

5.5 ±0.1 ± 1.0 µAVI = VCC, GND

I

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

I

OHD

Output Current (Note 3) 5.5 −75 mA V

OHD

= 3.85V Min

I

CC

(Note 4)

Maximum Quiescent
Supply Current

5.5 4.0 40.0 µAVIN = VCC or GND

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74AC175 • 74ACT175

DC Electrical Characteristics for ACT

Note 5: All outputs loaded; thresholds on input assoc iat ed with output under tes t.
Note 6: Maximum test duratio n 2. 0 ms, one output loaded at a time.

AC Electrical Characteristics for AC

Note 7: Voltage Range 3.3 is 3.3V ± 0.3V

Voltage Range 5.0 is 5.0V ± 0.5V

Symbol Parameter

V

CC

TA = +25°CTA = −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

V

IH

Minimum HIGH Level 4.5 1.5 2.0 2.0

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V

V

IL

Maximum LOW Level 4.5 1.5 0.8 0.8

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 0.8 0.8 or V

CC

− 0.1V

V

OH

Minimum HIGH Level 4.5 4.49 4.4 4.4

VI

OUT

= −50 µA

Output Voltage 5.5 5.49 5.4 5.4

VIN = VIL or V

IH

4.5 3.86 3.76 V IOH = −24 mA

5.5 4.86 4.76 I

OH

= −24 mA (Note 5)

V

OL

Maximum LOW Level 4.5 0.001 0.1 0.1

VI

OUT

= 50 µA

Output Voltage 5.5 0.001 0.1 0.1

VIN = VIL or V

IH

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 5)

I

IN

Maximum Input Leakage Current 5.5 ±0.1 ± 1.0 µAVI = VCC, GND

I

CCT

Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V

I

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

I

OHD

Output Current(Note 6) 5.5 −75 mA V

OHD

= 3.85V Min

I

CC

Maximum Quiescent

5.5 4.0 40.0 µA

VIN = V

CC

Supply Current or GND

V

CC

TA = +25°CT

A

= −40°C to +85°C

Symbol Parameter (V)

CL = 50 pF CL = 50 pF

Units

(Note 7) Min Typ Max Min Max

f

MAX

Maximum Clock 3.3 149 214 139

MHz

Frequency 5.0 187 244 187

t

PLH

Propagation Delay 3.3 2.0 9.5 12.0 2.0 13.5

ns

CP to Qn or Q

n

5.0 1.5 7.0 9.0 1.0 9.5

t

PHL

Propagation Delay 3.3 2.5 8.5 13.0 2.0 14.5

ns

CP to Qn or Q

n

5.0 1.5 6.0 9.5 1.5 10.5

t

PLH

Propagation Delay 3.3 3.0 7.5 12.5 2.5 13.5

ns

MR to Q

n

5.0 2.0 5.5 9.0 1.5 10.0

t

PHL

Propagation Delay 3.3 3.0 8.5 11.0 2.5 12.5

ns

MR to Q

n

5.0 2.0 6.0 8.5 1.5 9.0

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74AC175 • 74ACT175

AC Operating Requirements for AC

Note 8: Voltage Range 3.3 is 3.3V ± 0.3V

Voltage Range 5.0 is 5.0V ± 0.5V

AC Electrical Characteristics for ACT

Note 9: Voltage Range 5.0 is 5.0V ± 0.5V

AC Operating Requirements for ACT

Note 10: Voltage Ran ge 5.0 is 5.0V ± 0.5V

Capacitance

V

CC

TA = +25°CT

A

= −40°C to +85°C

Symbol Parameter (V)

C

L

= 50 pF CL = 50 pF

Units

(Note 8) Typ Guaranteed Minimum

t

S

Setup Time, HIGH or LOW 3.3 2.0 4.5 4.5

ns

D

n

to CP 5.0 1.0 3.0 3.0

t

H

Hold Time, HIGH or LOW 3.3 1.0 1.0 1.0

ns

D

n

to CP 5.0 1.0 1.0 1.0

t

W

CP Pulse Width 3.3 2.5 4.5 4.5

ns

HIGH or LOW 5.0 2.0 3.5 3.5

t

W

MR Pulse Width, LOW

3.3 2.5 4.5 5.0
ns

5.0 2.0 3.5 3.5

t

REC

Recovery Time 3.3 −2.0 0 0

ns

MR to CP

5.0 −1.0 0 0

V

CC

TA = +25°CT

A

= −40°C to +85°C

Symbol Parameter (V)

CL = 50 pF CL = 50 pF

Units

(Note 9) Min Typ Max Min Max

f

MAX

Maximum Clock

5.0 175 236 145 MHz

Frequency

t

PLH

Propagation Delay

5.0 2.0 6.0 10.0 1.5 11.0 ns

CP to Qn or Q

n

t

PHL

Propagation Delay

5.0 2.0 7.0 11.0 1.5 12.0 ns

CP to Qn or Q

n

t

PLH

Propagation Delay

5.0 2.0 6.0 9.5 1.5 10.5 ns

MR to Q

n

t

PHL

Propagation Delay

5.0 2.0 5.5 9.5 1.5 10.5 ns

MR

to Q

n

V

CC

TA = +25°CT

A

= −40°C to +85°C

Symbol Parameter (V)

CL = 50 pF CL = 50 pF

Units

(Note 10) Typ Guaranteed Minimum

t

S

(H) Setup Time 5.0 3.0 2.0 2.0

ns

tS (L) Dn to CP 3.0 2.5 2.5
t

H

Hold Time, HIGH or LOW

5.001.0 1.0 ns

Dn to CP

t

W

CP Pulse Width

5.0 4.0 3.0 3.5 ns

HIGH or LOW

t

W

MR Pulse Width, LOW

5.0 4.0 3.0 4.0 ns

t

rec

Recovery Time, MR to CP

5.0 0 0 0 ns

Symbol Parameter Typ Units Conditions

C

IN

Input Capacitance 4.5 pF VCC = OPEN

C

PD

Power Dissipation Capacitance 45.0 pF VCC = 5.0V

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74AC175 • 74ACT175

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body

Package Number M16A

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74AC175 • 74ACT175

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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74AC175 • 74ACT175

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC16

9 www.fairchildsemi.com

74AC175 • 74ACT175 Quad D-Type Flip-Flop

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.3 00” Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the labe l ing, can be re a­sonably expected to result in a significant injury to the
user.

2. A critical compo nent in any com ponen t of a life s upp ort
device or system whose failure to perform can be rea­sonably expected to cause the failure of the l ife support
device or system, or to affect its safety or effectiveness.

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