Datasheet 74abt899 DATASHEETS (Philips)

INTEGRATED CIRCUITS

74ABT899

9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

Product specification Supersedes data of 1993 Oct 04 IC23 Data Handbook

 

1998 Jan 16

Philips Semiconductors Product specification

9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

FEA TURES

•Symmetrical (A and B bus functions are identical)

•Selectable generate parity or ”feed-through” parity for A-to-B and

B-to-A directions

•Independent transparent latches for A-to-B and B-to-A directions

•Selectable ODD/EVEN parity

•Continuously checks parity of both A bus and B bus latches as

and ERRB

ERRA

•Ability to simultaneously generate and check parity

•Can simultaneously read/latch A and B bus data

•Output capability: +64 mA/–32mA

•Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

•Power up 3-State

•Power-up reset

•Live insertion/extraction permitted

DESCRIPTION

The 74ABT899 is a 9-bit to 9-bit parity transceiver with separate transparent latches for the A bus and B bus. Either bus can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input.

Parity error checking of the A and B bus latches is continuously provided with ERRA

The 74ABT899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN signal output pins for checking parity.

FUNCTIONAL DESCRIPTION

The 74ABT899 has three principal modes of operation which are outlined below. All modes apply to both the A-to-B and B-to-A directions.

Transparent latch, Generate parity, Check A and B bus parity:

Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are High and the Mode Select (SEL A0-A7 and B0-B7 can be checked and monitored by ERRA ERRB

74ABT899

and ERRB, even with both buses in 3-State.

parity, and separate error

) is Low, the parity generated from

and

. (Fault detection on both input and output buses.)

QUICK REFERENCE DATA

SYMBOL PARAMETER

t

PLH

t

PHL

t

PLH

t

PHL

C C I

CCZ

I/O

Propagation delay An to Bn or Bn to An

Propagation delay An to ERRA

Input capacitance VI = 0V or V

IN

Output capacitance Outputs disabled; VO = 0V or V Total supply current Outputs disabled; VCC =5.5V 50 µA

Transparent latch, Feed-through parity, Check A and B bus parity:

Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is High. Parity is still generated and checked as ERRA and ERRB and can be used as an interrupt to signal a data/parity bit error to the CPU.

Latched input, Generate/Feed-through parity, Check A (and B) bus parity:

Independent latch enables (LEA and LEB) allow other permutations of:

•Transparent latch / 1 bus latched / both buses latched

•Feed-through parity / generate parity

•Check in bus parity / check out bus parity / check in and out bus

parity

CONDITIONS

T

= 25°C; GND = 0V

amb

CL = 50pF; VCC = 5V 2.9 ns

CL = 50pF; VCC = 5V 6.1 ns

CC

TYPICAL UNIT

4 pF 7 pF

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

28-Pin Plastic PLCC –40°C to +85°C 74ABT899 A 74ABT899 A SOT261-3 28-Pin Plasti c SOP –40°C to +85°C 74ABT899 D 74ABT899 D SOT136-1 28-Pin Plasti c SSOP –40°C to +85°C 74ABT899 DB 74ABT899 DB SOT341-1

1998 Jan 16 853-1623 18864

2

Philips Semiconductors Product specification

9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

PIN CONFIGURATION

ODD/EVEN

1 227

ERRA OEB

3

LEA

4

A0

5

A1

6

A2

7

A3

APAR

TOP VIEW

8

A4

9

A5

10

A6

11

A7 BPAR

12 17 13 16OEA 14 15GND

28

V

B0

26 25

B1

24

B2

23

B3

22

B4

21

B5

20

B6

19

B7

18

LEB SEL ERRB

SA00289

CC

PLCC PIN CONFIGURATION

B1 B2 B3 B4 B5 B6 B7 25

24 23 22 21 20 19

B0

26

OEB

27 28

V

CC

ODD/

1

EVEN

2

ERRA

3

LEA

4

A0

67891011

5

A1 A2 A3 A4 A5 A6 A7

74ABT899

18

BPAR

17

LEB

16

SEL

15

ERRB 14 GND 13

OEA 12

APAR

SA00291

PIN DESCRIPTION

SYMBOL

A0 - A7

B0 - B7

APAR 12 A bus parity 3-State input BPAR 18 B bus parity 3-State input ODD/

EVEN

OEA, OEB 13, 27

SEL 16 Mode select input (Low for generate)

LEA, LEB 3, 17 Latch enable inputs (transparent High)

ERRA,

ERRB

GND 14 Ground (0V)

V

CC

NUMBER

NAME AND FUNCTION

4, 5, 6, 7,

8, 9, 10,

Latched A bus 3-State inputs/outputs

11

19, 20, 21, 22, 23, 24,

Latched B bus 3-State inputs/outputs

25, 26

Parity select input (Low for EVEN

1

parity) Output enable inputs (gate A to B,

B to A)

2, 15 Error signal outputs (active-Low)

28 Positive supply voltage

LOGIC SYMBOL

A0 A1 A2 A3 A4 A5 A6 A7

3 17 16

1 27 13

B0 B1 B2 B3 B4 B5 B6 B7

26 25 24 23 22 21 20 19

4567 891011

LEA LEB SEL ODD/EVEN OEB OEA

ERRA ERRB

12

APAR

2

15

BPAR

18

SA00290

1998 Jan 16

3

Philips Semiconductors Product specification

9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

9–bit

Transparent

Latch

3

LEA

APAR

4

A0

5

A1

6

A2

7

A3

8

A4

9

A5

10

A6

11

A7

12

LE

Parity

Generator

9–bit

Output

Buffer

1

mux

0

9–bit

Output

Buffer

9–bit

Transparent

Latch

OE

74ABT899

27

OEB

26

B0

25

B1

24

B2

23

B3

22

B4

21

B5

20

B6

19

B7

18

BPAR

13

OEA

SEL

ODD/

EVEN

16

1

OE

mux

1

0

Parity

Generator

LE

FUNCTION TABLE

INPUTS OPERATING MODE

OEB OEA SEL LEA LEB

H H X X X 3-State A bus and B bus (input A & B simultaneously) H L L L H B → A, transparent B latch, generate parity from B0 - B7, check B bus parity H L L H H B → A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity H L L X L B → A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity H L H X H B → A, transparent B latch, parity feed-through, check B bus parity H L H H H B → A, transparent A & B latch, parity feed-through, check A & B bus parity

L H L H X A → B, transparent A latch, generate parity from A0 - A7, check A bus parity L H L H H A → B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity L H L L X A → B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity L H H H L A → B, transparent A latch, parity feed-through, check A bus parity L H H H H A → B, transparent A & B latch, parity feed-through, check A & B bus parity L L X X X Output to A bus and B bus (NOT ALLOWED)

H = High voltage level L = Low voltage level X = Don’t care

17

2

15

LEB

ERRA

ERRB

SA00292

1998 Jan 16

4

Philips Semiconductors Product specification

9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

PARITY AND ERROR FUNCTION TABLE

INPUTS OUTPUTS

SEL ODD/EVEN

H H H

H H L

H L H

H L L

L H H

L H L

L L H

L L L

H = High voltage level L = Low voltage level t = Transmit–if the data path is from A→B then ERRt r = Receive–if the data path is from A→B then ERRr is ERRB * Blocked if latch is not transparent

xPAR

(A or B)

Σ of High

Inputs

Even

Odd

Even

Odd

Even

Odd

Even

Odd

Even

Odd

Even

Odd

Even

Odd

Even

Odd

xPAR

(B or A)

H H

L L

H H

L L

H

L

H

L L

H

L

H

is ERRA

ERRt ERRr*

H

L L

H

L

H H

L

H

L L

H

L

H H

L

H

L Odd L

H

L

H Even H

L

H H Odd

H H

H H Even

H H

Mode

74ABT899

PARITY MODES

Feed-through/check parity

Generate parity

ABSOLUTE MAXIMUM RATINGS

SYMBOL

V

I

V

I

OK

V

OUT

I

OUT

T

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 1505C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

DC supply voltage –0.5 to +7.0 V

CC

DC input diode current VI < 0 –18 mA

IK

DC input voltage

I

DC output diode current VO < 0 –50 mA DC output voltage DC output current output in Low state 128 mA Storage temperature range –65 to 150 °C

stg

PARAMETER CONDITIONS RATING UNIT

3

1, 2

–1.2 to +7.0 V

output in Off or High state –0.5 to +5.5 V

1998 Jan 16

5

Philips Semiconductors Product specification

9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT

Min Max

V

V V V I

OH

I

OL

∆t/∆v Input transition rise or fall rate 0 5 ns/V T

amb

DC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER TEST CONDITIONS T

V

OH

V

OL

V

RST

I

OFF

IPU/I

IIH + I

IIL + I

I

CEX

I

O

I

CCH

I

CCL

I

CCZ

∆I

CC

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

4. This parameter is valid for any V transition time of up to 100µsec is permitted.

DC supply voltage 4.5 5.5 V

CC

Input voltage 0 V

I

High-level input voltage 2.0 V

IH

Low-level Input voltage 0.8 V

IL

High-level output current –32 mA Low-level output current 64 mA

Operating free-air temperature range –40 +85 °C

LIMITS

= +25°C

amb

Min Typ Max Min Max

Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V

IK

VCC = 4.5V; IOH = –3mA; VI = VIL or V

High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or V

VCC = 4.5V; IOH = –32mA; VI = VIL or V Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V Power-up output low

3

voltage Input leakage Control pins VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA

I

VCC = 5.5V; IO = 1mA; VI = GND or V

IH

CC

2.5 3.5 2.5 V

3.0 4.0 3.0 V

2.0 2.6 2.0 V

0.42 0.55 0.55 V

0.13 0.55 0.55 V

current Data pins VCC = 5.5V; VI = GND or 5.5V ±5 ±100 ±100 µA Power-off leakage current VCC = 0.0V; VO or V Power-up/down 3-State

PD

output current 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V

OZH

3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V

OZL

4

VCC = 2.1V; VO = 0.5V; VI= GND or VCC;

V

= Don’t care

OE

Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V Output current

1

VCC = 5.5V; VO = 2.5V –50 –80 –180 –50 –180 mA

VCC = 5.5V; Outputs High, VI = GND or V Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or V

VCC = 5.5V; Outputs 3-State;

VI = GND or V Additional supply current per

input pin

2

CC

VCC = 5.5V; one input at 3.4V,

other inputs at VCC or GND

between 0V and 2.1V , with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10%, a

≤

4.5V ±5.0 ±100 ±100 µA

I

±5.0 ±50 ±50 µA

IH

CC

5.0 50 50 µA

–5.0 –50 –50 µA

5.0 50 50 µA

50 250 250 µA 28 34 34 mA

50 250 250 µA

0.3 1.5 1.5 mA

74ABT899

CC

T

= –40°C

amb

to +85°C

V

UNIT

1998 Jan 16

6

Philips Semiconductors Product specification

9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

AC CHARACTERISTICS

GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORM

t t

t

PLH PHL

PZH PZL

PHZ PLZ

Propagation delay An to Bn or Bn to An

Propagation delay An to BPAR or Bn to APAR

Propagation delay An to ERRA or Bn to ERRB

Propagation delay APAR to BPAR or BPAR to APAR

Propagation delay APAR to ERRA or BPAR to ERRB

Propagation delay ODD/EVEN to APAR or BPAR

Propagation delay ODD/EVEN to ERRA or ERRB

Propagation delay SEL

to APAR or BPAR

Propagation delay SEL to ERRA or ERRB

Propagation delay LEA to Bn or LEB to An

Propagation delay LEA to BPAR or LEB to APAR

Propagation delay LEA to ERRA or LEB to ERRB

Output enable time OEA to An, APAR or OEB to Bn, BPAR

Output disable time OEA to An, APAR or OEB to Bn, BPAR

1

2

3

1

6

5

4

8

9

7

11, 12

74ABT899

LIMITS

T

= +25oC

amb

VCC = +5.0V

CL = 50pF RL = 500Ω

Min Typ Max Min Max

1.0

3.0

2.5

2.8

2.0

1.3

1.5

2.6

2.5

2.3

2.6

1.3

1.4

3.7

5.1

1.0

2.0

1.7

2.0

1.0

0.5

3.2

2.7

6.0

6.4

6.0

6.7

4.0

3.2

4.2

4.0

5.5

5.3

5.4

5.7

4.1

6.8

8.3

3.2

3.1

6.8

6.3

7.1

3.0

3.4

3.0

4.5

4.1

7.5

7.9

8.0

8.5

5.2

4.4

5.4

6.8

6.7

6.8

7.2

5.2

5.3

8.3

9.7

4.4

4.5

8.3

7.9

8.3

9.2

4.3

4.8

4.7

4.2

T

= –40 to +85oC

amb

VCC = +5.0V ±10%

CL = 50pF RL = 500Ω

1.0

3.0

2.5

2.8

2.0

1.3

1.5

2.6

2.5

2.3

2.6

1.3

1.4

3.7

5.1

1.0

2.0

1.7

2.0

1.0

0.5

4.9

4.6

9.0

8.8

9.1

9.3

5.7

5.0

6.0

6.1

8.1

7.8

7.9

8.4

6.0

5.9

9.8

11.0

4.9

5.0

9.7

9.0

9.6

10.3

5.1

5.4

5.5

4.7

UNIT

ns

AC SETUP REQUIREMENTS

GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORM

ts(H) ts(L)

th(H) th(L)

tw(H)

1998 Jan 16

Setup time, High or Low An, APAR to LEA or Bn, BPAR to LEB

Hold time, High or Low An, APAR to LEA or Bn, BPAR to LEB

Pulse width, High LEA or LEB

10

10 3.0 1.9 3.0 ns

LIMITS

T

= +25oC

amb

VCC = +5.0V

CL = 50pF R

= 500Ω

L

Min Typ Max Min Max

2.0

1.5

1.0

0.4

0.0

–0.2

7

T

= –40 to +85oC

amb

VCC = +5.0V ±10%

CL = 50pF R

= 500Ω

L

2.0

1.5

1.0

UNIT

ns

Philips Semiconductors Product specification

9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

AC WAVEFORMS

VM = 1.5V, VIN = GND to 3.0V

1

SEL

An, APAR

(Bn, BPAR)

Bn, BPAR

(An, APAR)

Waveform 1. Propagation Delay, An to Bn, Bn to An, APAR to BPAR, BPAR to APAR

SEL

ODD/EVEN

V

M

t

PLH

0

V

M

t

PHL

V

M

V

M

74ABT899

INPUT

OUTPUT

SA00293

1

LEA

(LEB)

An

(Bn)

BPAR

(APAR)

ODD PARITY

V

M

t

PHL

EVEN PARITY ODD PARITY

V

M

V

M

t

PLH

V

M

NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1

Waveform 2. Propagation Delay, An to BPAR or Bn to APAR

ODD/EVEN

0

APAR

(BPAR)

LEA

(LEB)

(Bn)

An

0

1

ODD PARITY

V

M

EVEN PARITY ODD PARITY

V

M

INPUT

OUTPUT

SA00294

INPUT

1998 Jan 16

ERRA

(ERRB)

t

PLH

V

M

t

PHL

V

M

NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1

Waveform 3. Propagation Delay, An to ERRA or Bn to ERRB

8

OUTPUT

SA00295

Philips Semiconductors Product specification

9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

1

APAR

(BPAR)

An

(Bn)

ODD/EVEN

ERRA

(ERRB)

V

M

t

PLH

V

M

NOTE: Only even parity mode is shown, odd parity mode would cause inverted output

Waveform 4. Propagation Delay, ODD/EVEN to ERRA or ODD/EVEN to ERRB

M

EVEN PARITY

t

PHL

V

M

74ABT899

INPUT

OUTPUT

SA00296

SEL

0

APAR

(BPAR)

ODD/EVEN

(APAR)

(Bn)

BPAR

0

An

t

PLH

V

M

V

M

V

M

EVEN PARITY

t

PHL

V

M

NOTE: Only even parity mode is shown, odd parity mode would cause inverted output

Waveform 5. Propagation Delay, ODD/EVEN to APAR or ODD/EVEN to BPAR

INPUT

OUTPUT

SA00297

1998 Jan 16

9

Philips Semiconductors Product specification

9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

ODD/EVEN

0

An

(Bn)

APAR

(BPAR)

ERRA

(ERRB)

V

M

t

PLH

V

M

V

M

NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output and odd parity mode would be with ODD/EVEN = 1

Waveform 6. Propagation Delay, APAR to ERRA or BPAR to ERRB

1

ODD/EVEN

EVEN PARITY

t

PHL

V

M

74ABT899

INPUT

OUTPUT

SA00298

APAR

(BPAR)

(ERRB)

(Bn)

LEA

(LEB)

ERRA

An

0

EVEN PARITY

ODD PARITY EVEN PARITY

V

M

t

PLH

V

M

V

M

t

PHL

V

M

NOTE: Only odd parity mode is shown. Even parity mode would be with ODD/EVEN = o

Waveform 7. Propagation Delay, LEA to ERRA or LEB to ERRB

INPUT

OUTPUT

SA00299

1998 Jan 16

10

Philips Semiconductors Product specification

9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

1

ODD/EVEN

APAR

(BPAR)

(APAR)

NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output and odd parity mode would be with ODD/EVEN = 1

0

An

(Bn)

SEL

BPAR

t

PLH

V

M

V

M

V

M

EVEN PARITY

t

PHL

V

M

Waveform 8. Propagation Delay, SEL to BPAR or SEL to APAR

74ABT899

INPUT

OUTPUT

SA00300

1

SEL

APAR, An]

(BPAR, Bn)

LEA

(LEB)

Bn, BPAR

(An, APAR)

V

M

t

PLH

V

M

V

M

t

PHL

V

M

SA00301

Waveform 9. Propagation Delay, LEA to BPAR or LEB to APAR, LEA to Bn or LEB to An

APAR, BPAR,

An, Bn

LEA, LEB

The shaded areas indicate when the input is permitted to change for predictable output performance.

ts(H)

V

M

V

M

t

(H)

h

V

M

V

M

V

M

(L)

t

s

tw(H)

V

M

t

(L)

h

V

M

SA00302

Waveform 10. Data Setup and Hold Times, Pulse W idth High

INPUT

OUTPUT

1998 Jan 16

11

Philips Semiconductors Product specification

9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

OEA, OEB

An, APAR,

Bn, BPAR

Waveform 11. 3-State Output Enable Time to High Level and Output Disable Time from High Level

OEA, OEB

An, APAR,

Bn, BPAR

Waveform 12. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level

V

M

t

PZH

V

M

V

M

t

PZL

V

M

74ABT899

V

M

t

PHZ

V

–0.3V

OH

SA00303

M

t

PLZ

VOL +0.3V

SA00304

0V

TEST CIRCUIT AND WAVEFORM

From Output Under Test

C

= 50 pF

L

DEFINITIONS

= Load capacitance includes jig and probe capacitance;

C

L

see AC CHARACTERISTICS for value.

500 Ω

Load Circuit

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

open

7 V

open

7 V

S1

Open

GND

SA00012

1998 Jan 16

12

Philips Semiconductors Product specification

9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

PLCC28: plastic leaded chip carrer; 28 leads; pedestal SOT261-3

74ABT899

1998 Jan 16

13

Philips Semiconductors Product specification

9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

SO28: plastic small outline package; 28 leads; body width 7.5mm SOT136-1

74ABT899

1998 Jan 16

14

Philips Semiconductors Product specification

9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3mm SOT341-1

74ABT899

1998 Jan 16

15

Philips Semiconductors Product specification

9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

74ABT899

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 05-96 Document order number: 9397-750-03478

 

yyyy mmm dd

16