Datasheet 74ABT853PW, 74ABT853N, 74ABT853DB, 74ABT853D Datasheet (Philips)

Philips Semiconductors Product specification

8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)

FEA TURES

•Low static and dynamic power dissipation with high speed and

high output drive

•Open-collector ERROR output

•Output capability: +64mA/–32mA

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

•Power-up 3-State

•Live insertion/extraction permitted

DESCRIPTION

The 74ABT853 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.

QUICK REFERENCE DATA

SYMBOL PARAMETER

t

PLH

t

PHL

t

PLH

t

PHL

C
C
I

CCZ

IN

I/O

Propagation delay
An to Bn or Bn to An

Propagation delay
An to PARITY

Input capacitance VI = 0V or V
I/O capacitance Outputs disabled; VO = 0V or V
Total supply current Outputs disabled; VCC =5.5V 50 µA

74ABT853

The 74ABT853 is an octal transceiver with a parity
generator/checker and is intended for bus–oriented applications.

When Output Enable A (OEA
high impedance state. Output Enable B (OEB
outputs in the same way.

The parity generator creates an odd parity output (PARITY) when
OEB

is Low. When OEA is Low, the parity of the B port, including
the PARITY input, is checked for odd parity. When an error is
detected, the error data is sent to the input of a latch. The error data
can then be passed, stored, cleared, or sampled depending on the
ENABLE

If both OEA

and CLEAR control signals.

and OEB are Low, data will flow from the A bus to the B
bus and the part is forced into an error condition which creates an
inverted PARITY output. This error condition can be used by the
designer for system diagnostics.

CONDITIONS
= 25°C; GND = 0V

T

amb

CL = 50pF; VCC = 5V 3.4 ns

CL = 50pF; VCC = 5V 7.4 ns

CC

) is High, it will place the A outputs in a

) controls the B

TYPICAL UNIT

4 pF

CC

7 pF

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

24-Pin Plastic DIP –40°C to +85°C 74ABT853 N 74ABT853 N SOT222-1
24-Pin plastic SO –40°C to +85°C 74ABT853 D 74ABT853 D SOT137-1
24-Pin Plastic SSOP Type II –40°C to +85°C 74ABT853 DB 74ABT853 DB SOT340-1
24-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT853 PW 74ABT853PW DH SOT355-1

PIN CONFIGURA TION

1

OEA

2

A0

3

A1

4

A2

5

A3

6

A4
A5

7
8

A6

9

A7

10

ERROR

11

CLEAR

GND

24
23
22
21
20

19
18
17
16
15
14
1312

V

CC

B0
B1
B2
B3
B4
B5

B6
B7
PARITY
OEB
ENABLE

LOGIC SYMBOL

14

1

11

23456789

A0 A1 A2 A3 A4 A5 A6 A7

OEB
OEA
CLEAR
ENABLE13

B0 B1 B2 B3

23 22 21 20 19 18 17 16

PARITY

ERROR

B4 B5 B6 B7

15

10

TOP VIEW

1995 Sep 06 853-1672 15702

SA00262

1

SA00263

Philips Semiconductors Product specification

8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)

PIN DESCRIPTION

SYMBOL PIN NUMBER NAME AND FUNCTION

A0 – A7 2, 3, 4, 5, 6, 7, 8, 9 A port 3–State inputs/outputs
B0 – B7 23, 22, 21, 20, 19, 18, 17, 16 B port 3–State inputs/outputs

OEA 1 Enables the A outputs when Low

OEB 14 Enables the B outputs when Low
PARITY 15 Parity output/input
ERROR 10 Error output (open collector)

CLEAR 11 Clears the error flag register when Low

ENABLE 13 Enable input (active-Low)

GND 12 Ground (0V)

V

CC

FUNCTION TABLE

MODE OEB OEA

A data to B bus and generate odd parity output L H
B data to A bus and check for parity error

A bus and B bus disabled
A data to B bus and generate inverted parity output L L

NOTES:

1. Error checking is detailed in the Error Flag Function Table below.

2. When ENABLE

2

is Low, ERROR is Low if the sum of A inputs is even or ERROR is High if the sum of A inputs is odd.

1

24 Positive supply voltage

H L (output) X Bn (input) (input)
H H X X Z Z Z

74ABT853

INPUTS OUTPUTS

An

Σ OF HIGHS

Odd

Even

Odd

Even

Bn + PARITY

Σ OF HIGHS

(output) (input) An

(output) (input) An

An Bn PARITY

L

H

H

L

ERROR FLAG FUNCTION TABLE

MODE ENABLE CLEAR

Pass L L

Sample L H

Clear H L X X X H
Store H H X X

H = High voltage level steady state
L = Low voltage level steady state
X = Don’t care
Z = High impedance ”off” state

1995 Sep 06

INPUTS INTERNAL NODE OUTPUT

Bn + PARITY

Σ OF HIGHS

Odd

Even

Odd

Even

X

2

POINT ”P”

H
L

H
L
X

PRE–STATE

ERROR

X
H

X
L

L
H

n–1

ERROR

OUTPUT

H

L

H

L
L

L

H

Philips Semiconductors Product specification

8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)

LOGIC DIAGRAM

8 8

A0 – A7

8

OEB

OEA

88

}
}

Sel A/B

MUX

B

A

74ABT853

B0 – B7

PARITY

9–bit

Odd

Parity

9

Tree

”P”

ERROR

ENABLE

CLEAR

SA00264

ABSOLUTE MAXIMUM RATINGS

SYMBOL

V

CC

I

IK

V

I

I

OK

V

OUT

I

OUT

T

stg

DC supply voltage –0.5 to +7.0 V
DC input diode current VI < 0 –18 mA
DC input voltage
DC output diode current VO < 0 –50 mA
DC output voltage
DC output current output in Low state 128 mA
Storage temperature range –65 to 150 °C

PARAMETER CONDITIONS RATING UNIT

3

3

1, 2

–1.2 to +7.0 V

output in Off or High state –0.5 to +5.5 V

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1995 Sep 06

3

Philips Semiconductors Product specification

8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT

MIN MAX

V

CC

V

I

V

IH

V

IL

I

OH

I

OL

∆t/∆v Input transition rise or fall rate 0 5 ns/V

T

amb

DC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER TEST CONDITIONS T

V

IK

V

OH

V

OL

I

I

I

OFF

I

PU/PD

IIH + I

OZH

IIL + I

OZL

I

CEX

I

O

I

CCH

I

CCL

I

CCZ

∆I

CC

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. This parameter is valid for any V
transition time of up to 100µsec is permitted. The ERROR

DC supply voltage 4.5 5.5 V
Input voltage 0 V
High-level input voltage 2.0 V
Low-level input voltage 0.8 V
High-level output current –32 mA
Low-level output current 64 mA

Operating free-air temperature range –40 +85 °C

LIMITS

= +25°C

amb

Min Typ Max Min Max

Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V

VCC = 4.5V; IOH = –3mA; VI = VIL or V

High–level output voltage
All outputs except ERROR

VCC = 5.0V; IOH = –3mA; VI = VIL or V
VCC = 4.5V; IOH = –32mA; VI = VIL or V

Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V

IH

IH

IH

IH

2.5 3.5 2.5 V

3.0 4.0 3.0 V

2.0 2.6 2.0 V

0.42 0.55 0.55 V

Input leakage Control pins VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA
current Data pins VCC = 5.5V; VI = GND or 5.5V ±5 ±100 ±100 µA
Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA

Power-up/down 3-State
output current

3

3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V
3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V
Output high leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V
Output current

1

Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or V

Additional supply current per
input pin

2

CC

VCC = 2.1V; VO = 0.5V; VI = GND or VCC;

= Don’t care

V

OE

IH
IH

CC

±5.0 ±50 ±50 µA

5.0 50 50 µA

–5.0 –50 –50 µA

5.0 50 50 µA
VCC = 5.5V; VO = 2.5V –50 –100 –180 –50 –180 mA
VCC = 5.5V; Outputs High, VI = GND or V

CC

CC

VCC = 5.5V; Outputs 3-State;

= GND or V

V

I

CC

Outputs enabled, one input at 3.4V ,
other inputs at V

or GND; VCC = 5.5V

CC

Outputs 3-State, one data input at 3.4V ,
other inputs at V

or GND; VCC = 5.5V

CC

Outputs 3-State, one enable input at 3.4V ,
other inputs at V

between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10%, a

or GND; VCC = 5.5V

CC

0.5 250 250 µA

25 38 38 mA

0.5 50 50 µA

0.5 1.5 1.5 mA

0.01 50 50 µA

0.5 1.5 1.5 mA

output pin 10 is not included in this spec due to the open collector design.

74ABT853

CC

T

= –40°C

amb

to +85°C

V

UNIT

1995 Sep 06

4

Philips Semiconductors Product specification

8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)

AC CHARACTERISTICS

GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORMS

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

Propagation delay
An to Bn or Bn to An

Propagation delay
An to PARITY

Propagation delay

to PARITY

OEA
Propagation delay

to ERROR

CLEAR
Propagation delay

ENABLE

to ERROR

Propagation delay
Bn or PARITY to ERROR

Output enable time

to An or OEB to Bn, PARITY

OEA
Output disable time

to An or OEB to Bn, PARITY

OEA

4

1, 4

1, 4

3 1.0 3.6 5.5 1.0 6.2 ns

4

1, 4

2, 5

2, 5

74ABT853

LIMITS

T

= +25oC

amb

= +5.0V

V

CC

Min Typ Max Min Max

1.2

1.0

2.1

2.5

1.8

2.3

1.8

1.8

2.0

3.0

1.0

2.1

3.1

3.2

3.4

2.6

7.4

7.4

6.6

6.7

3.8

4.5

7.9

9.0

3.2

4.1

5.1

5.6

4.8

4.0

9.5

9.7

8.5

8.6

5.1

5.8

10.1

11.5

5.1

5.8

7.3

7.2

T

= –40 to +85oC

amb

= +5.0V ±10%

V

CC

1.2

1.0

2.1

2.5

1.8

2.3

1.8

1.8

2.0

3.0

1.0

2.1

3.1

3.2

5.3

4.5

11.2

11.0

10.5

10.0

6.0

6.6

11.7

12.8

6.2

6.7

7.9

8.1

UNIT

ns

ns

ns

ns

ns

ns

ns

AC SETUP REQUIREMENTS

GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORMS

ts(H)

t

s

th(H)
t

h

ts(H)

th(L)

tw(L)

tw(L)

Setup time, High or Low

(L)

Bn or PARITY to ENABLE
Hold time, High or Low

(L)

Bn or PARITY to ENABLE
Setup time, High

CLEAR
Hold time, Low

CLEAR
Pulse width, Low

CLEAR
Pulse width, Low

ENABLE

to ENABLE

to ENABLE

6

6

6 2.0 –1.6 2.0 ns

6 3.0 1.8 3.0 ns

3 3.5 1.0 3.5 ns

6 4.0 2.5 4.0 ns

LIMITS

T

amb

V

CC

= +25oC
= +5.0V

T

= –40 to +85oC

amb

= +5.0V ±10%

V

CC

MIN TYP MIN

8.5

8.5

0.0

0.0

6.5

3.6

–3.4
–6.3

8.5

8.5

0.0

0.0

UNIT

ns

ns

1995 Sep 06

5

Philips Semiconductors Product specification

8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)

AC WAVEFORMS

VM = 1.5V, VIN = GND to 3.0V

INPUT

OUTPUT

Waveform 1. Propagation Delay For Inverting Output

OEA, OEB V

OUTPUT

Waveform 2. 3-State Output Enable Time to High Level and

Output Disable Time from High Level

V

M

t

PHL

M

t

PZH

V

M

t

PLH

V

M

V

M

V

M

t

PHZ

V

M

SA00216

–0.3V

V

OH

0V

SA00238

74ABT853

INPUT

OUTPUT

Waveform 4. Propagation Delay For Non-Inverting Output

OEA, OEB

OUTPUT

Waveform 5. 3-State Output Enable Time to Low Level and

V

M

t

PLH

V

M

V

V

M

t

PZL

M

V

M

V

M

t

PHL

t

PLZ

Output Disable Time from Low Level

V

OL

V

M

SA00023

+0.3V

0V

SA00239

CLEAR

ERROR

V

M

V

M

t

PLH

V

M

t

(L)

w

SA00265

Waveform 3. CLEAR Pulse Width and CLEAR to ERROR Delay

CLEAR,

Bn, PARITY

ENABLE

V

V

M

M

ts(H)

NOTE: The shaded areas indicate when the input is permitted to

change for predictable output performance.

(H)

t

h

V

M

V

MVM

t

(L)

s

tw(L)

V

M

V

M

SA00266

(L)

t

h

Waveform 6. Data Setup and Hold Times and ENABLE Pulse

Width

1995 Sep 06

6

Philips Semiconductors Product specification

8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)

TYPICAL PROPAGA TION DELAYS VERSUS LOAD FOR OPEN COLLECT OR OUTPUTS

18

16

14

12

10

8

6

Propagation delay (ns)

4

2

0

0 100 200 300 400 500 600

NOTE:

When using Open-Collector parts, the value of the pull–up resistor greatly affects the value of the t
500Ω to 100Ω will improve the t
that the total I

current through the resistor and the total IIL’s of the receivers does not exceed the IOL maximum specification.

OL

over 300% with only a slight change in the t

PLH

Load resistor (Ω)

. However, if the value of the pull-up resistor is changed, the user must make certain

PHL

. For example, changing the specified pull-up resistor value from

PLH

t

t

PHL

PLH

74ABT853

TEST CIRCUIT AND WAVEFORM

V

CC

V

OUT

C

L

PULSE

GENERATOR

V

IN

D.U.T

R

T

Test Circuit for 3-State Outputs

SWITCH POSITION

TEST SWITCH

t
t

PLZ
PZL

closed
closed

LOAD VALUES

OUTPUT RXV

ERROR 100Ω V
All other 500Ω 7.0V

All other open

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.

= Load capacitance includes jig and probe capacitance;

C

L

see AC CHARACTERISTICS for value.

= Termination resistance should be equal to Z

R

T

pulse generators.

OUT

R

R

of

X

L

CC

SA00241

t

90%

V

X

NEGATIVE
PULSE

POSITIVE
PULSE

10%

V

M

10% 10%

t

THL

t

TLH

90% 90%

V

M

W

V

M

(tF)

(tR)t

V

M

t

W

90%

10%

t

TLH

THL

AMP (V)

0V

(tR)

(tF)

AMP (V)

0V

VM = 1.5V

X

Input Pulse Definition

INPUT PULSE REQUIREMENTS

FAMILY

Amplitude Rep. Rate t

t

W

t

R

F

74ABT 3.0V 1MHz 500ns 2.5ns 2.5ns

SA00242

1995 Sep 06

7