Page 1
INTEGRATED CIRCUITS
74ABT16899
74ABTH16899
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
Product specification
Supersedes data of 1997 Mar 28
IC23 Data Handbook
1998 Feb 25
Page 2
Philips Semiconductors Product specification
Quiescent supply current
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
FEA TURES
•Symmetrical (A and B bus functions are identical)
•Selectable generate parity or ”feed-through” parity for A-to-B and
B-to-A directions
•Independent transparent latches for A-to-B and B-to-A directions
•Selectable ODD/EVEN parity
•Continuously checks parity of both A bus and B bus latches as
and ERRB
ERRA
•Open-collector ERR output
•Ability to simultaneously generate and check parity
•Can simultaneously read/latch A and B bus data
•Output capability: +64 mA/–32mA
•Latch-up protection exceeds 500mA per Jedec Std 17
•ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
•Power up 3-State
•Power-up reset
•Live insertion/extraction permitted
•Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
DESCRIPTION
The 74ABT/H16899 is a 16-bit to 16-bit parity transceiver with
separate transparent latches for the A bus and B bus. Either bus
can generate or check parity. The parity bit can be fed-through with
no change or the generated parity can be substituted with the SEL
input.
74ABT16899
74ABTH16899
Parity error checking of the A and B bus latches is continuously
provided with ERRA
The 74ABT/H16899 features independent latch enables for the A
and B bus latches, a select pin for ODD/EVEN
error signal output pins for checking parity.
FUNCTIONAL DESCRIPTION
The 74ABT/H16899 has three principal modes of operation which
are outlined below. All modes apply to both the A-to-B and B-to-A
directions.
Transparent latch, Generate parity, Check A and B bus parity:
Bus A (B) communicates to Bus B (A), parity is generated and
passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are
High and the Mode Select (SEL
A0-A7 and B0-B7 can be checked and monitored by ERRA
ERRB
. (Fault detection on both input and output buses.)
Transparent latch, Feed-through parity, Check A and B bus
parity:
Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL
is High. Parity is still generated and checked as ERRA and ERRB
and can be used as an interrupt to signal a data/parity bit error to the
CPU.
Latched input, Generate/Feed-through parity, Check A (and B)
bus parity:
Independent latch enables (LEA and LEB) allow other permutations
of:
•Transparent latch / 1 bus latched / both buses latched
•Feed-through parity / generate parity
•Check in bus parity / check out bus parity / check in and out bus
parity
and ERRB, even with both buses in 3-State.
parity, and separate
) is Low, the parity generated from
and
QUICK REFERENCE DATA
SYMBOL PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
C
IN
C
I/O
I
CCZ
I
CCL
ORDERING INFORMATION
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16899 DL BT16899 DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16899 DGG BT16899 DGG SOT364-1
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16899 DL BH16899 DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16899 DGG BH16899 DGG SOT364-1
1998 Feb 25 853-1960 19018
CONDITIONS
T
= 25°C; GND = 0V
amb
Propagation delay
An to Bn or Bn to An
Propagation delay
An to ERRA
Input capacitance VI = 0V or V
Output capacitance Outputs disabled; VO = 0V or V
pp
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
CL = 50pF; VCC = 5V 2.7 ns
CL = 50pF; VCC = 5V 5.0 ns
CC
CC
Outputs disabled; VCC =5.5V 500 µA
Output Low; VCC = 5.5V 10.5 mA
2
TYPICAL UNIT
4 pF
7 pF
Page 3
Philips Semiconductors Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
PIN CONFIGURATION
ODD/EVEN
1APAR
1ERRA
2ERRA
2APAR
1
2
OEA
3
1A0
4
GND
5
1A1
6
1A2
7
1A3 1B3
8
1A4
9
V
CC
10
1A5
11
1A6
12
1A7
13
14
15
GND
16
17
18
2A7 2B7
19
2A6
20
2A5
21
V
CC
22
2A4 2B4
23
2A3
24
2A2
25
2A1
26
GND
27
2A0
28 29
LEB
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
SH00082
SEL
LEA
1B0
GND
1B1
1B2
1B4
V
CC
1B5
1B6
1B7
1BPAR
1ERRB
GND
2ERRB
2BPAR
2B6
2B5
V
CC
2B3
2B2
2B1
GND
2B0
OEB
74ABT16899
74ABTH16899
PIN DESCRIPTION
SYMBOL
1A0 - 1A7
2A0 - 2A7
1B0 - 1B7
2B0 - 2B7
1APAR
2APAR
1BPAR
2BPAR
ODD/EVEN 1 Parity select input (Low for EVEN parity)
OEA, OEB 2, 29
SEL 56 Mode select input (Low for generate)
LEA, LEB 55, 28 Latch enable inputs (transparent High)
1ERRA, 1ERRB
2ERRA, 2ERRB
GND 4, 15, 26, 31, 42, 53 Ground (0V)
V
CC
1998 Feb 25
PIN
NUMBER
3, 5, 6, 7, 8, 10, 11, 12
27, 25, 24, 23, 22, 20, 19, 18
54, 52, 51, 50, 49, 47, 46, 45
30, 32, 33, 34, 35, 37, 38, 39
Latched A bus 3-State inputs/outputs
Latched B bus 3-State inputs/outputs
13, 17 A bus parity 3-State input
44, 40 B bus parity 3-State input
Output enable inputs (gate A to B,
B to A)
14, 43,
16, 41
Error signal outputs (active-Low)
9, 21, 36, 48 Positive supply voltage
3
NAME AND FUNCTION
Page 4
Philips Semiconductors Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
LOGIC SYMBOL
3 5 6 7 8 10 11 12
1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7
55
28
56
29 OEB
LEA
LEB
SEL
1
ODD/EVEN
OEA
2
1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7
54 52 51 50 49 47 46 45
PARITY AND ERROR FUNCTION TABLE
INPUTS OUTPUTS
SEL ODD/EVEN
xPAR
(A or B)
H H H
H H L
H L H
H L L
L H H
L H L
L L H
L L L
H = High voltage level
L = Low voltage level
t = Transmit–if the data path is from A→B then ERRt
r = Receive–if the data path is from A→B then ERRr is ERRB
* Blocked if latch is not transparent
Σ of High
Inputs
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
13
1APAR
1ERRA
1ERRB
1BPAR
44
xPAR
(B or A)
H
H
L
L
H
H
L
L
H
L
H
L
L
H
L
H
is ERRA
14
43
ERRt ERRr*
74ABT16899
74ABTH16899
27 25 24 23 22 20 19 18
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
55
28
56
29
LEA
LEB
SEL
1
ODD/EVEN
OEA
2
OEB
2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7
30 32 33 34 35 37 38 39
PARITY MODES
H
L
L
H
L
H
H
L
H
L
L
H
L
H
H
L
H
L Odd
L
Mode
H
L
H Even
H
Mode
L
H
H Odd
H
Mode
H
H
H Even
H
Mode
H
17
2APAR
2ERRA
2ERRB
2BPAR
40
16
41
SH00083
Feed-through/check parity
Generate parity
1998 Feb 25
4
Page 5
Philips Semiconductors Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
BLOCK DIAGRAM
9–bit
Transparent
Latch
LEA
A0
A1
A2
A3
A4
A5
A6
A7
APAR
LE
Parity
Generator
9–bit
Output
Buffer
1
mux
0
9–bit
Output
Buffer
9–bit
Transparent
Latch
OE
74ABT16899
74ABTH16899
OEB
B0
B1
B2
B3
B4
B5
B6
B7
BPAR
OEA
SEL
ODD/
EVEN
OE
mux
1
0
Parity
Generator
LE
(1 of 2 parity blocks)
FUNCTION TABLE
INPUTS OPERATING MODE
OEB OEA SEL LEA LEB
H H X X X 3-State A bus and B bus (input A & B simultaneously)
H L L L H B → A, transparent B latch, generate parity from B0 - B7, check B bus parity
H L L H H B → A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity
H L L X L B → A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity
H L H X H B → A, transparent B latch, parity feed-through, check B bus parity
H L H H H B → A, transparent A & B latch, parity feed-through, check A & B bus parity
L H L H X A → B, transparent A latch, generate parity from A0 - A7, check A bus parity
L H L H H A → B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity
L H L L X A → B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity
L H H H L A → B, transparent A latch, parity feed-through, check A bus parity
L H H H H A → B, transparent A & B latch, parity feed-through, check A & B bus parity
L L X X X Output to A bus and B bus (NOT ALLOWED)
H = High voltage level
L = Low voltage level
X = Don’t care
LEB
ERRA
ERRB
SH00084
1998 Feb 25
5
Page 6
Philips Semiconductors Product specification
I
DC output current
mA
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
I
IK
V
I
OK
V
OUT
OUT
T
stg
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 1505C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC supply voltage –0.5 to +7.0 V
DC input diode current VI < 0 –18 mA
DC input voltage
I
DC output diode current VO < 0 –50 mA
DC output voltage
p
Storage temperature range –65 to 150 °C
PARAMETER CONDITIONS RATING UNIT
3
3
1, 2
output in Off or High state –0.5 to +5.5 V
output in Low state 128
output in High state –64
74ABT16899
74ABTH16899
–1.2 to +7.0 V
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS UNIT
Min Max
V
CC
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 0 5 ns/V
T
amb
DC supply voltage 4.5 5.5 V
Input voltage 0 V
I
High-level input voltage 2.0 V
IH
Low-level Input voltage 0.8 V
IL
High-level output current –32 mA
Low-level output current 64 mA
Operating free-air temperature range –40 +85 °C
CC
V
1998 Feb 25
6
Page 7
Philips Semiconductors Product specification
Bushold current A or B
4ABTH16899
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST CONDITIONS T
Min Typ Max Min Max
V
V
V
V
RST
Input clamp voltage VCC = 4.5V; IIK = –18mA –0.7 –1.2 –1.2 V
IK
VCC = 4.5V; IOH = –3mA; VI = VIL or V
High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or V
OH
VCC = 4.5V; IOH = –32mA; VI = VIL or V
Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V
OL
Power-up output low
3
voltage
I
Input leakage Control pins VCC = 5.5V; VI = GND or 5.5V ±0.2 ±1.0 ±1.0 µA
I
VCC = 5.5V; IO = 1mA; VI = GND or V
IH
IH
IH
IH
CC
current Data pins VCC = 5.5V; VI = GND or 5.5V ±1.0 ±100 ±100 µA
VCC = 4.5V; VI = 0.8V 75 75
I
HOLD
I
OFF
IPU/I
IIH + I
IIL + I
I
CEX
I
CCH
I
CCL
I
CCZ
∆I
5
inputs
7
Power-off leakage current VCC = 0.0V; VO or V
Power-up/down 3-State
PD
output current
3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V
OZH
3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V
OZL
4
Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V
I
O
Output current
1
Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or V
Additional supply current per
CC
input pin
2
VCC = 4.5V; VI = 2.0V –75 –75
VCC = 5.5V; VI = 0 to 5.5V ±500
≤
4.5V ±2.0 ±100 ±100 µA
I
VCC = 2.1V; VO = 0.5V; VI= GND or V
CC
IH
IH
CC
VCC = 5.5V; VO = 2.5V –50 –100 –180 –50 –180 mA
VCC = 5.5V; Outputs High, VI = GND or V
CC
CC
VCC = 5.5V; Outputs 3-State;
VI = GND or V
CC
VCC = 5.5V; one input at 3.4V,
other inputs at VCC or GND
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
transition time of up to 100µsec is permitted.
between 0V and 2.1V , with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10%, a
CC
5. This is the bus hold overdrive current required to force the input to the opposite logic state.
= +25°C
amb
2.5 3.1 2.5 V
3.0 3.6 3.0 V
2.0 2.7 2.0 V
0.36 0.55 0.55 V
0.13 0.55 0.55 V
±5.0 ±50 ±50 µA
2.0 50 50 µA
–2.0 –50 –50 µA
2.0 50 50 µA
0.5 1 1 mA
10.5 19 19 mA
0.5 1 1 mA
0.2 1.5 1.5 mA
74ABT16899
74ABTH16899
T
= –40°C
amb
to +85°C
UNIT
µA
1998 Feb 25
7
Page 8
Philips Semiconductors Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
AC CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω
SYMBOL PARAMETER WAVEFORM
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
Propagation delay
An to Bn or Bn to An
Propagation delay
An to BPAR or Bn to APAR
Propagation delay
An to ERRA or Bn to ERRB
Propagation delay
APAR to BPAR or BPAR to APAR
Propagation delay
APAR to ERRA or BPAR to ERRB
Propagation delay
ODD/EVEN to APAR or BPAR
Propagation delay
ODD/EVEN to ERRA or ERRB
Propagation delay
SEL
to APAR or BPAR
Propagation delay
SEL to ERRA or ERRB
Propagation delay
LEA to Bn or LEB to An
Propagation delay
LEA to BPAR or LEB to APAR
Propagation delay
LEA to ERRA or LEB to ERRB
Output enable time
OEA to An, APAR or OEB to Bn, BPAR
Output disable time
OEA to An, APAR or OEB to Bn, BPAR
1
2
3
1
6
5
4
8
8
9
9
7
11, 12
11, 12
74ABT16899
74ABTH16899
LIMITS
T
= +25oC
amb
VCC = +5.0V
CL = 50pF
RL = 500Ω
Min Typ Max Min Max
1.0
1.0
2.5
2.5
2.8
2.8
1.5
1.5
1.0
1.0
2.5
2.5
2.5
2.5
1.5
1.5
2.5
2.5
1.0
1.0
2.8
2.8
1.1
1.2
1.0
1.0
2.5
1.5
2.7
2.2
4.9
5.0
5.0
4.9
3.1
2.5
2.5
2.5
4.1
3.9
4.1
4.0
3.1
2.6
5.0
4.4
3.1
2.8
5.5
5.1
5.4
5.8
2.6
2.3
3.9
2.8
4.5
3.5
7.2
7.4
9.3
8.0
3.9
3.1
3.3
3.3
5.1
5.0
6.1
5.5
4.0
3.4
7.5
5.9
4.2
4.3
8.0
7.7
8.0
8.0
3.6
3.2
5.6
4.1
T
= –40 to +85oC
amb
VCC = +5.0V ±10%
CL = 50pF
RL = 500Ω
1.0
1.0
2.5
2.5
2.8
2.8
1.5
1.5
1.0
1.0
2.5
2.5
2.5
2.5
1.5
1.5
2.5
2.5
1.0
1.0
2.8
2.8
1.1
1.2
1.0
1.0
2.5
1.5
5.5
6.9
8.8
8.7
11.0
10.2
4.8
3.9
4.3
3.9
6.1
5.7
7.1
6.6
5.0
4.2
8.3
7.1
5.2
4.7
9.7
9.1
9.2
9.6
5.1
4.5
6.0
4.4
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC SETUP REQUIREMENTS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω
SYMBOL PARAMETER WAVEFORM
ts(H)
ts(L)
th(H)
th(L)
tw(H)
1998 Feb 25
Setup time, High or Low
An, APAR to LEA or Bn, BPAR to LEB
Hold time, High or Low
An, APAR to LEA or Bn, BPAR to LEB
Pulse width, High
LEA or LEB
10
10
10 3.0 1.0 3.0 ns
LIMITS
T
= +25oC
amb
VCC = +5.0V
CL = 50pF
R
= 500Ω
L
T
= –40 to +85oC
amb
VCC = +5.0V ±10%
CL = 50pF
R
= 500Ω
L
UNIT
Min Typ Min
1.5
1.0
1.5
1.0
0.3
–0.1
0.1
–0.2
1.5
1.0
1.5
1.0
ns
ns
8
Page 9
Philips Semiconductors Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
1
SEL
An, APAR
(Bn, BPAR)
Bn, BPAR
(An, APAR)
Waveform 1. Propagation Delay, An to Bn, Bn to An, APAR to BPAR, BPAR to APAR
SEL
ODD/EVEN
V
M
t
PLH
0
0
V
M
V
M
t
PHL
74ABT16899
74ABTH16899
INPUT
V
M
OUTPUT
SA00293
1
LEA
(LEB)
An
(Bn)
BPAR
(APAR)
ODD PARITY
V
M
t
PHL
EVEN PARITY ODD PARITY
V
M
V
M
t
PLH
V
M
NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1
Waveform 2. Propagation Delay, An to BPAR or Bn to APAR
ODD/EVEN
0
APAR
(BPAR)
SEL
LEA
(LEB)
(Bn)
An
0
1
ODD PARITY
V
M
EVEN PARITY ODD PARITY
V
M
INPUT
OUTPUT
SA00294
INPUT
1998 Feb 25
ERRA
(ERRB)
t
PLH
V
M
t
PHL
V
M
NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1
Waveform 3. Propagation Delay, An to ERRA or Bn to ERRB
9
OUTPUT
SA00295
Page 10
Philips Semiconductors Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
1
APAR
(BPAR)
An
(Bn)
ODD/EVEN
ERRA
(ERRB)
NOTE: Only even parity mode is shown, odd parity mode would cause inverted output
Waveform 4. Propagation Delay, ODD/EVEN to ERRA or ODD/EVEN to ERRB
V
M
t
PLH
V
M
V
M
EVEN PARITY
t
PHL
V
M
74ABT16899
74ABTH16899
INPUT
INPUT
OUTPUT
SA00296
SEL
0
APAR
(BPAR)
ODD/EVEN
(APAR)
(Bn)
BPAR
0
An
t
PLH
V
M
V
M
V
M
EVEN PARITY
t
PHL
V
M
NOTE: Only even parity mode is shown, odd parity mode would cause inverted output
Waveform 5. Propagation Delay, ODD/EVEN to APAR or ODD/EVEN to BPAR
INPUT
INPUT
OUTPUT
SA00297
1998 Feb 25
10
Page 11
Philips Semiconductors Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
ODD/EVEN
0
An
(Bn)
APAR
(BPAR)
ERRA
(ERRB)
V
M
NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output
and odd parity mode would be with ODD/EVEN = 1
Waveform 6. Propagation Delay, APAR to ERRA or BPAR to ERRB
1
ODD/EVEN
t
PLH
V
M
V
74ABT16899
74ABTH16899
EVEN PARITY
t
PHL
V
M
M
INPUT
INPUT
OUTPUT
SA00298
APAR
(BPAR)
(ERRB)
(Bn)
LEA
(LEB)
ERRA
An
0
EVEN PARITY
ODD PARITY EVEN PARITY
V
M
t
PLH
V
M
V
M
t
PHL
V
M
NOTE: Only odd parity mode is shown. Even parity mode would be with ODD/EVEN = o
Waveform 7. Propagation Delay, LEA to ERRA or LEB to ERRB
INPUT
INPUT
OUTPUT
SA00299
1998 Feb 25
11
Page 12
Philips Semiconductors Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
1
ODD/EVEN
APAR
(BPAR)
(APAR)
NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output
and odd parity mode would be with ODD/EVEN = 1
0
An
(Bn)
SEL
BPAR
V
M
t
PLH
V
M
V
Waveform 8. Propagation Delay, SEL to BPAR or SEL to APAR
74ABT16899
74ABTH16899
EVEN PARITY
t
PHL
V
M
M
INPUT
INPUT
OUTPUT
SA00300
1
SEL
APAR, An]
(BPAR, Bn)
LEA
(LEB)
Bn, BPAR
(An, APAR)
V
M
t
PLH
V
M
V
M
t
PHL
V
M
SA00301
Waveform 9. Propagation Delay, LEA to BPAR or LEB to APAR, LEA to Bn or LEB to An
APAR, BPAR,
An, Bn
LEA, LEB
The shaded areas indicate when the input is permitted to change for predictable output performance.
ts(H)
V
M
V
M
t
(H)
h
V
M
V
M
V
M
(L)
t
s
tw(H)
V
M
t
(L)
h
V
M
SA00302
Waveform 10. Data Setup and Hold Times, Pulse W idth High
INPUT
INPUT
OUTPUT
1998 Feb 25
12
Page 13
Philips Semiconductors Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
OEA,
OEB
An, APAR,
Bn, BPAR
Waveform 11. 3-State Output Enable Time to High Level and Output Disable Time from High Level
OEA,
OEB
An, APAR,
Bn, BPAR
Waveform 12. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
V
M
t
PZH
V
M
t
PZL
74ABT16899
74ABTH16899
V
M
t
PHZ
V
–0.3V
V
M
V
M
t
PLZ
V
M
VOL +0.3V
OH
0V
SA00303
SA00304
TEST CIRCUIT AND WAVEFORM
V
CC
R
PULSE
GENERATOR
V
IN
R
T
D.U.T.
V
OUT
Test Circuit for Open Collector Outputs
SWITCH POSITION
TEST SWITCH
t
PLZ
t
PZL
closed
closed
LOAD VALUES
OUTPUT RX V
ERROR 100 V
All other 500 7.0V
All other open
DEFINITIONS:
RL= Load resistor; see AC CHARACTERISTICS for value.
CL= Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
X
C
R
L
L
Ω
Ω
OUT
of
V
X
X
CC
NEGATIVE
PULSE
POSITIVE
PULSE
FAMILY
74ABT/H16
90%
10%
t
W
V
M
10%
)
t
THL (tf
)
t
TLH (tr
90%
V
M
t
TLH (tr
t
THL (tf
t
W
Input Pulse Definition
INPUT PULSE REQUIREMENTS
Amplitude
3.0V
Rep. Rate
1MHz 500ns
10%
)
)
90%
V
M
V
M
t
w
AMP (V)
90%
0V
AMP (V)
10%
0V
t
R
t
F
2.5ns 2.5ns
SH00009
1998 Feb 25
13
Page 14
Philips Semiconductors Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1
74ABT16899
74ABTH16899
1998 Feb 25
14
Page 15
Philips Semiconductors Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1
74ABT16899
74ABTH16899
1998 Feb 25
15
Page 16
Philips Semiconductors Product specification
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
74ABT16899
74ABTH16899
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-03507
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