Datasheet 73S1210F Datasheet (TERIDIAN Semiconductor)

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Page 1

73S1210F

Self-Contained Smart Card Reader

with PINpad and Power Management

Simplifying System Integration™

DATA SHEET

May 2009

GENERAL DESCRIPTION

The 73S1210F is a versatile and economical CMOS System-on-Chip device intended for smart card reader applications. The circuit is built around an 80515 highperformance core; it features primarily an ISO-7816 / EMV interface and a generic asynchronous serial interface. Delivered with turnkey Teridian embedded firmware, it forms a ready-to-use smart card reader solution that can be seamlessly incorporated into any microprocessor-based system where a serial line is available.

The solution is scalable, thanks to a built-in I that allows to drive external electrical smart card interfaces such as Teridian 73S8010 ICs. This makes the so l ution immediately able to support multi-card slots or multi-SAM architectures.

In addition, the 73S1210 features a 5x6 PINpad interface, 8 user I/Os, multiple interrupt options and an analog volt age input (for DC voltage monitoring such as battery level detection) that make it suitable for low-cost PINpad reader devices.

The 80515 CPU core instruction set is compatible with the industry standard 8051, while offering one clock-cycle per instruction processing power (most instructions). Wit h a CPU clock running up to 24MHz, it results in up to 24MIPS available that meets the requirements of various encryption needs such as AES, DES / 3-DES and even RSA (for PIN encryption for instance).

The circuit requires a single 6MHz to 12MHz crystal.

The respective 73S1210F embedded memories are 32KB Flash program memory, 2KB user XRAM memory, and 256B IRAM memory. Dedicated FIFOs for the IS O 7816 UART are independent from the user XRAM and IRAM.

Alternatively to the turnkey firmware offered by Teridian, customers can develop their own embedded firmware directly within their application or using Teridian 73S1210F Evaluation Board through a JTAG-like interface .

The chip incorporates an inductor-based DC-DC convert er that generates all the necessary voltages to the various 73S1210F function blocks (smart card interface, digital core, etc.) from any of two distinct power supply sources: the +5V bus (V

4.0V to 6.5V). The chip automatically powers-up the DCDC converter with V supply input if V can support a wider power supply input range (2.7V to

6.5V), when using a single system supply source.

, 4.4 to 6.5V), or a main battery (V

BUS

if it is present, or uses V

BUS

is not present. Alternatively, the pin VPC

BUS

C interface

BAT

as the

BAT

In addition, the circuit features an ON/OF F mode which operates directly with an ON/OFF system switch: Any activity on the ON/OFF button is debounced internally and controls the power generation circuit accordingly, under the supervision of the firmware (OFF request / OFF acknowledgement at firmware level). The OFF mode can be alternatively initiated from the controller (firmware action instead of ON/OFF switch).

In OFF mode, the circuit typically draws less than 1µA, which makes it ideal for applications where battery life must be maximized.

Embedded Flash memory is in-system programmable and lockable by means of on-silicon fuses. This makes the 73S1210F suitable for both development and production phases.

Teridian Semiconductor Corporation offers with its 73S1210F a very comprehensive set of software libraries for EMV. Refer to the 73S12xxF Sof tware User’s Guide for a complete description of the Application Programming Interface (API Libraries) and related software modules.

A complete array of development and programming tools, libraries and demonstration boards enable rapid development and certification of readers that meet most demanding smart card standards.

APPLICATIONS

• PINpad smart card readers:

o With serial connectivity o Ideal for low-cost POS Terminals and Digital

Identification (Secure Login, Gov’t ID, ...)

• SIM Readers in Personal Wireless devices

• Payphones & Vending machines

• General purpose smart card readers

ADVANTAGES

• Reduced BOM

• Versatile power supply options

o 2.7V to 6.5V ranges

• Higher performance CPU core (up to 24MIPS)

• Built-in EMV/ISO slot, expandable to multi-slots

• Flexible power supply options

o On-chip DC-DC converter o CMOS switches between supply inputs

• Sub-µA Power Down mode with ON/OFF switch

• Powerful In-Circuit Emulation and Programming

• A complete set of EMV4.1 / ISO7816 libraries

• Turnkey PC/SC firmware and host drivers

o Multiple OS supported

Page 2

73S1210F Data Sheet DS_1210F_001

FEATURES 80515 Core:

• 1 clock cycle per instruction (most instructions)

• CPU clocked up to 24MHz

• 32KB Flash memory (lockable)

• 2kB XRAM (User Data Memory)

• 256 byte IRAM

• Hardware watchdog timer

Oscillators:

• Single low-cost 6MHz to 12MHz crystal

• An Internal PLL provides all the necessary clocks to

each block of the system

Interrupts:

• Standard 80C515 4-priority level structure

• 9 different sources of interrupt to the core

Power Down Modes:

• 2 standard 80C515 Power Down and IDLE modes

• Sub-µA OFF mode

• ON/OFF Main System Power Switch:

• Input for an SPST momentary switch to ground

Timers:

• (2) Standard 80C52 timers T0 and T1

• (1) 16-bit timer

Built-in ISO-7816 Card Interface:

• Linear regulator produces VCC for the card (1.8V, 3V or 5V)

• Full compliance with EMV 4.1

• Activation/Deactivation sequencers

• Auxiliary I/O lines (C4 and C8 signals)

• 7kV ESD protection on all interface pins

Communication with Smart Cards:

• ISO 7816 UART 9600 to 115kbps for T=0, T=1

• (2) 2-Byte FIFOs for transmit and receive

• Configured to drive multiple external Teridian

73S8010x interfaces (for multi-SAM architectures)

Voltage Detection:

• Analog Input (detection range: 1.0V to 2.5V)

Communication Interfaces:

• Full-duplex serial interface (1200 to 115kbps UART)

C Master Interface (400kbps)

• I

• Man-Machine Interface and I/Os:

• 6x5 Keyboard (hardware scanning, debouncing

and scrambling)

• (8) User I/Os

• Single programmable current output (LED)

• Operating Voltage:

• Single supply 2.7V to 6.5V operation (VPC)

• 5V supply (VBUS 4.4V to 5.5V) with or without

battery back up operation (VBAT 4.0V to 6.5V)

• Automated detection of voltage presence - Priority on VBUS over VBAT

DC-DC Converter:

• Requires a single 10µH Inductor

• 3.3V / 20mA supply available for external circuits

Operating Temperature:

• -40°C to 85°C

Package:

• 68-pin QFN, 44 pin QFN

Turnkey Firmware:

• Compliant with PC/SC, ISO7816 and EMV4.1 specifications

• Features a Power Down mode accessible from the host

• Supports Plug & Play over serial interface

• Windows

• Windows CE / Mobile driver available (*)

• Linux and other OS: Upon request

• Or for custom developments:

o A complete set of ISO-7816, EMV4.1 and

o Two-level Application Pr ogr amming Interface

XP driver available (*)

low-level libraries are available for T=0 / T=1

(ANSI C-language libraries)

(*) Contact Teridian Semiconductor for condit i ons and availability.

2 Rev. 1.4

Page 3

DS_1210F_001 73S1210F Data Sheet

Table of Contents

1 Hardware Description ......................................................................................................................... 8

1.1

Pin Description ............................................................................................................................. 8

Hardware Overview ................................................................................................................... 11

1.2

80515 MPU Core ....................................................................................................................... 11

1.3

80515 Overview ............................................................................................................. 11

1.3.1

Memory Organization .................................................................................................... 11

1.3.2

Program Security ....................................................................................................................... 16

1.4

Special Function Registers (SFRs) ........................................................................................... 18

1.5

Internal Data Special Function Registers (SFRs) .......................................................... 18

1.5.1

IRAM Special Function Registers (Generic 80515 SFRs) ............................................ 19

1.5.2

External Data Special Function Registers (SFRs) ........................................................ 20

1.5.3

Instruction Set ............................................................................................................................ 22

1.6

Peripheral Descriptions .............................................................................................................. 22

1.7

Oscillator and Clock Generation .................................................................................... 22

1.7.1

Power Supply Management .......................................................................................... 25

1.7.2

Power ON/OFF .............................................................................................................. 26

1.7.3

Power Control Modes .................................................................................................... 27

1.7.4

Interrupts ........................................................................................................................ 33

1.7.5

UART ............................................................................................................................. 40

1.7.6

Timers and Counters ..................................................................................................... 45

1.7.7

WD Timer (Software Watchdog Timer) ......................................................................... 47

1.7.8

User (USR) Ports ........................................................................................................... 49

1.7.9

Analog Voltage Comparator .......................................................................................... 51

1.7.10

LED Driver ..................................................................................................................... 53

1.7.11

1.7.12

1.7.13

1.7.14

1.7.15

1.7.16

Typical Application Schematic ...................................................................................................... 104

Keypad Interface ............................................................................................................ 61

Emulator Port ................................................................................................................. 68

Smart Card Interface Function ...................................................................................... 69

VDD Fault Detect Function .......................................................................................... 103

C Master Interface ....................................................................................................... 54

Electrical Specification ................................................................................................................... 105

3.1

Absolute Maximum Ratings ..................................................................................................... 105

Recommended Operating Conditions ..................................................................................... 105

3.2

Digital IO Characteristics ......................................................................................................... 106

3.3

Oscillator Interface Requirements ........................................................................................... 107

3.4

DC Characteristics: Analog Input ............................................................................................. 107

3.5

Smart Card Interface Requirements ........................................................................................ 108

3.6

DC Characteristics ................................................................................................................... 110

3.7

Current Fault Detection Circuits ............................................................................................... 111

3.8

Equivalent Circuits ......................................................................................................................... 112

4 5

Package Pin Designation ............................................................................................................... 120

5.1

68-pin QFN Pinout ................................................................................................................... 120

44-pin QFN Pinout ................................................................................................................... 121

5.2

Packaging Information ................................................................................................................... 122

6.1

68-Pin QFN Package Outline .................................................................................................. 122

44-Pin QFN Package Outline .................................................................................................. 123

6.2

Ordering Information ...................................................................................................................... 124

7 8

Related Documentation .................................................................................................................. 124

Contact Information ........................................................................................................................ 124

Revision History

Rev. 1.4 3

...................................................................................................................................... 125

Page 4

73S1210F Data Sheet DS_1210F_001

Figures

Figure 1: IC Functional Block Diagram ......................................................................................................... 7

Figure 2: Memory Map Figure 3: Clock Generation and Control Circuits Figure 4: Oscillator Circuit Figure 5: Detailed Power Management Logic Block Diagram Figure 6: Power Down Control Figure 7: Detail of Power Down Interrupt Logic Figure 8: Power Down Sequencing Figure 9: External Interrupt Configuration Figure 10: I Figure 11: I Figure 12: Simplified Keypad Block Diagram Figure 13: Keypad Interface Flow Chart Figure 14: Smart Card Interface Block Diagram Figure 15: External Smart Card Interface Block Diagram Figure 16: Asynchronous Activation Sequence Timing Figure 17: Deactivation Sequence Figure 18: Smart Card CLK and ETU Generation Figure 19: Guard, Block, Wait and ATR Time Definitions Figure 20: Synchronous Activation Figure 21: Example of Sync Mode Operation: Generating/Reading ATR Signals Figure 22: Creation of Synchronous Clock Start/Stop Mode Start Bit in S ync Mode Figure 23: Creation of Synchronous Clock Start/Stop Mode Stop Bit in Sync Mode Figure 24: Operation of 9-bit Mode in Sync Mode Figure 25: 73S1210F Typical Application Schematic Figure 26: 12 MHz Oscillator Circuit Figure 27: 32KHz Oscillator Circuit Figure 28: Digital I/O Circuit Figure 29: Digital Output Circuit Figure 30: Digital I/O with Pull Up Circuit Figure 31: Digital I/O with Pull Down Circuit Figure 32: Digital Input Circuit Figure 33: OFF_REQ Interface Circuit Figure 34: Keypad Row Circuit Figure 35: Keypad Column Circuit Figure 36: LED Circuit Figure 37: Test and Security Pin Circuit Figure 38: Analog Input Circuit Figure 39: Smart Card Output Circuit Figure 40: Smart Card I/O Circuit Figure 41: PRES Input Circuit Figure 42: PRESB Input Circuit Figure 43: ON_OFF Input Circuit Figure 44: 73S1210F 68 QFN Pinout Figure 45: 73S1210F 44 QFN Pinout Figure 46: 73S1210F 68 QFN Mechanical Drawing Figure 47: 73S1210F 44 QFN Package Drawing

2 2

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C Write Mode Operation .......................................................................................................... 55

C Read Operation ................................................................................................................... 56

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4 Rev. 1.4

Page 5

DS_1210F_001 73S1210F Data Sheet

Tables

Table 1: 73S1210 Pinout Description ........................................................................................................... 8

Table 2: MPU Data Memory Map Table 3: Flash Special Function Registers Table 4: Internal Data Memory Map Table 5: Program Security Registers Table 6: IRAM Special Function Registers Locations Table 7: IRAM Special Function Registers Reset Values Table 8: XRAM Special Function Registers Reset Values Table 9: PSW Register Table 10: Port Registers Table 11: Frequencies and Mcount Values for MCLK = 96MHz Table 12: The MCLKCtl Register Table 13: The TCON Register Table 14: The INT5Ctl Register Table 15: The MISCtl0 Register Table 16: The MISCtl1 Register Table 17: The MCLKCtl Register Table 18: The PCON Register Table 19: The IEN0 Register Table 20: The IEN1 Register Table 21: The IEN2 Register Table 22: The TCON Register Table 23: The T2CON Register Table 24: The IRCON Register Table 25: External MPU Interrupts Table 26: Control Bits for External Interrupts Table 27: Priority Level Groups Table 28: The IP0 Register Table 29: The IP1 Register Table 30: Priority Levels Table 31: Interrupt Polling Sequence Table 32: Interrupt Vectors Table 33: UART Modes Table 34: Baud Rate Generation Table 35: The PCON Register Table 36: The BRCON Register Table 37: The MISCtl0 Register Table 38: The S0CON Register Table 39: The S1CON Register Table 40: The TMOD Register Table 41: Timers/Counters Mode Description Table 42: The TCON Register Table 43: The IEN0 Register Table 44: The IEN1 Register Table 45: The IP0 Register Table 46: The WDTREL Register Table 47: Direction Registers and Internal Resources for DIO Pin Groups Table 48: UDIR Control Bit Table 49: Selectable Controls Using the UxIS Bits Table 50: The USRIntCtl1 Register Table 51: The USRIntCtl2 Register Table 52: The USRIntCtl3 Register Table 53: The USRIntCtl4 Register

Table 54: The ACOMP Register ................................................................................................................. 51

Table 55: The INT6Ctl Register Table 56: The LEDCtl Register

Rev. 1.4 5

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Page 6

73S1210F Data Sheet DS_1210F_001

Table 57: The DAR Register ....................................................................................................................... 57

Table 58: The WDR Register Table 59: The SWDR Register Table 60: The RDR Register Table 61: The SRDR Register Table 62: The CSR Register Table 63: The INT6Ctl Register Table 64: The KCOL Register Table 65: The KROW Register Table 66: The KSCAN Register Table 67: The KSTAT Register Table 68: The KSIZE Register Table 69: The KORDERL Register Table 70: The KORDERH Register Table 71: The INT5Ctl Register Table 72: The SCSel Register Table 73: The SCInt Register Table 74: The SCIE Register Table 75: The VccCtl Register Table 76: The VccTmr Register Table 77: The CRDCtl Register Table 78: The STXCtl Register Table 79: The STXData Register Table 80: The SRXCtl Register Table 81: The SRXData Register Table 82: The SCCtl Register Table 83: The SCECtl Register Table 84: The SCDIR Register Table 85: The SPrtcol Register Table 86: The SCCLK Register Table 87: The SCECLK Register Table 88: The SParCtl Register Table 89: The SByteCtl Register Table 90: The FDReg Register Table 91: The FDReg Bit Functions Table 92: Divider Ratios Provided by the ETU Counter Table 93: Divider Values for the ETU Clock Table 94: The CRCMsB Register Table 95: The BGT Register Table 96: The EGT Register Table 97: The BWTB0 Register Table 98: The BWTB1 Register Table 99: The BWTB2 Register Table 100: The BWTB3 Register Table 101: The CWTB0 Register Table 102: The CWTB1 Register Table 103: The ATRLsB Register Table 104: The ATRMsB Register Table 105: The STSTO Register Table 106: The RLength Register Table 107: Smart Card SFR Table Table 108: The VDDFCtl Register Table 109: Order Numbers and Packaging Marks

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6 Rev. 1.4

Page 7

SMART

CARD

ISO

INTERFACE

SCLK

SIO

EXTERNAL

SMART

CARD

INTERFACE

POWER

REGULATION

AND VCC

CONTROL

LOGIC

GND

VDD

TBUS1

TBUS2

TBUS3

TBUS0

RXTX

ERST

ISBR

TCLK

TXD

RXD

ICE INTERFACE

SEC

SMART CARD LOGIC

ISO UART and CLOCK GENERATOR

FLASH/ROM

PROGRAM

MEMORY

32KB

DATA

XRAM

2KB

CORE

SERIAL

INT2

INT3

GND

PERIPHERAL

INTERFACE

and SFR LOGIC

FLASH

INTERFACE

TEST

OCDSI

ISR

WATCH-

DOG

TIMER

PMU

PORTS

TIMER_0_1

MEMORY_ CONTROL

CONTROL

UNIT

RAM_

SFR_

CONTROL

ALU

RESET

VOLTAGE REFERENCE

AND FUSE TRIM

CIRCUITRY

VPD REGULATOR

ANA_IN

PLL and

TIMEBASES

VDD

SCRATCH

IRAM 256B

12MHz

OSCILLATOR

X12OUT

X12IN

COL4

COL3

COL2

COL1

COL0

ROW5

ROW4

ROW3

ROW2

ROW1

ROW0

KEYPAD

INTERFACE

MASTER

INT.

SDA

SCL

USR(8:0)

DRIVERS

USR7

USR6

USR5

USR4

USR3

USR1 USR2

USR0

VCC

RST

CLK

I/O

AUX2

AUX1

PRES

VPC

GND

VBUS

VBAT

VDD

LIN

OFF_REQ

ON_OFF

GND

LED

DRIVER

LED0

Pins available on both 68 and 44-pin packages. Pins only available on 68-pin package.

DS_1210F_001 73S1210F Data Sheet

Figure 1: IC Functional Block Diagram

Rev. 1.4 7

Page 8

73S1210F Data Sheet DS_1210F_001

1 Hardware Description

1.1 Pin Description

Table 1: 73S1210 Pinout Description

Pin Name

Pin (68 QFN)

Pin (44 QFN)

X12IN 10 9 I Figure 26 MPU clock crystal oscillator input pin. A 1MΩ resistor is

X12OUT 11 10 O Figure 26 MPU clock crystal oscillator output pin. ROW(5:0)

0 1 2 3 4 5

COL(4:0) 0 1 2 3

USR(7:0) 0 1 2 3 4 5 6 7

SCL 5 6 O Figure 29 I2C (master mode) compatible Clock signal. Note: the pin

SDA 6 7 IO Figure 28 I

RXD 17 11 I Figure 32 Serial UART Receive data pin. TXD 18 12 O Figure 29 Serial UART Transmit data pin. INT3 48 30 I Figure 32 General purpose interrupt input. INT2 49 31 I Figure 32 General purpose interrupt input. SIO 47 29 IO Figure 28 IO data signal for use with external Smart Card interface

SCLK 45 28 O Figure 29 Clock signal for use with external Smart Card interface

21 22 24 33 36 37

12 13 14 16

35 34 32 31 30 29 23 20

I Figure 34 Keypad row input sense.

O Figure 35 Keypad column output scan pins.

22 21 20 19 18 17 14

Type

IO Figure 30 General-purpose user pins, individually configurable as

Equivalent

Description

Circuit*

required between pins X12IN and X12OUT.

inputs or outputs or as external input interrupt ports.

is configured as an open drain output. When the I2C interface is being used, an external pull up resistor is required. A value of 3K is recommended.

C (master mode) compatible data I/O. Note: this pin is bidirectional. When the pin is configured as output, it is an open drain output. When the I2C interface is being used, an external pull up resistor is required. A value of 3K is recommended.

circuit such as 73S8010.

circuit.

8 Rev. 1.4

Page 9

DS_1210F_001 73S1210F Data Sheet

Pin Name

Pin (68 QFN)

Pin (44 QFN)

Type

Equivalent

Description

Circuit*

PRES 53 34 I Figure 41 Smart Card presence. Active high. Note: the pin has a

very weak pull down resistor. In noisy environments, an external pull down may be desired to insure against a false card event.

CLK 55 36 O Figure 39 Smart Card clock signal. RST 57 38 O Figure 39 Smart Card reset signal. IO 61 42 IO Figure 40 Smart Card Data IO signal. AUX1 60 41 IO Figure 40 Auxiliary Smart Card IO signal (C4). AUX2 59 40 IO Figure 40 Auxiliary Smart Card IO signal (C8). VCC 58 39 PSO

Smart Card VCC supply voltage output. A 0.47µF capacitor is required and should be located at the smart card connector. The capacitor should be a ceramic type with low ESR.

GND 56 37 GND Smart Card Ground. VPC 65 44 PSI Power supply source for main voltage converter circuit. A

10µF and a 0.1µF capacitor are required at the VPC input. The 10µF capacitor should be a ceramic type with low ESR.

VBUS 62 PSI Alternate power source input from external power supply. VBAT 64 PSI Alternate power source input, typically from two series

cells, V > 4V.

VP 54 35 PSO Intermediate output of main converter circuit. Requires an

external 4.7µF low ESR filter capacitor to GND.

LIN 66 1 PSI

Connection to 10µH inductor for internal step up converter. Note: inductor must be rated for 400 mA maximum peak current.

ON_OFF 63 43 I Figure 43 Power control pin. Connected to normally open SPST

switch to ground. Closing switch for duration greater than debounce period will turn 73S1210F on. If 73S1210F is on, closing switch will flag the 73S1210F to go to the off state. Firmware will control when the power is shut down.

OFF_REQ 52 33 O Figure 33 Digital output. If ON_OFF switch is closed (to ground) for

debounce duration and circuit is “on,” OFF_REQ will go high (Request to turn OFF). This output should be connected to an interrupt pin to signal the CPU core that a request to shut down power has been initiated. The firmware can then perform all of its shut down

TBUS(3:0) 0

1 2 3

50 46 44 41

housekeeping duties before shutting down V Trace bus signals for ICE.

Rev. 1.4 9

Page 10

73S1210F Data Sheet DS_1210F_001

GND

Pin Name

Pin (68 Qfn)

Pin (44 QFN)

Type

Equivalent

Description

Circuit*

RXTX 43 27 IO ICE control. ERST 38 23 IO ICE control. ISBR 3 IO ICE control. TCLK 39 24 I ICE control. ANA_IN 15 AI Figure 38 Analog input pin. This signal goes to a programmable

comparator and is used to sense the value of an external voltage.

SEC 2 I Figure 37 Input pin for use in programming security fuse. It should be

connected to ground when not in use. TEST 51 32 DI Figure 37 Test pin, should be connected to ground LED0 4 5 IO Figure 36 Special output driver, programmable pull-down current to

drive LED. May also be used as an input. VDD 68

N/C 7

28 40

3 16 25

PSO

VDD supply output pin. A 0.1µF capacitor is recommended at each VDD pin.

No connect.

8 26 27

9 25 42 67

8 15 26

GND

General ground supply pins for all IO and logic circuits.

RESET 1 4 I Figure 32 Reset input, positive assertion. Resets logic and registers

to default condition. Note: to insure proper reset operation after V

is turned on by application of V

power or

BUS

activation of the ON/OFF switch, external reset circuitry must generate a proper reset signal to the 73S1210F. This can be accomplished via a simple RC network.

* See the figures in the Equivalent Circuits section.

10 Rev. 1.4

Page 11

DS_1210F_001 73S1210F Data Sheet

1.2 Hardware Overview

The 73S1210F single smart card controller integrates all primary functional blocks required to implement a smart card reader. Included on chip are an 8051-compatible microprocessor (MPU) which executes up to one instruction per clock cycle (80515), a fully integrated IS0 7816 compliant smart card interface, expansion smart card interface, serial interface, I2C interface, 6 x 5 keypad interface, RAM , FLASH memory, and a variety of I/O pins.

The power management circuitry provides a 3.3V voltage output (VDD, pin #68) that must be connected to the power supply inputs of the digital core of the circuit, pins # 28 and 40 (these are not internally connected). Should external circuitry require a 3.3V digital power supply, the VDD output i s capable of supplying additional current.

Figure 1 shows a functional block diagram of the 73S1210F.

1.3 80515 MPU Core

1.3.1 80515 Overview

The 73S1210F includes an 80515 MPU (8-bit, 8051-compatible) that performs most instructions in one clock cycle. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (average) improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency.

Actual processor clocking speed can be adjusted to the total processing demand of the application (cryptographic calculations, key management, memory management, and I/O management) using the XRAM special function register MPUCKCtl.

Typical smart card, serial, keyboard and I2C management functions are available for the MPU as part of the Teridian standard library. A standard ANSI “C” 80515-application programming interface library is available to help reduce design cycle. Refer to the 73S12xxF Software User’s Guide.

1.3.2 Memory Organization

The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces. Memory organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas: Program memory (Flash), external data memory (XRAM), and internal data m em ory (IRAM). Data bus address space is allocated to on-chip memory as shown Table 2

Table 2: MPU Data Memory Map

Address

(hex)

0000-7FFF Flash Memory Non-volatile Program and non-volatile data 32KB 0000-07FF Static RAM Volatile MPU data XRAM 2KB

FC00-FFFF External SFR Volatile Peripheral control 1KB

Note: The IRAM is part of the core and is addressed differently.

Program Memory: The 80515 can address up to 32KB of program memory space from 0x0000 to 0xFFFF. Program memory is read when the MPU fetches instructions or performs a MOVC operation. After reset, the MPU starts program execution from location 0x0000. The lower part of the program memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting from 0x0003. Reset is located at 0x0000.

Flash Memory: The program memory consists of flash memory. The flash memory i s intended to primarily contain MPU program code. Flash erasure is initiated by writing a specific data pattern to

Rev. 1.4 11

Memory

Technology

Memory Type Typi cal Usage

Memory Size

(bytes)

Page 12

73S1210F Data Sheet DS_1210F_001

specific SFR registers in the proper sequence. These special pattern/sequence requirements prevent inadvertent erasure of the flash memory.

The mass erase sequence is:

1. Write 1 to the FLSH_MEEN bit in the FLSHCTL register (SFR address 0xB2[1]).

2. Write pattern 0xAA to ERASE (SFR address 0x94). Note: The mass erase cycle can only be initiated when the ICE port is enabled. The page erase sequence is:

1. Write the page address to PGADDR (SFR address 0xB7[7:1]).

2. Write pattern 0x55 to ERASE (SFR address 0x94). The PGADDR register denotes the page address for page erase. The page size is 512 (200h) bytes and

there are 128 pages within the flash memory. The PGADDR denotes the upper seven bits of the flash memory address such that bit 7:1 of the PGADDR corresponds to bit 15:9 of the flash memory address. Bit 0 of the PGADDR is not used and is ignored. The MPU may write to the flash memory. This is one of the non-volatile storage options available to the user. The FLSHCTL SFR bit FLSH_PWE (flash program write enable) differentiates 80515 data store instructions (MOVX@DPTR,A) between Flash and XRAM writes. Before setting FLSH_PWE, all interrupts need to be disabled by setting EAL = 1. Table 3 shows the location and description of the 73S1210 flash-specific SFRs.

Any flash modifications must set the CPUCLK to operate at 3.6923 MHz (MPUCLKCtl = 0x0C) before any flash memory operations are executed to insure the proper timing when modifying the flash memory.

12 Rev. 1.4

Page 13

DS_1210F_001 73S1210F Data Sheet

Initiate Flash Page Erase cycle. Must be proceeded by a write

Table 3: Flash Special Function Registers

R/W Description

Address

ERASE 0x94 W This register is used to initiate either the Flash Mass Erase cycle or the

Flash Page Erase cycle. Specific patterns are expected for ERASE in order to initiate the appropriate Erase cycle (default = 0x00).

0x55 –

to PGADDR @ SFR 0xB7.

0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a write

to FLSH_MEEN @ SFR 0xB2 and the debug port must be enabled.

Any other pattern written to ERASE will have no effect.

PGADDR 0xB7 R/W Flash Page Erase Address register containing the flash memory page

address (page 0 through 127) that will be erased during the Page Erase cycle (default = 0x00). Note: the page address is shifted left by one bit (see detailed description above).

Must be re-written for each new Page Erase cycle.

FLSHCTL 0xB2 R/W

Bit 0 (FLSH_PWE): Program Write Enable: 0 – MOVX commands refer to XRAM Space, normal operation (default).

1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR. This bit is automatically reset after each byte written to flash. Writes to

this bit are inhibited when interrupts are enabled.

W Bit 1 (FLSH_MEEN): Mass Erase Enable:

0 – Mass Erase disabled (default). 1 – Mass Erase enabled.

Must be re-written for each new Mass Erase cycle.

R/W Bit 6 (SECURE):

Enables security provisions that prevent external reading of flash memory and CE program RAM. This bit is reset on chip reset and may only be set. Attempts to write zero are ignored.

Internal Data Memory: The Internal data memory provides 256 bytes (0x00 to 0xF F) of data memory. The internal data memory address is always one byte wide and can be accessed by either direct or indirect addressing. The Special Function Registers occupy the upper 128 bytes. This SFR area is

available only by direct addressing. Indirect addressin g accesses the up per 128 bytes of Internal RAM.

The lower 128 bytes contain working registers and bit-addressable memory. The lower 32 bytes form four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW) select which bank is in use. The next 16 bytes form a block of bit-addressable memory space at bit addresses 0x000x7F. All of the bytes in the lower 128 bytes are accessible through direct or indirect addressing. Table 4 shows the internal data memory map.

Rev. 1.4 13

Page 14

73S1210F Data Sheet DS_1210F_001

Table 4: Internal Data Memory Map

Address Direct Addressing Indirect Addressing

0xFF 0x80

Special Function Registers (SFRs)

RAM

0x7F 0x30

Byte-addressable area

0x2F 0x20 0x1F 0x00

Byte or bit-addressable area

External Data Memory: While the 80515 can address up to 64KB of external data memory in the space from 0x0000 to 0xFFFF, only the memory ranges shown in Figure 2 contain physical memory. The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MO V X @DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX A,@DPTR instruction.

There are two types of instructions, differing in whether they provide an eight-bit or sixteen-bit indi rect address to the external data RAM.

In the first type (MOVX A,@Ri), the contents of R0 or R1, in t he current regist er bank, prov i de the eight lower-ordered bits of address. This method allows the user access to the first 256 bytes of the 2KB of external data RAM. In the second type of MOVX instruction (MOVX A,@DPTR), the data pointer generates a sixteen-bit address.

14 Rev. 1.4

Page 15

DS_1210F_001 73S1210F Data Sheet

Address Use

0x7FFF

Address Use

0xFFFF 0XFF80 0xFF7F

Peripheral Control

Registers (128b)

Smart Card Control

0XFE00 0xFBFF

0x0800

(384b)

–

Use

Address

Flash

Program

Memory

32K

Bytes

0x07FF

XRAM

0xFF 0x80 0x7F 0x48 0x47 0x20 0x1F

Indirect Access Direct Access

Byte RAM SFRs

Byte RAM

Bit/Byte RAM

0x18 0x17

0x10 0x0F

0x08 0x07

0x0000

0x00

Program Memory External Data Memory Internal Data Memory

Figure 2: Memory Map

Dual Data Pointer: The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a

16-bit register that is used to address external memory. In the 80515 core, the standard data pointer i s called DPTR, the second data pointer is called DPTR1. The data pointer select bit chooses the active pointer. The data pointer select bit is located at the LSB of the DPS IRAM special f unct i on regist er (DPS.0). DPTR is selected when DPS.0 = 0 and DPTR1 is selected when DPS.0 = 1.

The user switches between pointers by toggling the LSB of the DPS register. All DPTR-related instructions use the currently selected DPTR for any activity.

The second data pointer may not be supported by certain compilers.

Rev. 1.4 15

Page 16

73S1210F Data Sheet DS_1210F_001

1.4 Program Security

Two levels of program and data security are available. Each level requires a specific fuse to be blown in order to enable or set the specific security mode. Mode 0 security is enabled by setting the SE CURE bi t (bit 6 of SFR register FLSHCTL 0xB2). Mode 0 limits the ICE interface to only allow bulk erase of the flash program memory. All other ICE operations are blocked. This guarantees the security of the user’s MPU program code. Security (Mode 0) is enabled by MPU code that sets the SECURE bit. The M P U code must execute the setting of the SECURE bit immediately af ter a reset to properly enable Mode 0. This should be the first instruction after the reset vector jump has been executed. If the “startup.a51” assembly file is used in an application, then it must be modified to set the SECURE bit after the reset vector jump. If not using “startup.a51”, then this should be the first instructi on in m ain(). O nce security Mode 0 is enabled, the only way to disable it is to perform a global erase of the flash f ol l owed by a full circuit reset. Once the flash has been erased and the reset has been executed, security Mode 0 is disabled and the ICE has full control of the core. The flash can be reprogrammed after the bulk erase operation is completed. Global erase of the flash will also clear the data XRAM memory.

The security enable bit (SECURE) is reset whenever the MPU is reset. Hardware associated with the bit only allows it to be set. As a result, the code may set the SECURE bit to enable the security Mode 0 feature but may not reset it. Once the SECURE bit is set, t he code is prot ected and no external read of program code in flash or data (in XRAM) is possible. In order to invoke the security Mode 0, the SECSET0 (bit 1 of the XRAM SFR register SECReg 0xFFD7) fuse must be blown beforehand or the security mode 0 will not be enabled. The SECSET0 and SECSET1 fuses once blown, cannot be overridden.

Specifically, when SECURE is set:

• The ICE is limited to bulk flash erase only.

• Page zero of flash memory, the preferred location for the user’s preboot code, may not be page-

erased by either MPU or ICE. Page zero may only be erased with global flash erase. Note that global flash erase erases XRAM whether the SECURE bit is set or not.

• Writes to page zero, whether by MPU or ICE, are inhibited. Security mode 1 is in effect when the SECSET1 fuse has been programmed (blown open). In security

mode 1, the ICE is completely and permanently disabled. The Flash program memory and the MPU are not available for alteration, observation, nor control. As soon as the fuse has been blown, the ICE is disabled. The testing of the SECSET1 fuse will occur during the reset and before the start of pre-boot and boot cycles. This mode is not reversible, nor recoverable. In order to blow the SECSET1 f use, the SEC pin must be held high for the fuse burning sequence to be executed properly. The firmware can check to see if this pin is held high by reading the SECPIN bit (bit 5 of XRAM SFR register SECReg 0xFFD7). If this bit is set and the firmware desires, it can blow the SECSET1 f use. The burning of the SECSET0 does not require the SEC pin to be held high.

In order to blow the fuse for SECSET1 and SECSET0, a particular set of register writ es in a specif ic order need to be followed. There are two additional registers that need to have a specific value writt en to them in order for the desired fuse to be blown. These registers are FUSECtl (0xFFD2) and TRIMPCtl (0xFFD1). The sequence for blowing the fuse is as follows:

1. Write 0x54H to FUSECtl.

2. Write 0x81H for security mode 0. Note: only program one security mode at a time. Write 0x82H for security mode 1. Note: SEC pin must be high for security mode 1.

3. Write 0xA6 to TRIMPCtl.

4. Delay about 500 µs.

5. Write 0x00 to TRIMPCtl and FUSECtl.

16 Rev. 1.4

Page 17

DS_1210F_001 73S1210F Data Sheet

Table 5: Program Security Registers

R/W Description

Address

FLSHCTL 0xB2 R/W Bit 0 (FLSH_PWE): Program Write Enable:

0 – MOVX commands refer to XRAM Space, normal operation (default). 1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.

This bit is automatically reset after each byte written to flash. Writes to this bit are inhibited when interrupts are enabled.

W Bit 1 (FLSH_MEEN): Mass Erase Enable:

0 – Mass Erase disabled (default). 1 – Mass Erase enabled.

Must be re-written for each new Mass Erase cycle.

R/W Bit 6 (SECURE):

Enables security provisions that prevent external reading of flash memory and CE program RAM. This bit is reset on chip reset and may only be set. Attempts to write zero are ignored.

TRIMPCtl 0xFFD1 W 0x54 value will set up for security fuse control. All ot her values are

reserved and should not be used.

FUSECtl 0xFFD2 W 0xA6 value will cause t he select ed fuse to be blown. All other values

will stop the burning process.

SECReg 0xFFD7 W Bit 7 (PARAMSEC):

0 – Normal operation. 1 – Enable permanent programming of the security fuses.

R Bit 5 (SECPIN):

Indicates the state of the SEC pin. The SEC pin is held low by a pull-down resistor. The user can force this pin high during boot sequence time to indicate to firmware that sec mode 1 is desired.

R/W Bit 1 (SECSET1):

See the Program Security section.

R/W Bit 0 (SECSET0):

See the Program Security section.

Rev. 1.4 17

Page 18

73S1210F Data Sheet DS_1210F_001

Hex

KCOL

KROW

KSCAN

KSTAT

KSIZE

KORDERL

KORDERH

USR70

UDIR70

ERASE

MCLKCtl

1.5 Special Function Registers (SFRs)

The 73S1210F utilizes numerous SFRs to communicate with the 73S1210Fs many peripherals. This results in the need for more SFR locations outside the direct address IRAM space (0x80 to 0xFF). While some peripherals are mapped to unused IRAM SFR locations, additional SFRs for the smart card and other peripheral functions are mapped to the top of the XRAM data space (0xFC00 to 0xFFFF).

1.5.1 Internal Data Special Function Registers (SFRs)

A map of the Special Function Registers is shown in Table 6.

Table 6: IRAM Special Function Registers Locations

Hex\Bin X000 X001 X010 X011 X100 X101 X110 X111

F8 FF F0 B F7 E8 EF E0 A E7 D8 BRCON DF D0 PSW C8 T2CON CF C0 IRCON C7 B8 IEN1 IP1 S0RELH S1RELH BF B0 A8 IEN0 IP0 S0RELL AF A0 A7 98 S0CON S0BUF IEN2 S1CON S1BUF S1RELL 9F 90 88 TCON TMOD TL0 TL1 TH0 TH1 80 SP DPL DPH DPL1 DPH1 WDTREL PCON 87

Only a few addresses are used, the others are not implemented. SFRs specific to the 73S1210F are shown in bold print (gray background). Any read access to unimplemented addresses will return undefined data, while most write access will have no effect. However, a few locations are reserved and not user configurable in the 73S1210F. Writes to the unused SFR locations can affect the operation

of the core and therefore must not be written to. This applies to all the SFR areas in both the IRAM and XRAM spaces. In addition, all unused bit locations within valid SFR registers must be left in their default (power on default) states.

FLSHCTL

DPS

PGADDR

Bin/

18 Rev. 1.4

Page 19

DS_1210F_001 73S1210F Data Sheet

1.5.2 IRAM Special Function Registers (Generic 80515 SFRs)

Table 7 shows the location of the SFRs and the value they assume at reset or power-up.

Table 7: IRAM Special Function Registers Reset Values

Name Location Reset Value Description

SP 0x81 0x07 Stack Pointer DPL 0x82 0x00 Data Pointer Low 0 DPH 0x83 0x00 Data Pointer High 0 DPL1 0x84 0x00 Data Pointer Low 1 DPH1 0x85 0x00 Data Pointer Hi gh 1 WDTREL 0x86 0x00 Watchdog Timer Reload register PCON 0x87 0x00 Power Control TCON 0x88 0x00 Timer/Counter Control TMOD 0x89 0x00 Timer Mode Control TL0 0x8A 0x00 Timer 0, low byte TL1 0x8B 0x00 Timer 1, high byte TH0 0x8C 0x00 Timer 0, low byte TH1 0x8D 0x00 Timer 1, high byte MCLKCtl 0x8F 0x0A Master Clock Control USR70 0x90 0xFF User Port Data (7:0) UDIR70 0x91 0xFF User Port Direction (7:0) DPS 0x92 0x00 Data Pointer Select Register ERASE 0x94 0x00 Flash Erase S0CON 0x98 0x00 Serial Port 0, Control Register S0BUF 0x99 0x00 Serial Port 0, Data Buffer IEN2 0x9A 0x00 Interrupt Enable Register 2 S1CON 0x9B 0x00 Serial Port 1, Control Register S1BUF 0x9C 0x00 Serial Port 1, Data Buffer S1RELL 0x9D 0x00 Serial Port 1, Reload Register, low byte IEN0 0xA8 0x00 Interrupt Enable Register 0 IP0 0xA9 0x00 Interrupt Priority Regist er 0 S0RELL 0xAA 0xD9 Serial Port 0, Reload Register, low byte FLSHCTL 0xB2 0x00 Flash Control PGADDR 0xB7 0x00 Flash Page Address IEN1 0xB8 0x00 Interrupt Enable Register 1 IP1 0xB9 0x00 Interrupt Priority Regist er 1 S0RELH 0xBA 0x03 Serial Port 0, Reload Register, high byte S1RELH 0xBB 0x03 Serial Port 1, Reload Register, high byte IRCON 0xC0 0x00 Interrupt Request Control Register T2CON 0xC8 0x00 Timer 2 Control PSW 0xD0 0x00 Program Status Word KCOL 0XD1 0x1F Keypad Column

Rev. 1.4 19

Page 20

73S1210F Data Sheet DS_1210F_001

Name Location Reset Value Description

KROW 0XD2 0x3F Keypad Row KSCAN 0XD3 0x00 Keypad Scan Time KSTAT 0XD4 0x00 Keypad Control/Status KSIZE 0XD5 0x00 Keypad Size KORDERL 0XD6 0x00 Keypad Column LS Scan Order KORDERH 0XD7 0x00 Keypad Column MS Scan Order BRCON 0xD8 0x00 Baud Rate Control Register (only BRCON.7 bit used) A 0xE0 0x00 Accumulator B 0xF0 0x00 B Register

1.5.3 External Data Special Function Registers (SFRs)

A map of the XRAM Special Function Registers is shown in Table 8. The smart card registers are listed separately in Table 107.

Table 8: XRAM Special Function Registers Reset Values

Name Location Reset Value Description

DAR 0x FF80 0x00 Device Address Register (I2C)

WDR 0x FF81 0x00 Write Data Register (I SWDR 0x FF82 0x00 Secondary Write Data Register (I RDR 0x FF83 0x00 Read Data Register (I SRDR 0x FF84 0x00 Secondary Read Data Register (I CSR 0x FF85 0x00 Control and Status Register (I USRIntCtl1 0x FF90 0x00 External Interrupt Control 1 USRIntCtl2 0x FF91 0x00 External Interrupt Control 2 USRIntCtl3 0x FF92 0x00 External Interrupt Control 3 USRIntCtl4 0x FF93 0x00 External Interrupt Control 4 INT5Ctl 0x FF94 0x00 External Int errupt Control 5 INT6Ctl 0x FF95 0x00 External Int errupt Control 6 MPUCKCtl 0x FFA1 0x0C MPU Clock Control ACOMP 0x FFD0 0x00 Analog Compare Register TRIMPCtl 0x FFD1 0x00 TRIM Pulse Control FUSECtl 0x FFD2 0x00 FUSE Control VDDFCtl 0x FFD4 0x00 VDDFault Control SECReg 0x FFD7 0x00 Security Register MISCtl0 0x FFF1 0x00 Miscellaneous Control Register 0 MISCtl1 0x FFF2 0x10 Miscellaneous Control Register 1 LEDCtl 0x FFF3 0xFF LED Control Register

Accumulator (ACC, A): ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The mnemonics for accumulator-specific instructions refer to accumulator as “A”, not ACC.

B Register: The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register to hold temporary data.

20 Rev. 1.4

Page 21

DS_1210F_001 73S1210F Data Sheet

Program Status Word (PSW):

Table 9: PSW Register

MSB LSB

CV AC F0 RS1 RS OV – P

Bit Symbol Function

PSW.7 CV Carry flag. PSW.6 AC Auxiliary Carry flag for BCD operations. PSW.5 F0 General purpose Flag 0 available for user. PSW.4 RS1 Register bank select control bits. The contents of RS1 and RS0 select the

working register bank:

RS1/RS0 Bank Selected Location

PSW.3 RS0

00 Bank 0 (0x00 – 0x07) 01 Bank 1 (0x08 – 0x0F) 10 Bank 2 (0x10 – 0x17)

11 Bank 3 (0x18 – 0x1F) PSW.2 OV Overflow flag. PSW.1 F1 General purpose Flag 1 available for user. PSW.0 P Parity flag, affected by hardware to indicate odd / even number of “one” bits

in the Accumulator, i.e. even parity.

Stack Pointer: The stack pointer (SP) is a 1-byte register initialized to 0x07 after reset. This register is incremented before PUSH and CALL instructions, causing the stack to begin at location 0x08.

Data Pointer: The data pointer (DPTR) is 2 bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as a 2-byte register (MOV DPTR,#data16) or as two registers (e.g. MOV DPL,#data8). I t is generally used to access external code or data space (e.g. MOVC A,@A+DPTR or MOVX A,@DPTR respectively).

Program Counter: The program counter (PC) is 2 bytes wide initialized to 0x0000 after reset. This register is incremented during the fetching operation code or when operating on data from program memory. Note: The program counter is not mapped to the SFR area.

Port Registers: The I/O ports are controlled by Special Function Register USR70. The contents of the SFR can be observed on corresponding pins on the chip. Writing a 1 to any of the ports (see Table 10) causes the corresponding pin to be at high level (3.3V), and writing a 0 causes the corresponding pin to be held at low level (GND). The data direction register UDIR70 define individual pins as input or output pins (see the User (USR) Ports section for details).

Table 10: Port Registers

SFR

Address

R/W Description

USR70 0x90 R/W Register for User port bit 7: 0 read and write operations (pins USR0…

USR7).

UDIR70 0x91 R/W Data direction register for User port bits 0:7. Setting a bit to 0 means

that the corresponding pin is an output.

Rev. 1.4 21

Page 22

73S1210F Data Sheet DS_1210F_001

VCO

Phase

Freq DET

CPU CLOCK

DIVIDER

6 bits

MCLK

96MHz

1.5-48MHz MPU CLOCK - CPCLK

SMART CARD LOGIC

BLOCK CLOCK

SCCLK

SCLK

CLOCK

Prescaler 6bits

SC/SCE

CLOCK

Prescaler 6bits

SEL

ETU CLOCK

DIVIDER

12 bits

CPUCKDiv

See SC Clock descriptions for m ore accurate diagram

ETUCLK

MCount(2:0)

KEYCLK

I2CCLK

1kHz

400kHz

DIVIDE

by 120

DIVIDER

/93760

HIGH XTAL

OSC

X12IN

X12OUT

M DIVIDER

/(2*N + 4)

HCLK

HOSCen

12.00MHz

div 2

ICLK

SCCKenb

SELSC

DIVIDE

by 96

CLK1M

1MHz

7.386MHz

3.6923MHz

I2C_2x

800kHz

div 2

SCECLK

div 2

All ports on the chip are bi-directional. Each consists of a Latch (SFR ‘USR70’), an output driver, and an input buffer, therefore the MPU can output or read data through any of these ports if they are not used for alternate purposes.

1.6 Instruction Set

All instructions of the generic 8051 microcontroller are supported. A complete list of the instructi on set and of the associated op-codes is contained in the 73S12xxF Software User’s Guide.

1.7 Peripheral Descriptions

1.7.1 Oscillator and Clock Generation

The 73S1210F has one oscillator circuit for the main CPU clock. The main oscillator circuit is designed to operate with various crystal or external clock frequencies. An internal divider working in conjunction with a PLL and VCO provides a 96MHz internal clock within the 73S1210F. 96 MHz is the recommended frequency for proper operation of specific peripheral blocks such as the specific timers, ISO 7816 UART and interfaces, Step-up converter, and keypad. The clock generation and control circuits are shown in Figure 3.

22 Rev. 1.4

Figure 3: Clock Generation and Control Circuits

Page 23

DS_1210F_001 73S1210F Data Sheet

Bit

Symbol

Function

The master clock control register enables different sections of the clock circuitry and specifies the value of the VCO Mcount divider. The MCLK must be configured to operate at 96MHz to ensure proper operation of some of the peripheral blocks according to the following formula:

MCLK = (Mcount * 2 + 4) * F

= 96MHz

XTAL

Mcount is configured in the MCLKCtl register must be bound between a value of 1 to 10. The possible crystal or external clock frequencies for getting MCLK = 96MHz are shown in Table 11.

Table 11: Frequencies and Mcount Values for MCLK = 96MHz

(MHz) Mcount (N)

XTAL

12.00 2

9.60 3

8.00 4

6.86 5

6.00 6

Master Clock Control Register (MCLKCtl): 0x8F

 0x0A

The MPU clock that drives the CPU core defaults to 3.6923MHz after reset. The MPU clock is scalable by configuring the MPU Clock Control register.

Table 12: The MCLKCtl Register

MSB LSB

HSOEN KBEN SCEN – – MCT.2 MCT.1 MCT.0

MCLKCtl.7 HSOEN

High-speed oscillator disable. When set = 1, disables the high-speed

crystal oscillator and VCO/PLL system. Do not set this bit = 1. MCLKCtl.6 KBEN 1 = Disable the keypad logic clock. MCLKCtl.5 SCEN 1 = Disable the smart card logic clock. MCLKCtl.4 – MCLKCtl.3 – MCLKCtl.2 MCT.2 This value determines the ratio of the VCO frequency (MCLK) to the

MCLKCtl.1 MCT.1 MCLKCtl.0 MCT.0

high-speed crystal oscillator frequency such that:

MCLK = (MCount*2 + 4)* F

. The default value is MCount = 2h such

XTAL

that MCLK = (2*2 + 4)*12.00MHz = 96MHz.

Rev. 1.4 23

Page 24

73S1210F Data Sheet DS_1210F_001

Bit

Symbol

Function

73S1210F

X12IN

X12OUT

12MHz

22pF 22pF

1MΩ

MPU Clock Control Register (MPUCKCtl): 0xFFA1  0x0C

Table 13: The TCON Register

MSB LSB

– – MDIV.5 MDIV.4 MDIV.3 MDIV.2 MDIV.1 MDIV.0

MPUCKCtl.7 – MPUCKCtl.6 – MPUCKCtl.5 MDIV.5 MPUCKCtl.4 MDIV.4 MPUCKCtl.3 MDIV.3 MPUCKCtl.2 MDIV.2 MPUCKCtl.1 MDIV.1 MPUCKCtl.0 MDIV.0

The oscillator circuits are designed to connect directly to standard parallel resonant crystal in a Pierce oscillator configuration. Each side of the crystal should include a 22pF capacitor to ground for both oscillator circuits and a 1MΩ resistor is required across the 12MHz crystal.

This value determines the ratio of the MPU master clock frequency to the

VCO frequency (MCLK) such that

MPUClk = MCLK/(2 * (MPUCKDiv(5:0) + 1)).

Do not use values of 0 or 1 for MPUCKDiv(n).

Default is 0Ch to set CPCLK = 3.6923MHz.

Note: The crystal should be placed as close as possible to the IC, and vias should be avoided.

Figure 4: Oscillator Circuit

24 Rev. 1.4

Page 25

DS_1210F_001 73S1210F Data Sheet

BUS

BAT

BUSTH

SET

CLR

Debounce

Circuit

ON_OFF

DC-DC

Converter

/ Pass

Through*

Delay Circuit (POR)

VPC

VCC

Regulator

LIN

OFF_REQ

INT3

MPU

INT

PWRDN*

*PWRDN bit in MISCtl0

VDD

VCC

Power

Control

VCC Voltage

Select

VCC Enable

Pass Through

Mode Enable

PTEN

SET

CLR

*Pass Through -> VP = VPC

Smart Card Power

To optional external circuits 20mA max.

VDD

Regulator

VDD to Internal Circuits

1.7.2 Power Supply Management

The detailed power supply management logic block diagram is shown in Figure 5.

Figure 5: Detailed Power Management Logic Block Diagram

The 73S1210F contains a power supply and converter circuit that takes power from any one of three

, V

sources; V

is specified to range from 2.7 to 6.5 volts. It can typically be supplied by a singl e cell battery with a

voltage range of 2.7 to approximately 3.1 volts or by a standard supply of 3.3 or 5 volts.

is typically supplied by an external power supply and ranges in value from 4.4 to 5. 5 volts (6.5V maximum).

BUS

, or V

BUS

BAT

Rev. 1.4 25

Page 26

73S1210F Data Sheet DS_1210F_001

is expected to be supplied from a battery of three to four series connected cells with a voltage value

BAT

of 4.0 to 6.5 volts.

and V

BAT

(break-before-make). They will not be enabled at the same time. V

when V

BAT

are internally switched to VPC by two separate FET switches configured as a SPDT switch

BUS

is automatically selected in lieu of

BUS

is present (i.e. V

BUS

always has the priority).

BUS

is provided and either V

If V

pin to prevent current flow from V

BAT

or V

is also used, the source of VPC must be diode isolated from the

BUS

BAT

or V

into the VPC source.

BUS

The power that is supplied to the V up-converted to the intermediate voltage V

pin (externally or internally, i.e. through V

utilizing an inductive, step-up converter. A series power

inductor (nominal value = 10 µH) must be connected from V capacitor must be connected to V

to the pin LIN, and a 10µF low ESR filter

BAT

or V

– see above) is

BUS

requires a 4.7µF filter capacitor and will have a nominal value of 5.5 volts during normal operation. VP

is used internally by the smart card electrical interface circuit and is regulated to the desired smart card supply V

voltage (can be programmed for values of 5V, 3V, or 1.8V).

is also used internally to generate a 3.3V nominal, regulated power supply VDD. VDD is output on pin

68 and must be directly tied to all other V

pins on the 73S1210F (pins 28 and 40). VDD powers all the

digital logic, input/output buffering, and analog functions. It can also be used for external circuitry: up to 20mA current can be supplied to external devices simultaneously to the 73S1210F’s digital core maximum consumption.

1.7.3 Power ON/OFF

The 73S1210F features an ON_OFF input pin for a momentary contact, main-system ON/OFF switch. T he purpose of this switch is to place the circuit in a very low-power mode – the “OFF” mode – where all circuits are no longer powered, therefore allowing the lowest possible current consumption.

When in “OFF” mode, an action on the ON/OFF switch will turn-on the power supply of the digital core

) and apply a power-on-reset condition. Alternatively, entering the “OFF” mode from the “ON” mode

requires firmware action. When in “ON” mode, an action on the ON/OFF switch will send a request to the controller that will have to

be acknowledged (firmware action required) in order to enter the “OFF” state. When placed into the “OFF” state, the 73S1210F will consume minimum current from V

and V

will be unavailable (VDD out = 0V and VP = 0V).

and V

BAT

; VP

When in “ON” mode, the 73S1210F will operate normally, with all the features described in this document available. V

and VDD will be available (VDD out = 3.3V and VP = 5.5V nominal).

Whenever V ON/OFF switch and circuitry are overridden and the 73S1210F is in the “ON” state with V

power is supplied, the circuit will be automatically in the “ON” state. The functions of the

BUS

and VDD available.

Without V

applied, the circuit is by default in the “OFF” state, and will respond only to the ON_OFF pin.

BUS

The ON_OFF pin should be connected to an SPST switch to ground. If the circuit is OFF and the swit ch is closed for a debounce period of 50-100ms, the circuit will go into the “ON” state wherein all functions are operating in normal fashion. If the circuit is in the “ON” state and the ON/OFF pin is connected to ground for a period greater than the debounce period, OFF_REQ will be asserted high and held regardless of the state of ON/OFF. The OFF_REQ signal should be connected to one of the interrupt pins to signal the CPU core that a request to shutdown has been initiated. The firmware will acknowledge this request by setting the SCPWRDN bit in the Smart Card V

Control/Status Register

(VccCtl) high after it has completed all shutdown activities. When SCPWRDN is set high, the circuit will deactivate the smart card interface if required and turn off all analog functions and the V

supply for the

logic and companion circuits. The default state upon application of power is the “OFF” state unless power is supplied to the V

supply. Note that at any time, the firmware may assert SCP WRDN and t he

BUS

26 Rev. 1.4

Page 27

DS_1210F_001 73S1210F Data Sheet

VDDFAULT

Analog functions

(VCO, PLL,

reference and bias

circuits, etc.)

ANALOG

COMPARE

High Speed OSC

MISCtl0 - PWRDN

VDDFCtl - VDDFEN

ACOMP - CMPEN

MCLCKCtl - HOSEN

Smart Card Power

SCVCCCtl - SCPRDN

These are the registers and

the names of the control bits.

These are the block

references.

PWRDN Signal

Note: the PWRDN Signal is not the direct version of the PWRDN Bit. There are delays from assertion of the PWRDN bit to the assertion of the PWRDN Signal (32 MPU clocks). Refer to the Power Down sequence diagram.

Flash Read Pulse

one-shot circuit

MISCtl1 - FRPEN

73S1210F will go into the “OFF” state (when V

is not present). If the ON/OFF switch function is not

BUS

desired and the application does not need to shut down power on VDD, the ON_OFF input can be permanently grounded which will automatically turn on VDD when power is supplied on any of the VPC, VBAT or VBUS power supply inputs.

If power is applied to both V

BAT

and V

source. The 73S1210F will be unconditionally “ON” when V

, the circuit will automatically consume power from only the V

BUS

is applied. If the V

BUS

source is removed,

BUS

the 73S1210F will switchover to the VBAT input supply and remain in the “ON” stat e. The firmware should assert SCPWRDN based on no activity or V When operating from V connecting V

to VP in order to save power.

BUS

, and not calling for VCC, the step-up converter becomes a simple switch

BUS

removal to reduce battery power consumption.

BUS

Note: When the ON_OFF switch function is not needed, i.e. when the 73S1210F must be in an always-ON state when using another supply than VBUS (V

or V

), some external discrete components are needed.

BAT

1.7.4 Power Control Modes

The 73S1210F contains circuitry to disable portions of the device and place it into a lower power standby mode or power down the 73S1210F into its “OFF” mode. The standby mode will stop the core, clock subsystem and the peripherals connected to it. This is accomplished by either shutting off the power or disabling the clock going to the block. The Miscellaneous Control registers MISCtl0, MISCtl1 and the Master Clock Control register (MCLKCtl) provide control over the power modes. The PWRDN bit in

MISCtl0 will setup the 73S1210F for standby or “OFF” modes. Depending on the state of the ON/OFF

circuitry and power applied to the VBUS input, the 73S1210F will go into either st andby mode or power “OFF” mode. If system power is provided by, VBUS or the ON/OFF circuitry is in t he “ON” state, the MPU core will placed into standby mode. If the VBUS input is not sourcing power and the ON/OFF circuit ry is in the “OFF” state, setting the PWRDN bit will shut down the converter and VP will turn of f. The power down mode should only be initiated by setting the PWRDN bit in the MISCtl0 register and not by manipulating individual control bits in various registers. Figure 6 shows how the PWRDN bit controls the various functions that comprise power down state.

Figure 6: Power Down Control

Rev. 1.4 27

Page 28

73S1210F Data Sheet DS_1210F_001

USR[7:0] Control

USRxINTSrc set to

4(ext INT0 high)

6(ext INT0 low)

INT5

INT4

RESETB

CLR

9 BIT CNTR

RESETB

PDMUX (FF94h:bit7)

MPU

INT0

PWRDN_analogQ

CLR

PWRDN (FFF1h:bit7)

USR0

USR6

USR1 USR2 USR3 USR4 USR5

USR7

CLR

5 BIT CNTR

Notes:

1. The counters are clocked by the MPUCLK

2. TC - Terminal count (high at overflow)

3. CE - Count enable

RESETB

When the PWRDN bit is set, the clock subsystem will provide a delay of 32 MPUCLK cycles to allow the program to set the STOP bit in the PCON register. This delay will enable the program to properly halt the core before the analog circuits shut down (high speed oscillator, VCO/PLL, voltage reference and bias circuitry, etc.). The PDMUX bit in SFR INT5Ctl should be set prior to setting the PWRDN bit in order to configure the wake up interrupt logic. The power down mode is de-asserted by any of the interrupts connected to external interrupts 0, 4 and 5 (external USR[0:7], smart card and Key pad). T hese interrupt sources are OR’ed together and routed through some delay logic into INT0 to provide this functionality. The interrupt will turn on the power to all sections that were shut off and start the clock subsystem. After the clock subsystem clocks start running, the MPUCLK begins to clock a 512 count delay counter. When the counter times out, the interrupt will then be active on INT0 and the program can resume. Figure 7 shows the detailed logic for waking up the 73S1210F from a power down state using these specific interrupt sources. Figure 8 shows the timing associated with the power down mode.

28 Rev. 1.4

Figure 7: Detail of Power Down Interrupt Logic

Page 29

DS_1210F_001 73S1210F Data Sheet

PWRDN BIT

PWRDN SIG

EXT. EVENT

INT0 to MPU

MPU STOP

ANALOG Enable

PLL CLOCKS

t0: MPU sets PWRDN bit. t1: 32 MPU clock cycles after t0, the PWRDN SIG is asserted, turning all analog functions OFF. t2: MPU executes STOP instruction, must be done prior to t1.

t3: Analog functions go to OFF condition. No Vref, PLL/VCO, Ibias, etc.

text

text: An external event (RTC, Keypad, Card event, USB) occurs. t4: PWRDN bit and PWRDN signal are cleared by external event. t5: High-speed oscillator/PLL/VCO operating.

t6: After 512 MPU clock cycles, INT0 to MPU is asserted.

t7: INT0 causes MPU to exit STOP condition.

Figure 8: Power Down Sequencing

Rev. 1.4 29

Page 30

73S1210F Data Sheet DS_1210F_001

External Interrupt Control Register (INT5Ctl): 0xFF94  0x00

Table 14: The INT5Ctl Register

MSB LSB

PDMUX – – – – – KPIEN KPINT

Bit Symbol Function

When set = 1, enables interrupts from Keypad (normally going to int5), Smart Card interrupts (normally going to int4), or USR(7:0) pins (int0) to cause interrupt on int0. The assertion of the interrupt to int0 is delayed by

INT5Ctl.7 PDMUX

512 MPU clocks to allow the analog circuits, including the clock system, to stabilize. This bit must be set prior to asserting the PWRDN bit in order to properly configure the interrupts that will wake up the circuit. This bit is

reset = 0 when this register is read. INT5Ctl.6 – INT5Ctl.5 – INT5Ctl.4 – INT5Ctl.3 – INT5Ctl.2 – INT5Ctl.1 KPIEN Keypad interrupt enable. INT5Ctl.0 KPINT Keypad interrupt flag.

Miscellaneous Control Register 0 (MISCtl0): 0xFFF1  0x00

Table 15: The MISCtl0 Register

MSB LSB

PWRDN – – – – – SLPBK SSEL

Bit Symbol Function

This bit sets the circuit into a low-power condition. All analog (high-speed oscillator and VCO/PLL) functions are disabled 32 MPU clock cycles after

MISCtl0.7 PWRDN

this bit is set = 1. This allows time for the next instruction to set t he S T OP bit in the PCON register to stop the CPU core. The MPU is not operative in this mode. When set, this bit overrides the individual control bits that

otherwise control power consumption. MISCtl0.6 – MISCtl0.5 – MISCtl0.4 – MISCtl0.3 – MISCtl0.2 – MISCtl0.1 SLPBK UART loop back testing mode. MISCtl0.0 SSEL Serial port pins select.

30 Rev. 1.4

Page 31

DS_1210F_001 73S1210F Data Sheet

Miscellaneous Control Register 1 (MISCtl1): 0xFFF2  0x10

Table 16: The MISCtl1 Register

MSB LSB

– – FRPEN FLSH66 – – – –

Bit Symbol Function

MISCtl1.7 – MISCtl1.6 –

Flash Read Pulse enable (low). If FRPEN = 1, the Flash Read signal is passed through with no change. When FRPEN = 0 a one-shot circuit that

MISCtl1.5 FRPEN

shortens the Flash Read signal is enabled to save power. The Flash Read pulse will shorten to 40 or 66ns (approximate based on the setting of the FLSH66 bit) in duration, regardless of the MPU clock rate. For MPU clock frequencies greater than 10MHz, this bit should be set high.

MISCtl1.4 FLSH66

When high, creates a 66ns Flash read pulse, otherwise creates a 40ns

read pulse when FRPEN is set. MISCtl1.3 – MISCtl1.2 – MISCtl1.1 – MISCtl1.0 –

Master Clock Control Register (MCLKCtl): 0x8F  0x0A

Table 17: The MCLKCtl Register

MSB LSB

HSOEN KBEN SCEN – – MCT.2 MCT.1 MCT.0

Bit Symbol Function

High-speed oscillator enable. When set = 1, disables the high-speed

MCLKCtl.7 HSOEN*

crystal oscillator and VCO/PLL system. This bit is not changed when the PWRDN bit is set but the oscillator/VCO/PLL is disabled.

MCLKCtl.6 KBEN

1 = Disable the keypad logic clock. This bit is not changed in PWRDN mode but the function is disabled.

1 = Disable the smart card logic clock. This bit is not changed in PWRDN

MCLKCtl.5 SCEN

mode but the function is disabled. Interrupt logic for card insertion/removal

remains operable even with smart card clock disabled. MCLKCtl.4 – MCLKCtl.3 – MCLKCtl.2 MCT.2 This value determines the ratio of the VCO frequency (MCLK) to the

MCLKCtl.1 MCT.1

high-speed crystal oscillator frequency such that:

MCLK = (MCount*2 + 4)*Fxtal. The default value is MCount = 2h such MCLKCtl.0 MCT.0

that MCLK = (2*2 + 4)*12.00MHz = 96MHz.

*Note: The HSOEN bit should never be set under normal circumstances. Power down control should only be initiated via use of the PWRDN bit in MISCtl0.

Rev. 1.4 31

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73S1210F Data Sheet DS_1210F_001

Power Control Register 0 (PCON): 0x87  0x00

The SMOD bit used for the baud rate generator is set up via this register.

Table 18: The PCON Register

MSB LSB

SMOD – – – GF1 GF0 STOP IDLE

Bit Symbol Function

PCON.7 SMOD If SM0D = 1, the baud rate is doubled. PCON.6 – PCON.5 – PCON.4 – PCON.3 GF1 General purpose flag 1. PCON.2 GF0 General purpose flag 1. PCON.1 STOP Sets CPU to Stop mode. PCON.0 IDLE Sets CPU to Idle mode.

32 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

USR

Int

Ctl

USR

Int Ctl

USR

Int Ctl

SCInt

Wait Timeout

Card Event

RxData

TX_Event

Tx_Sent

TX_Error

RX_Error

Card_Det

VCC_OK

CRDCtl

VccCTL

SCIE

VCC_TMR

Analog

Comp

KeyPad

I2C

USR

Int Ctl

int0

int1

USR Pads

USR0

USR7

USR6

USR5

USR4

USR3

USR2

USR1

INT2

INT3

INT

Pads

int2

int3

Serial

Ch 0

Serial

Ch 1

SerChan 0 int

SerChan 1 int

int4

INT5

Ctl

INT6

Ctl

int5

int6

During STOP, IDLE

when PWRDN bit is set

MPU

CORE

VDD_Fault

Delay

Clear PWRDN bit

PDMUXCtl

1.7.5 Interrupts

The 80515 core provides 10 interrupt sources with four priority levels. Each source has its own request flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0, IEN1, and

IEN2. Some of the 10 sources are multiplexed in order to expand the number of interrupt sources.

These are described in more detail in the respective sections. External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of

the 73S1210F, for example the USR I/O, smart card interface, analog comparators, etc. T he external interrupt configuration is shown in Figure 9.

Figure 9: External Interrupt Configuration

Rev. 1.4 33

Page 34

73S1210F Data Sheet DS_1210F_001

1.7.5.1 Interrupt Overview

When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 32. Once the interrupt service has begun, it can only be interrupted by a higher priority interrupt. T he i nterrupt service is terminated by a return from the RETI instruction. When a RETI is performed, the processor will return to the instruction that would have been next when the interrupt occurred.

When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. Thi s bit is set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, then samples are polled by the hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then the interrupt request flag is set. On the nex t instruction cycle, the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector address.

Interrupt response will require a varying amount of time depending on the state of the MPU when t he interrupt occurs. If the MPU is performing an interrupt service with equal or greater priority, the new interrupt will not be invoked. In other cases, the response time depends on the current instruction. The fastest possible response to an interrupt is 7 machine cycles. This includes one machine cycle for detecting the interrupt and six cycles to perform the LCALL.

1.7.5.2 Special Function Registers for Interrupts

Interrupt Enable 0 Register (IEN0): 0xA8  0x00

Table 19: The IEN0 Register

MSB LSB

EAL WDT – ES0 ET1 EX1 ET0 EX0

Bit Symbol Function

IEN0.7 EAL EAL = 0 – disable all interrupts. IEN0.6 WDT Not used for interrupt control. IEN0.5 – IEN0.4 ES0 ES0 = 0 – disable serial channel 0 interrupt. IEN0.3 ET1 ET1 = 0 – disable timer 1 overflow interrupt. IEN0.2 EX1 EX1 = 0 – disable external interrupt 1. IEN0.1 ET0 ET0 = 0 – disable timer 0 overflow interrupt. IEN0.0 EX0 EX0 = 0 – disable external interrupt 0.

34 Rev. 1.4

Page 35

DS_1210F_001 73S1210F Data Sheet

Interrupt Enable 1 Register (IEN1): 0xB8  0x00

Table 20: The IEN1 Register

MSB LSB

– SWDT EX6 EX5 EX4 EX3 EX2 –

Bit Symbol Function

IEN1.7 – IEN1.6 SWDT Not used for interrupt control. IEN1.5 EX6 EX6 = 0 – disable external interrupt 6. IEN1.4 EX5 EX5 = 0 – disable external interrupt 5. IEN1.3 EX4 EX4 = 0 – disable external interrupt 4. IEN1.2 EX3 EX3 = 0 – disable external interrupt 3. IEN1.1 EX2 EX2 = 0 – disable external interrupt 2. IEN1.0 –

Interrupt Enable 2 Register (IEN2): 0x9A  0x00

Table 21: The IEN2 Register

MSB LSB

– – – – – – – ES1

Bit Symbol Function

IEN2.0 ES1 ES1 = 0 – disable serial channel interrupt.

Rev. 1.4 35

Page 36

73S1210F Data Sheet DS_1210F_001

Timer/Counter Control Register (TCON): 0x88  0x00

Table 22: The TCON Register

MSB LSB

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Bit Symbol Function

TCON.7 TF1 Timer 1 overflow flag. TCON.6 TR1 Not used for interrupt control. TCON.5 TF0 Timer 0 overflow flag. TCON.4 TR0 Not used for interrupt control. TCON.3 IE1 Interrupt 1 edge flag is set by hardware when the falling edge on external

interrupt int1 is observed. Cleared when an interrupt is processed.

TCON.2 IT1 Interrupt 1 type control bit. 1 selects falling edge and 0 selects low level for

input pin to cause an interrupt.

TCON.1 IE0 Interrupt 0 edge flag is set by hardware when the falling edge on external

interrupt int0 is observed. Cleared when an interrupt is processed.

TCON.0 IT0 Interrupt 0 type control bit. 1 selects falling edge and 0 sets low level for input

pin to cause interrupt.

Timer/Interrupt 2 Control Register (T2CON): 0xC8  0x00

Table 23: The T2CON Register

MSB LSB

– I3FR I2FR – – – – –

Bit Symbol Function

T2CON.7 –

External interrupt 3 failing/rising edge flag.

T2CON.6 I3FR

I3FR = 0 external interrupt 3 negative transition active.

I3FR = 1 external interrupt 3 positive transition active.

External interrupt 3 failing/rising edge flag.

T2CON.5 I2FR

I2FR = 0 external interrupt 3 negative transition active.

I2FR = 1 external interrupt 3 positive transition active.

T2CON.4 – T2CON.3 – T2CON.2 – T2CON.1 – T2CON.0 –

36 Rev. 1.4

Page 37

DS_1210F_001 73S1210F Data Sheet

Interrupt Request Register (IRCON): 0xC0  0x00

Table 24: The IRCON Register

MSB LSB

– – EX6 IEX5 IEX4 IEX3 IEX2 –

Bit Symbol Function

IRCON.7 – IRCON.6 – IRCON.5 IEX6 External interrupt 6 flag. IRCON.4 IEX5 External interrupt 5 flag. IRCON.3 IEX4 External interrupt 4 flag. IRCON.2 IEX3 External interrupt 3 flag. IRCON.1 IEX2 External interrupt 2 flag. IRCON.0 –

1.7.5.3 External Interrupts

The external interrupts (external to the CPU core) are connected as shown in Table 25. Interrupts with multiple sources are OR’ed together and individual interrupt source control is provided in XRAM SFRs to mask the individual interrupt sources and provide the corresponding interrupt flags. Multifunction USR [7:0] pins control Interrupts 0 and 1. Dedicated external interrupt pins INT2 and INT3 control i nterrupts 2 and 3. The polarity of interrupts 2 and 3 is programmable in the MPU. Interrupt s 4, 5 and 6 have multiple peripheral sources and are multiplexed to one of these three interrupts. The peripheral functions will be described in subsequent sections. Generic 80515 MPU literature states that interrupts 4 through 6 are defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 4, 5 and 6 are converted to rising edge level by the hardware.

SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit that is set by the interrupt hardware and is reset automat i call y by the MPU interrupt handler.

Table 25: External MPU Interrupts

External

Interrupt

Connection Polarity Flag Reset

0 USR I/O High Priority see USRIntCtlx Automatic 1 USR I/O Low Priority see USRIntCtlx Automatic 2 External Interrupt Pin INT2 Edge selectable Automatic 3 External Interrupt Pin INT3 Edge selectable Automatic 4 Smart Card Interrupts N/A Automatic 5 Keypad N/A Automatic 6 I

N/A C, VDD_Fault, Analog Comp Automatic

Note: Interrupts 4, 5 and 6 have multiple interrupt sources and the flag bits are cleared upon reading of the corresponding register. To prevent any interrupts from being ignored, the register containing multipl e interrupt flags should be stored temporary to allow each interrupt flag to be tested separately to see which interrupt(s) is/are pending.

Rev. 1.4 37

Page 38

73S1210F Data Sheet DS_1210F_001

Table 26: Control Bits for External Interrupts

Enable Bit Description Flag Bit Description

EX0 Enable external interrupt 0 IE0 External interrupt 0 flag EX1 Enable external interrupt 1 IE1 External interrupt 1 flag EX2 Enable external interrupt 2 IEX2 External interrupt 2 flag EX3 Enable external interrupt 3 IEX3 External interrupt 3 flag EX4 Enable external interrupt 4 IEX4 External interrupt 4 flag EX5 Enable external interrupt 5 IEX5 External interrupt 5 flag EX6 Enable external interrupt 6 IEX6 External interrupt 6 flag

1.7.5.4 Power Down Interrupt Logic

The 73S1210F contains special interrupt logic to allow INT0 to wake up the CPU from a power down (CPU STOP) state. See the Power Control Modes section for details.

1.7.5.5 Interrupt Priority Level Structure

All interrupt sources are combined in groups, as shown in Table 27.

Table 27: Priority Level Groups

Group

0 External i nterrupt 0 Serial channel 1 interrupt 1 Timer 0 interrupt – External interrupt 2 2 External i nterrupt 1 – External interrupt 3 3 Timer 1 interrupt – External interrupt 4 4 Serial channel 0 interrupt – External interrupt 5 5 – – External interrupt 6

Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the special function register IP0 and one in IP1. If requests of the same priority level are received simultaneously, an internal polling sequence as per Table 31 determines which request is serviced first.

IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has i ts own flag bit that is set by the interrupt hardware and is reset automatically by the MP U interrupt handler.

Interrupt Priority 0 Register (IP0): 0xA9  0x00

Table 28: The IP0 Register

MSB LSB

– WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0

Note: WDTS is not used for interrupt controls.

38 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

Interrupt Priority 1 Register (IP1): 0xB9  0x00

Table 29: The IP1 Register

MSB LSB

– – IP1.5 IP1.4 IP1.3 IP1.2 IP1.1 IP1.0

Table 30: Priority Levels

IP1.x IP0.x Priority Level

0 0 Level0 (lowest) 0 1 Level1 1 0 Level2 1 1 Level3 (highest)

Table 31: Interrupt Polling Sequence

External interrupt 0

Serial channel 1 interrupt

Timer 0 interrupt External interrupt 2 External interrupt 1 External interrupt 3

Timer 1 interrupt

Serial channel 0 interrupt

Polling sequence

External interrupt 4 External interrupt 5 External interrupt 6

1.7.5.6 Interrupt Sources and Vectors

Table 32 shows the interrupts with their associated flags and vector addresses.

Table 32: Interrupt Vectors

Interrupt Request Flag Description Interrupt Vector Address

N/A Chip Reset 0x0000 IE0 External interrupt 0 0x0003 TF0 Timer 0 interrupt 0x000B IE1 External interrupt 1 0x0013 TF1 Timer 1 interrupt 0x001B RI0/TI0 Serial channel 0 interrupt 0x0023 RI1/TI1 Serial channel 1 interrupt 0x0083 IEX2 External interrupt 2 0x004B IEX3 External interrupt 3 0x0053 IEX4 External interrupt 4 0x005B IEX5 External interrupt 5 0x0063 IEX6 External interrupt 6 0x006B

Rev. 1.4 39

Page 40

73S1210F Data Sheet DS_1210F_001

1.7.6 UART

The 80515 core of the 73S1210F includes two separate UARTs that can be programmed to communicate with a host. The 73S1210F can only connect one UART at a time since there is only one set of TX and Rx pins. The MISCtl0 register is used to select which UART is connected to the TX and RX pins. Each UART has a different set of operating modes that the user can select according to their needs. The UART is a dedicated 2-wire serial interface, which can communicate with an external host processor at up to 115,200 bits/s. The TX and RX pins operate at the V exceed 3.6V. The operation of each pin is as follows:

RX: Serial input data is applied at this pin. Conforming to RS-232 standard, the by tes are input LSB first. The voltage applied at RX must not exceed 3.6V.

TX: This pin is used to output the serial data. The bytes are output LSB first. The 73S1210F has several UART-related read/write registers. All UART transfers are programmable for

parity enable, parity select, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 115200 bps. Table 33 shows the selectable UART operation modes and Table 34 shows how the baud rates are calculated.

Table 33: UART Modes

supply voltage levels and should never

Mode 0

Mode 1

Mode 2

Start bit, 8 data bits, stop bit, variable

baud rate (internal baud rate generator

Start bit, 8 data bits, parity, stop bit, fixed

baud rate 1/32 or 1/64 of f

UART 0 UART 1

N/A

Start bit, 8 data bits, parity, stop bit, v ariable

baud rate (internal baud rate generator).

Start bit, 8 data bits, stop bit, variable baud

or timer 1).

CKMPU.

rate (internal baud rate generator).

N/A

Start bit, 8 data bits, parity, stop bit,

Mode 3

variable baud rate (internal baud rate

N/A

generator or timer 1).

Note: Parity of serial data is available through the P flag of the accumulator. Seven-bit serial modes with parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of 8-bit output data. Seven-bit serial modes without parity can be simulated by setting bit 7 to a constant 1. 8-bit serial modes with parity can be simulated by setting and reading the 9th bit, using the control bits S0CON3 and S1CON3 in the S0COn and S1CON SFRs.

Table 34: Baud Rate Generation

Serial Interface 0 Serial Interface 1

smod

Using Timer 1 Using Internal Baud Rate Generator

smod

/ (384 * (256-TH1))

CKMPU

N/A f

2 * f

* f

CKMPU

/(64 * (210-S0REL))

CKMPU

/(32 * (210-S1REL))

Note: S0REL (9:0) and S1REL (9:0) are 10-bit values derived by combining bits from the respective timer reload registers SxRELH (bits 1:0) and SxRELL (bits 7:0). TH1 is the high byte of timer 1. The SMOD bit is located in the PCON SFR.

40 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

Power Control Register 0 (PCON): 0x87  0x00

The SMOD bit used for the baud rate generator is set up via this register.

Table 35: The PCON Register

MSB LSB

SMOD – – – GF1 GF0 STOP IDLE

Bit Symbol Function

Baud Rate Control Register 0 (BRCON): 0xD8  0x00

The BSEL bit used to enable the baud rate generator is set up via this register.

Table 36: The BRCON Register

MSB LSB

BSEL – – – – – – –

Bit Symbol Function

BRCON.7 BSEL

If BSEL = 0, the baud rate is derived using timer 1. If BSEL = 1 the

baud rate generator circuit is used. BRCON.6 – BRCON.5 – . BRCON.4 – BRCON.3 – BRCON.2 – BRCON.1 – BRCON.0 –

Rev. 1.4 41

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73S1210F Data Sheet DS_1210F_001

Miscellaneous Control Register 0 (MISCtl0): 0xFFF1  0x00

Transmit and receive (TX and RX) pin selection and loop back test configuration are setup via this register.

Table 37: The MISCtl0 Register

MSB LSB

PWRDN – – – – – SLPBK SSEL

Bit Symbol Function

MISCtl0.7 PWRDN This bit places the 73S1210F into a power down state. MISCtl0.6 – MISCtl0.5 – MISCtl0.4 – MISCtl0.3 – MISCtl0.2 –

1 = UART loop back testing mode. The pins TXD and RXD are to be

connected together externally (with SLPBK =1) and therefore:

SLPBK SSEL Mode MISCtl0.1 SLPBK

0 0 normal using Serial_0

0 1 normal using Serial_1

1 0 Serial_0 TX feeds Serial_1 RX

1 1 Serial_1 TX feeds Serial_0 RX MISCtl0.0 SSEL

Selects either Serial_1 if set =1 or Serial_0 if set = 0 to be connected to

RXD and TXD pins.

1.7.6.1 Serial Interface 0

The Serial Interface 0 can operate in 4 modes:

• Mode 0 Pin RX serves as input and output. TX outputs the shift clock. 8 bits are transmitted with LSB first.

The baud rate is fixed at 1/12 of the crystal frequency. Reception is initiali zed in M ode 0 by setting the flags in S0CON as follows: RI0 = 0 and REN0 = 1. In other modes, a start bit when REN0 = 1 starts receiving serial data.

• Mode 1 Pin RX serves as input, and TX serves as serial output. No external shift clock is used, 10 bits are

transmitted: a start bit (always 0), 8 data bits (LSB first), and a st op bi t (always 1). On receive, a start bit synchronizes the transmission, 8 data bits are available by reading S0BUF, and stop bit sets the flag RB80 in the Special Function Register S0CON. In mode 1 either internal baud rate generator or timer 1 can be use to specify baud rate.

• Mode 2 This mode is similar to Mode 1, with two differences. The baud rate is fixed at 1/32 or 1/64 of

oscillator frequency and 11 bits are transmitted or received: a start bit (0), 8 data bits (LSB first), a programmable 9th bit, and a stop bit (1). The 9th bit can be used to control the parity of the serial interface: at transmission, bit TB80 in S0CON is output as the 9th bit, and at receiv e, the 9th bit affects RB80 in Special Function Register S0CON.

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DS_1210F_001 73S1210F Data Sheet

Transmit interrupt flag, set by hardware after completion of a serial transfer.

• Mode 3 The only difference between Mode 2 and Mode 3 is that in Mode 3 either internal baud rate generator

or timer 1 can be use to specify baud rate.

The S0BUF register is used to read/write data to/from the serial 0 interface.

Serial Interface 0 Control Register (S0CON): 0x9B  0x00

Transmit and receive data are transferred via this register.

Table 38: The S0CON Register

MSB LSB

SM0 SM1 SM20 REN0 TB80 RB80 TI0 RI0

Bit Symbol Function

S0CON.7 SM0 These two bits set the UART0 mode:

Mode Description SM0 SM1

0 N/A 0 0

S0CON.6 SM1

1 8-bit UART 0 1 2 9-bit UART 1 0

3 9-bit UART 1 1 S0CON.5 SM20 Enables the inter-processor communication feature. S0CON.4 REN0 If set, enables serial reception. Cleared by software to disable reception. S0CON.3 TB80 The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU,

depending on the function it performs (parity check, multiprocessor communication etc.).

S0CON.2 RB80 In Modes 2 and 3 it is the 9th data bit received. In Mode 1, if SM20 is 0,

RB80 is the stop bit. In Mode 0 this bit is not used. Must be cleared by software.

S0CON.1 TI0

Must be cleared by software.

S0CON.0 RI0 Receive interrupt flag, set by hardware after completion of a serial

reception. Must be cleared by software.

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73S1210F Data Sheet DS_1210F_001

1.7.6.2 Serial Interface 1

The Serial Interface 1 can operate in 2 modes:

• Mode A This mode is similar to Mode 2 and 3 of Serial interface 0, 11 bits are transmitted or received: a st art bit

(0), 8 data bits (LSB first), a programmable 9th bit, and a stop bit (1). The 9th bit can be used to control the parity of the serial interface: at transmission, bit TB81 in S1CON is output ted as the 9th bit, and at receive, the 9th bit affects RB81 in Special Function Register S1CON. The only difference between Mode 3 and A is that in Mode A only the internal baud rate generator can be use to specify baud rat e.

• Mode B This mode is similar to Mode 1 of Serial interface 0. Pin RX serves as input, and TX serves as serial

output. No external shift clock is used, 10 bits are transmitted: a start bit (alway s 0), 8 data bits (LSB first), and a stop bit (always 1). On receive, a start bit synchronizes the transmission, 8 data bits are available by reading S1BUF, and stop bit sets the flag RB81 in the Special Funct i on Regist er

S1CON. In mode 1, the internal baud rate generator is use to specify the baud rate.

The S1BUF register is used to read/write data to/from the serial 1 interface.

Serial Interface Control Register (S1CON): 0x9B  0x00

The function of the serial port depends on the setting of the Serial Port Control Register S1CON.

Table 39: The S1CON Register

MSB LSB

SM – SM21 REN1 TB81 RB81 TI1 RI1

Bit Symbol Function

S1CON.7 SM Sets the UART operation mode.

SM Mode Description Baud Rate

0 A 9-bit UART variable

1 B 8-bit UART variable S1CON.6 – S1CON.5 SM21 Enables the inter-processor communication feature. S1CON.4 REN1 If set, enables serial reception. Cleared by software to disable reception. S1CON.3 TB81 The 9th transmitted data bit in Mode A. Set or cleared by the MPU, depending

on the function it performs (parity check, multiprocessor communication, etc.). S1CON.2 RB81 In Mode B, if sm21 is 0, rb81 is the stop bit. Must be cleared by software. S1CON.1 TI1 Transmit interrupt flag, set by hardware after completion of a serial transfer.

Must be cleared by software. S1CON.0 RI1 Receive interrupt flag, set by hardware after completion of a serial reception.

Must be cleared by software.

Multiprocessor operation mode: The feature of receiving 9 bits in Modes 2 and 3 of Serial Interface 0 or in Mode A of Serial Interface 1 can be used for multiprocessor communication. In this case, the slave processors have bit SM20 in S0CON or SM21 in S1CON set to 1. When the master processor outputs slave’s address, it sets the 9th bit to 1, causing a serial port receive interrupt in all the slaves. The slave processors compare the received byte with their network address. If there is a match, the addressed slave will clear SM20 or SM21 and receive the rest of the message, while other slaves will leave the SM20 or SM21 bit unaffected and ignore this message. After addressing the slave, the host will output the rest of the message with the 9th bit set to 0, so no serial port receive interrupt will be generated in unselected slaves.

44 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

1.7.7 Timers and Counters

The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured for counter or timer operations.

In timer mode, the register is incremented every machine cycle, meaning that it count s up after every 12 periods of the MPU clock signal.

In counter mode, the register is incremented when the falling edge is observed at the corresponding input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from USR[0:7] pins, see the User (USR)

Ports section). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count

rate is 1/2 of the oscillator frequency. There are no restrictions on the duty cycle, however t o ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle.

Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers (TMOD and TCON) are used to select the appropriate mode.

The Timer 0 load registers are designated as TL0 and TH0 and the Timer 1 load registers are designated as TL1 and TH1.

Timer/Counter Mode Control Register (TMOD): 0x89

Table 40: The TMOD Register

 0x00

MSB LSB

GATE C/T M1 M0 GATE C/T M1 M0

Timer 1 Timer 0 Bits TR1 and TR0 in the TCON register start their associated timers when set.

Bit Symbol Function

TMOD.7 TMOD.3

Gate If set, enables external gate control (USR pin(s) connected to T0 or T1 for

Counter 0 or 1, respectively). When T0 or T1 is high, and TRx bit is set (see the TCON register), a counter is incremented every falling edge on T0 or T1 input pin. If not set, the TRx bit controls the corresponding timer.

TMOD.6 TMOD.2

C/T Selects Timer or Counter operation. When set to 1, the counter operation is

performed based on the falling edge of T0 or T1. When cleared to 0, the corresponding register will function as a timer.

TMOD.5 TMOD.1

TMOD.4 TMOD.0

M1 Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in the

TMOD description.

M0 Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in the

TMOD description.

Table 41: Timers/Counters Mode Description

M1 M0 Mode Function

0 0 Mode 0 13-bit Counter/Timer. 0 1 Mode 1 16-bit Counter/Timer. 1 0 Mode 2 8-bit auto-reload Counter/Timer. 1 1 Mode 3 If Timer 1 M1 and M0 bits are set to '1', Timer 1 stops. If Timer 0 M1

and M0 bits are set to '1', Timer 0 acts as two independent 8-bit Timer/Counters.

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73S1210F Data Sheet DS_1210F_001

Mode 0

Putting either timer/counter into mode 0 configures it as an 8-bit timer/counter with a di vide-by-32 prescaler. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1’s to all 0’s, it sets the timer overflow flag TF0. The overflow f l ag T F0 then can be used to request an interrupt. The counted input is enabled to the timer when TRx = 1 and either GATE = 0 or T X = 1 (setting GATE = 1 allows the timer to be controlled by external input TX, t o facilitate pulse width measurements). TRx are control bits in the special function register TCON; GATE is in TMOD. The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL0. The upper 3 bits of TL0 are indeterm i nate and should be ignored. Setting the run flag (TRx) does not clear the registers. Mode 0 operation is the same f or timer 0 as for timer 1.

Mode 1

Mode 1 is the same as mode 0, except that the timer register is run with all 16 bits.

Mode 2

Mode 2 configures the timer register as an 8-bit counter (TLx) with automatic reload. The overflow from TLx not only sets TFx, but also reloads TLx with the contents of THx, which is preset by software. The reload leaves THx unchanged.

Mode 3

Mode 3 has different effects on timer 0 and timer 1. Timer 1 in mode 3 simply holds it s count. The effect is the same as setting TR1 = 0. Timer 0 in mode 3 establishes TL0 and TH0 as two separate counters. TL0 uses the timer 0 control bits: C/T, GATE, TR0, INT0, and TF0. TH0 i s locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from timer 1. Thus, TH0 now controls the "timer 1" interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer or count er. When timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and int o its own mode 3, or can still be used by the serial channel as a baud rate generator, or in fact, in any application not requiring an interrupt from timer 1 itself.

Timer/Counter Control Register (TCON): 0x88  0x00

Table 42: The TCON Register

MSB LSB

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Bit Symbol Function

TCON.7 TF1 Timer 1 overflow flag. TCON.6 TR1 Not used for interrupt control. TCON.5 TF0 Timer 0 overflow flag. TCON.4 TR0 Not used for interrupt control.

TCON.3 IE1

TCON.2 IT1

TCON.1 IE0

TCON.0 IT0

Interrupt 1 edge flag is set by hardware when the falling edge on external interrupt int1 is observed. Cleared when an interrupt is processed.

Interrupt 1 type control bit. 1 selects falling edge and 0 selects low level for input pin to cause an interrupt.

Interrupt 0 edge flag is set by hardware when the falling edge on external interrupt int0 is observed. Cleared when an interrupt is processed.

Interrupt 0 type control bit. 1 selects falling edge and 0 sets low level for input pin to cause interrupt.

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DS_1210F_001 73S1210F Data Sheet

1.7.8 WD Timer (Software Watchdog Timer)

The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. After a reset, the watchdog timer is disabled and all registers are set to zero. The watchdog consists of a 16-bit counter (WDT), a reload register (WDTREL), prescalers (by 2 and by 16), and control logic. Once the watchdog starts, it cannot be stopped unless the internal reset signal becomes active.

WD Timer Start Procedure: The WDT is started by setting the SWDT flag. When the WDT register enters the state 0x7CFF, an asynchronous WDTS signal will become active. The signal WDTS sets bit 6 in the IP0 register and requests a reset state. WDTS is cleared either by the reset signal or by changing the state of the WDT timer.

Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request signal from becoming active. This requirement imposes an obligation on the programmer to issue two instructions. The first instruction sets WDT and the second instruction sets SWDT. The maximum delay allowed between setting WDT and SWDT is 12 clock cycles. If this period has expired and SWDT has not been set, WDT is automatically reset, otherwise the watchdog timer is reloaded with the content of the WDTREL

Interrupt Enable 0 Register (IEN0): 0xA8

Bit Symbol Function

 0x00

Table 43: The IEN0 Register

MSB LSB

EAL WDT ET2 ES0 ET1 EX1 ET0 EX0

IEN0.7 EAL EAL = 0 – disable all interrupts. IEN0.6 WDT Watchdog timer refresh flag.

Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT is set to prevent an unintentional refresh of the watchdog timer. WDT

is reset by hardware 12 clock cycles after it has been set. IEN0.5 – IEN0.4 ES0 ES0 = 0 – disable serial channel 0 interrupt. IEN0.3 ET1 ET1 = 0 – disable timer 1 overflow interrupt. IEN0.2 EX1 EX1 = 0 – disable external interrupt 1. IEN0.1 ET0 ET0 = 0 – disable timer 0 overflow interrupt. IEN0.0 EX0 EX0 = 0 – disable external interrupt 0.

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73S1210F Data Sheet DS_1210F_001

Interrupt Enable 1 Register (IEN1): 0xB8  0x00

Table 44: The IEN1 Register

MSB LSB

– SWDT EX6 EX5 EX4 EX3 EX2 –

Bit Symbol Function

IEN1.7 – IEN1.6 SWDT Watchdog timer start/refresh flag. Set to activate/refresh the watchdog timer.

When directly set after setting WDT, a watchdog timer refresh is performed. Bit

SWDT is reset by the hardware 12 clock cycles after it has been set. IEN1.5 EX6 EX6 = 0 – disable external interrupt 6. IEN1.4 EX5 EX5 = 0 – disable external interrupt 5. IEN1.3 EX4 EX4 = 0 – disable external interrupt 4. IEN1.2 EX3 EX3 = 0 – disable external interrupt 3. IEN1.1 EX2 EX2 = 0 – disable external interrupt 2. IEN1.0 –

Interrupt Priority 0 Register (IP0): 0xA9

 0x00

Table 45: The IP0 Register

MSB LSB

– WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0

Bit Symbol Function

IP0.6 WDTS Watchdog timer status flag. Set when the watchdog timer has expired. The

internal reset will be generated, but this bit will not be cleared by the reset. This allows the user program to determine if the watchdog timer caused the reset to occur and respond accordingly. Can be read and cleared by software.

Note: The remaining bits in the IP0 register are not used for watchdog control.

Watchdog Timer Reload Register (WDTREL): 0x86  0x00

Table 46: The WDTREL Register

MSB LSB

WDPSEL WDREL6 WDREL5 WDREL4 WDREL3 WDREL2 WDREL1 WDREL0

Bit Symbol Function

WDTREL.7 WDPSEL WDTREL.6

WDREL6-0

WDTREL.0

Prescaler select bit. When set, the watchdog is clocked through an additional divide-by-16 prescaler.

Seven bit reload value for the high-byte of the watchdog timer. This v al ue i s loaded to the WDT when a refresh is triggered by a consecutive setting of bits WDT and SWDT.

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DS_1210F_001 73S1210F Data Sheet

1.7.9 User (USR) Ports

The 73S1210F includes 8 pins of general purpose digital I/O (GPIO). On reset or power-up, all USR pins are inputs until they are configured for the desired direction. The pins are configured and controlled by the USR70 and UDIR70 SFRs. Each pin declared as USR can be configured independently as an input or output with the bits of the UDIR70 register. Table 47 lists the direction regist ers and confi gurabi li ty associated with each group of USR pins. USR pins 0 to 7 are multiple use pins that can be used for general purpose I/O, external interrupts and timer control. Table 48 shows the configuration for a USR pin through its associated bit in its UDIR register. Values read from and written into the GP IO ports use the data registers USR70. Note: After reset, all USR pins are defaulted as inputs and pull ed up to VDD until any write to the corresponding UDIR register is performed. This insures all USR pins are set to a known value until set by the firmware. Unused USR pins can be set for output if unused and unconnected to prevent them from floating. Alternatively , unused USR pins can be set for input and tied to ground or V

Table 47: Direction Registers and Internal Resources for DIO Pin Groups

USR Pin Group Type

Direction

Name

Direction

(SFR)

Location

Data

Name

Data

(SFR)

Location

USR_0…USR_7 Multi-use UDIR70 0x91 [7:0] USR70 0x90 [7:0]

Table 48: UDIR Control Bit

UDIR Bit

0 1

USR Pin Function

output input

Four XRAM SFR registers (USRIntTCtl0, USRIntTCtl1, USRIntTCtl2, and USRIntTCtl3) control the use of the USR [7:0] pins. Each of the USR [7:0] pins can be configured as GPIO or individually be assigned an internal resource such as an interrupt or a timer/counter control. Each of the four registers contains two 3-bit configuration words named UxIS (where x corresponds to the USR pin). The control resources selectable for the USR pins are listed in Table 50 through Table 53. If more than one input i s connected to the same resource, the resources are combined using a logical OR.

Table 49: Selectable Controls Using the UxIS Bits

UxIS Value Resource Selected for USRx Pin

0 None 1 None 2 T0 (counter0 gate/clock) 3 T1 (counter1 gate/clock) 4 Interrupt 0 rising edge/high level on USRx 5 Interrupt 1 rising edge/high level on USRx 6 Interrupt 0 falling edge/low level on USRx 7 Interrupt 1 falling edge/low level on USRx

Note: x denotes the corresponding USR pin. Interrupt edge or level control is assigned in the IT0 and IT1 bits in the TCON register.

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73S1210F Data Sheet DS_1210F_001

External Interrupt Control Register (USRIntCtl1) : 0xFF90  0x00

Table 50: The USRIntCtl1 Register

MSB LSB

– U1IS.6 U1IS.5 U1IS.4 – U0IS.2 U0IS.1 U0IS.0

External Interrupt Control Register (USRIntCtl2) : 0xFF91  0x00

Table 51: The USRIntCtl2 Register

MSB LSB

– U3IS.6 U3IS.5 U3IS.4 – U2IS.2 U2IS.1 U2IS.0

External Interrupt Control Register (USRIntCtl3) : 0xFF92  0x00

Table 52: The USRIntCtl3 Register

MSB LSB

– U5IS.6 U5IS.5 U5IS.4 – U4IS.2 U4IS.1 U4IS.0

External Interrupt Control Register (USRIntCtl4) : 0xFF93  0x00

Table 53: The USRIntCtl4 Register

MSB LSB

– U7IS.6 U7IS.5 U7IS.4 – U6IS.2 U6IS.1 U6IS.0

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DS_1210F_001 73S1210F Data Sheet

TSEL.2 TSEL.1 TSEL.0 Voltage Threshold

0 0 1.00V

0 1 0 1.40V

1 1 1.50V

1 0 1 2.00V

0 2.30V

1.7.10 Analog Voltage Comparator

The 73S1210F includes a programmable comparator that is connected to the ANA_IN pin. The comparator can be configured to trigger an interrupt if the input voltage rises above or falls below a selectable threshold voltage. The comparator control register should not be modified when the analog interrupt (ANAIEN bit in the INT6Ctl register) is enabled to guard against any false interrupt that might be generated when modifying the threshold. The comparator has a built-in hysteresis to prevent the comparator from repeatedly responding to low-amplitude noise. This hysteresis is approximately 20mV. Interrupt control is handled in the INT6Ctl register.

Analog Compare Control Register (ACOMP): 0xFFD0  0x00

Table 54: The ACOMP Register

MSB LSB

ANALVL – ONCHG CPOL CMPEN TSEL.2 TSEL.1 TSEL.0

Bit Symbol Function

When read, indicates whether the input level is above or below the

ACOMP.7 ANALVL

ACOMP.6 – ACOMP.5 ONCHG

ACOMP.4 CPOL

ACOMP.3 CMPEN

threshold. This is a real time value and is not latched, so it may change from the time of the interrupt trigger until read.

If set, the Ana_interrupt is invoked on any change above or below the threshold, bit 4 is ignored.

If set = 1, Ana_interrupt is invoked when signal rises above selected threshold. If set = 0, Ana_interrupt is invoked when signal goes below selected threshold (default).

Enables power to the analog comparator. 1 = Enabled. 0 = Disabled (default).

ACOMP.2 TSEL.2

ACOMP.1 TSEL.1

Sets the voltage threshold for comparison to the voltage on pin ANA_IN. Thresholds are as follows:

0 0 0 1 1.24V

0 1 0 0 1.75V

ACOMP.0 TSEL.0

1 1 1 1 1 2.50V

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73S1210F Data Sheet DS_1210F_001

External Interrupt Control Register (INT6Ctl): 0xFF95  0x00

Table 55: The INT6Ctl Register

MSB LSB

– – VFTIEN VFTINT I2CIEN I2CINT ANIEN ANINT

Bit Symbol Function

INT6Ctl.7 – INT6Ctl.6 – INT6Ctl.5 VFTIEN VDD fault interrupt enable. INT6Ctl.4 VFTINT VDD fault interrupt flag. INT6Ctl.3 I2CIEN I2C interrupt enabled. INT6Ctl.2 I2CINT I

INT6Ctl.1 ANIEN

C interrupt flag.

If ANIEN = 1 Analog Compare event interrupt is enabled. When masked (ANIEN = 0), ANINT (bit 0) may be set, but no interrupt is generated.

(Read Only) Set when the selected ANA_IN signal changes with respect to

INT6Ctl.0 ANINT

the selected threshold if Compare_Enable is asserted. Cleared on read of register.

52 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

1.7.11 LED Driver

The 73S1210F provides a single dedicated output pin for driving an LED. The LED driver pin can be configured as a current source that will pull to ground to drive an LED that is connected to VDD without the need for an external current limiting resistor. This pin may be used as general purpose output with the programmed pull-down current and a strong (CMOS) pull-up, if enabled. The analog block must be enabled when this output is being used to drive the selected output current.

This pin may be used as an input with consideration of the programmed output current and level. The register bit when read, indicates the state of the pin.

LED Control Register (LEDCtl): 0xFFF3  0xFF

Table 56: The LEDCtl Register

MSB LSB

– LPUEN ISET.1 ISET.0 – – – LEDD0

Bit Symbol Function

LEDCtl.7 – LEDCtl.6 LPUEN 0 = Pull-ups are enabled for all of the LED pins.

These two bits control the drive current (to ground) for the LED driver pin.

LEDCtl.5 ISET.1

LEDCtl.4 ISET.0

LEDCtl.3 – LEDCtl.2 – LEDCtl.1 – LEDCtl.0 LEDD0 Write data controls output level of pin LED0. Read will report level of pin LED0.

Current levels are: 00 = 0ma(off)

01 = 2ma 10 = 4ma 11 = 10ma

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73S1210F Data Sheet DS_1210F_001

1.7.12 I2C Master Interface

The 73S1210F includes a dedicated fast mode, 400kHz I2C Master interface. The I2C interface can read or write 1 or 2 bytes of data per data transfer frame. The MPU communicates with the interface through six dedicated SFR registers:

• Device Address (DAR)

• Write Data (WDR)

• Secondary Write Data (SWDR)

• Read Data (RDR)

• Secondary Read Data (SRDR)

• Control and Status (CSR)

The DAR register is used to set up the slave address and specify if the transaction is a read or write operation. The CSR register sets up, starts the transaction and reports any errors that may occur. When

C transaction is complete, the I2C interrupt is reported via external interrupt 6. The I2C interrupt is

the I automatically de-asserted when a subsequent I clock from the time-base circuits.

1.7.12.1 I2C Write Sequence

To write data on the I2C Master Bus, the 80515 has to program the following registers according to the following sequence:

1. Write slave device address to Device Address register (DAR). The data contains 7 bits for the slave device address and 1 bit of op-code. The op-code bit should be written with a 0 to indicate a write operation.

2. Write data to Write Data register (WDR). This data will be transferred to the slave device.

3. If writing 2 bytes, set bit 0 of the Control and Status regist er (CSR) and load the second data byte t o Secondary Write Data register (SWDR).

4. Set bit 1 of the CSR register to start I

5. Wait for I

C interrupt to be asserted. It indicates that the write on I2C Master Bus is done. Refer to

information about the INT6Ctl, IEN1 and IRCON register for masking and flag operation.

Figure 10 shows the timing of the I

C write mode:

C transaction is started. The I2C interface uses a 400kHz

C Master Bus.

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DS_1210F_001 73S1210F Data Sheet

1-7 8 9 10-17 18

ACK bit

STOP

condition

START

condition

SCL

SDA

LSBMSB LSBMSB

Device Address

[7:0]

Write Data [7:0

I2C_Interrupt

Start I2C

(CSR bit1)

Transfer length

(CSR bit0)

1-7 8 9 10-17 18

ACK bit

STOP

condition

START

condition

SCL

SDA

LSBMSB LSBMSB

Device Address

[7:0]

Write Data [7:0]

I2C_Interrupt

Start I2C

(CSR bit1)

Transfer length

(CSR bit0)

Secondary Write

Data [7:0]

ACK bit

19-26 27

LSBMSB

Figure 10: I

C Write Mode Operation

1.7.12.2 I2C Read Sequence

To read data on the I2C Master Bus from a slave device, the 80515 has to program the following registers in this sequence:

1. Write slave device address to Device Address register (DAR). The data contains 7 bits device address and 1 bit of op-code. The op-code bit should be written with a 1.

2. Write control data to Control and Status register. Write a 1 to bit 1 to st art I a 1 to bit 0 if the Secondary Read Data register (SRDR) is to be captured from the I

3. Wait for I

C interrupt to be asserted. It indicates that the read operation on the I2C bus is done.

C Master Bus. Also write

C Slave device.

Refer to information about the INT6Ctl, IEN1 and IRCON registers for masking and flag operation.

4. Read data from the Read Data register (RDR).

5. Read data from Secondary Read Data register (SRDR) if bit 0 of Control and Status register (CSR) is written with a 1.

Rev. 1.4 55

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73S1210F Data Sheet DS_1210F_001

1-7 8 9 10-17 18

ACK bit

No ACK bit

STOP

condition

START

condition

SCL

SDA

LSBMSB LSBMSB

Device Address

[7:0]

Read Data [7:0

I2c_Interrupt

Start I2C

(CSR bit1)

Transfer length

(CSR bit0)

1-7 8 9 10-17 18

ACK bit

No ACK bit

STOP

condition

START

condition

SCL

SDA

LSBMSB LSBMSB

Device Address

[7:0]

Read Data [7:0]

I2c_Interrupt

Start I2C

(CSR bit1)

Transfer length

(CSR bit0)

Secondary Read

Data[7:0]

ACK bit

19-26 27

Figure 11 shows the timing of the I2C read mode:

Figure 11: I

C Read Operation

56 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

Device Address Register (DAR): 0xFF80  0x00

Table 57: The DAR Register

MSB LSB

DVADR.6 DVADR.5 DVADR.4 DVADR.3 DVADR.2 DVADR.1 DVADR.0 I2CRW

Bit Symbol Function

DAR.7 DAR.6 DAR.5 DAR.4

DVADR

[0:6]

Slave device address. DAR.3 DAR.2 DAR.1 DAR.0 I2CRW If set = 0, the transaction is a write operation. If set=1, read.

I2C Write Data Register (WDR): 0XFF81  0x00

Table 58: The WDR Register

MSB LSB

WDR.7 WDR.6 WDR.5 WDR.4 WDR.3 WDR.2 WDR.1 WDR.0

Bit Function

WDR.7 WDR.6 WDR.5 WDR.4 WDR.3

Data to be written to the I

C slave device.

WDR.2 WDR.1 WDR.0

Rev. 1.4 57

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73S1210F Data Sheet DS_1210F_001

I2C Secondary Write Data Register (S WDR): 0 XFF82  0x00

Table 59: The SWDR Register

MSB LSB

SWDR.7 SWDR.6 SWDR.5 SWDR.4 SWDR.3 SWDR.2 SWDR.1 SWDR.0

Bit Function

SWDR.7 SWDR.6 SWDR.5 SWDR.4 SWDR.3

Second Data byte to be written to the I2C slave device if bit 0 (I2CLEN) of the Control and Status register (CSR) is set = 1.

SWDR.2 SWDR.1 SWDR.0

I2C Read Data Register (RDR): 0XFF83  0x00

Table 60: The RDR Register

MSB LSB

RDR.7 RDR.6 RDR.5 RDR.4 RDR.3 RDR.2 RDR.1 RDR.0

Bit Function

RDR.7 RDR.6 RDR.5 RDR.4 RDR.3

Data read from the I

C slave device.

RDR.2 RDR.1 RDR.0

58 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

I2C Secondary Read Data Register (SRDR): 0XFF84  0x00

Table 61: The SRDR Register

MSB LSB

SRDR.7 SRDR.6 SRDR.5 SRDR.4 SRDR.3 SRDR.2 SRDR.1 SRDR.0

Bit Function

SRDR.7 SRDR.6 SRDR.5 SRDR.4 SRDR.3

Second Data byte to be read from the I2C slave device if bit 0 (I2CLEN) of the Control and Status register (CSR) is set = 1.

SRDR.2 SRDR.1 SRDR.0

I2C Control and Status Register (CSR): 0xFF85  0x00

Table 62: The CSR Register

MSB LSB

– – – – – AKERR I2CST I2CLEN

Bit Symbol Function

CSR.7 – CSR.6 – CSR.5 – CSR.4 – CSR.3 –

CSR.2 AKERR

CSR.1 I2CST

Set to 1 if acknowledge bit from Slave Device is not 0. Automati cally reset

when the new bus transaction is started.

Write a 1 to start I

C transaction. Automatically reset to 0 when the bus transaction is done. This bit should be treated as a “busy” indicator on reading. If it is high, the serial read/write operations are not completed and no new address or data should be written.

CSR.0 I2CLEN Set to 1 for 2 byte read or write operations. Set to 0 for 1-byte operations.

Rev. 1.4 59

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73S1210F Data Sheet DS_1210F_001

External Interrupt Control Register (INT6Ctl): 0xFF95  0x00

Table 63: The INT6Ctl Register

MSB LSB

– – VFTIEN VFTINT I2CIEN I2CINT ANIEN ANINT

Bit Symbol Function

INT6Ctl.7 – INT6Ctl.6 – INT6Ctl.5 VFTIEN VDD fault interrupt enable. INT6Ctl.4 VFTINT VDD fault interrupt flag. INT6Ctl.3 I2CIEN When set = 1, the I2C interrupt is enabled.

INT6Ctl.2 I2CINT

When set = 1, the I2C transaction has completed. Cleared upon the start of a subsequent I

C transaction. INT6Ctl.1 ANIEN Analog compare interrupt enable. INT6Ctl.0 ANINT Analog compare interrupt flag.

60 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

Scan

pull-up

Debouncing

Debounce Time

KSIZE Register

(1) KCOL is normally used as Read only register. When hardware keyscan mode is disabled, this register is to be used by firmware to write the column data to handle firmware scanning.

Key_Detect

Hardware Scan Enable

Column

Scan Order

Column Value

Row Value

Key_Detect_Enable

KORDERL / H Registers

KCOL Register

(1)

KROW Register

Dividers

1kHz

Scan

Time

KSCAN Register

KSTAT Register

Keypad Clock

VDD

pull-

COL4:0

ROW5:0

73S1210F

If smaller keypad than 6 x 5 is to be implemented, unused row inputs should be connected to VDD. Unused column outputs should be left unconnected.

VDD

1.7.13 Keypad Interface

The 73S1210F supports a 30-button (6 rows x 5 columns) keypad (SPST Mechanical Contact Switches) interface using 11 dedicated I/O pins. Figure 12 shows a simplified block diagram of the keypad interface.

There are five drive lines (outputs) corresponding to columns and 6 sense lines (inputs) corresponding to rows. Hysteresis and pull-ups are provided on all inputs (rows), which eliminate the need for external resistors in the keypad. Key scanning happens by asserting one of the 5 column lines low and looking for a low on a sense line indicating that a key is pressed (switch closed) at the intersection of the drive/sense (column/row) line in the keypad. Key detection is performed by hardware with an incorporated debounce timer. Debouncing time is adjustable through the KSCAN register. Internal hardware circuitry performs column scanning at an adjustable scanning rate and column scanning order through registers KSCAN and KORDERL / KORDERH. Key scanning is disabled at reset and must be enabled by fi rm ware. When a valid key is detected, an interrupt is generated and the valid value of t he pressed key is automatically

Rev. 1.4 61

Figure 12: Simplified Keypad Block Diagram

Page 62

73S1210F Data Sheet DS_1210F_001

written into the KCOL and KROW registers. The keypad interface uses a 1kHz clock derived from the 12MHz crystal. The clock is enabled by setting bit 6 – KBEN – in the MCLKCtl register (see the Oscillator

and Clock Generation section) to carry out scanning and debouncing. The keypad size can be adjusted

within the KSIZE register. Normal scanning is performed by hardware when the SCNEN bit is set at 1 in the KSTAT register. Figure

13 shows the flowchart of how the hardware scanning operates. In order to minimize power, scanning

does not occur until a key-press is detected. Once hardware key scanning is enabled, the hardware drives all column outputs low and waits for a low to be detected on one of the inputs. When a low i s detected on any row, and before key scanning starts, the hardware checks that the low level is still detected after a debounce time. The debounce time is defined by firmware in the KSCAN register (bits 7:0, DBTIME). Debounce times from 4ms to 256ms in 4ms increments are supported. If a key i s not pressed after the debounce time, the hardware will go back to looking for any input to be low. If a key is confirmed to be pressed, key scanning begins.

Key scanning asserts one of the 5 drive lines (COL 4:0) low and looks for a low on a sense line indicating that a key is pressed at the intersection of the drive/sense line in the keypad. After all sense lines have been checked without a key-press being detected, the next column line is asserted. The time between checking each sense line is the scan time and is defined by firmware in the KSCAN register (bits 0:1 – SCTIME). Scan times from 1ms to 4ms are supported. Scanning order does not affect t he scan t im e. This scanning continues until the entire keypad is scanned. If only one key is pressed, a valid key is detected. Simultaneous key presses are not considered as valid (If two keys are pressed, no key is reported to firmware).

Possible scrambling of the column scan order is provided by means of the KORDERL and KORDERH registers that define the order of column scanning. Values in these registers must be updated every time a new keyboard scan order is desired. It is not possible to change the order of scanning the sense lines. The column and row intersection for the detected valid key are stored in the KCOL and KROW registers. When a valid key is detected, an interrupt is generated. Firmware can then read those registers to determine which key had been pressed. After reading the KCOL and KROW registers, the firmware can update the KORDERL / KORDERH registers if a new scan order is needed. When the SCNEN bit is enabled in the KSTAT register, the KCOL and KROW registers are only updated after a valid key has been identified. The hardware does not wait for the firmware to service the interrupt i n order to proceed with the key scanning process. Once the valid key (or invalid key – e.g. two keys pressed) is detected, the hardware waits for the key to be released. Once the key is released, the debounce timer is started. I f the key is not still released after the debounce time, the debounce counter starts again. After a key release, all columns will be driven low as before and the process will repeat waiting for any key to be pressed. When the SCNEN bit is disabled, all drive outputs are set to the value in t he KCOL register. If firmware clears the SCNEN bit in the middle of a key scan, the KCOL register contains the last value stored in there which will then be reflected on the output pins. A bypass mode is provided so that the firmware can do the key scanning manually (SCNEN bit must be cleared). In bypass mode, the firmware writes/reads the Column and Row registers to perform the key scanning.

62 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

Any

Row

Input = 0 ?

Keypad

Initialization

All Column

Outputs = 0

Deboucing

Timer

Any Row

Input still = 0 ?

Yes

How Many

keys have been

detected?

Download of the key row and column values in KROW and

KCOL registers

1 key

Keypad Interrupt

generation

Is (are)

the key(s)

released ?

(*)

Deboucing

Timer

Yes

Is (are)

the key(s)

still released ?

(*)

KSCAN Register: Debouncing Time

KSTAT Register:

Enable HW Scanning

Enable Keypad Interrupt

Keypad Scanning

KORDERL / H Registers:

Column Scan Order

KSTAT Register:

Key Detect Interrupt

Yes

KCOL Register:

Value of the valid key column

KROW Register:

Value of the valid key row

KSCAN Register:

Scanning Rate

KSIZE Register:

Keypad Size Definition

0 key

than

1 key

KSCAN Register:

Debouncing Time

(*) Key release is cheked by looking for a low level on any row.

Figure 13: Keypad Interface Flow Chart

Rev. 1.4 63

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73S1210F Data Sheet DS_1210F_001

Keypad Column Register (KCOL): 0xD1  0x1F

This register contains the value of the column of a key detected as valid by the hardware. In bypass mode, this register firmware writes directly this register to carry out manual scanning.

Table 64: The KCOL Register

MSB LSB

– – – COL.4 COL.3 COL.2 COL.1 COL.0

Bit Symbol Function

KCOL.7 – KCOL.6 – KCOL.5 – KCOL.4 COL.4 KCOL.3 COL.3 KCOL.2 COL.2 KCOL.1 COL.1

Drive lines bit mapped to corresponding with pins COL(4:0). When a key is detected, firmware reads this register to determine column. In bypass (S/W keyscan) mode, Firmware writes this register directly. 0x1E = COL(0) low, all others high. 0x0F = COL(4) low, all others high. 0x1F = COL(4:0) all high.

KCOL.0 COL.0

Keypad Row Register (KROW): 0xD2  0x3F

This register contains the value of the row of a key detected as valid by the hardware. In bypass mode, this register firmware reads directly this register to carry out manual detection.

Table 65: The KROW Register

MSB LSB

– – ROW.5 ROW.4 ROW.3 ROW.2 ROW.1 ROW.0

Bit Symbol Function

KROW.7 – KROW.6 – KROW.5 ROW.6 KROW.4 ROW.4 KROW.3 ROW.3 KROW.2 ROW.2 KROW.1 ROW.1

Sense lines bit mapped to correspond with pins ROW(5:0). When key detected, firmware reads this register to determine row. In bypass mode, firmware reads rows and has to determine if there was a key press or not. 0x3E = ROW(0) low, all others high. 0x1F = ROW(5) low, all others high. 0x3F = ROW(5:0) all high.

KROW.0 ROW.0

64 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

Keypad Scan Time Register (KSCAN): 0xD3  0x00

This register contains the values of scanning time and debouncing time.

Table 66: The KSCAN Register

MSB LSB

DBTIME.5 DBTIME.4 DBTIME.3 DBTIME.2 DBTIME.1 DBTIME.0 SCTIME.1 SCTIME.0

Bit Symbol Function

KSCAN.7 DBTIME.5 KSCAN.6 DBTIME.4 KSCAN.5 DBTIME.3 KSCAN.4 DBTIME.2

Debounce time in 4ms increments. 1 = 4ms de-bounce time, 0x3F = 252ms, 0x00 = 256ms. Key presses and key releases are debounced by this amount of time.

KSCAN.3 DBTIME.1 KSCAN.2 DBTIME.0 KSCAN.1 SCTIME.1 KSCAN.0 SCTIME.0

Scan time in ms. 01 = 1ms, 02 = 2ms, 00 = 3ms, 00 = 4ms. Time between checking each key during keypad scanning.

Keypad Control/Status Register (KSTAT): 0xD4  0x00

This register is used to control the hardware keypad scanning and detection capabilities, as well as the keypad interrupt control and status.

Table 67: The KSTAT Register

MSB LSB

– – – – KEYCLK HWSCEN KEYDET KYDTEN

Bit Symbol Function

KSTAT.7 – KSTAT.6 – KSTAT.5 – KSTAT.4 – KSTAT.3 KEYCLK The current state of the keyboard clock can be read from this bit.

Hardware Scan Enable – When set, the hardware will perform automatic

KSTAT.2 HWSCEN

key scanning. When cleared, the firmware must perform the key scanning manually (bypass mode).

Key Detect – When HWSCEN = 1, this bit is set causing an interrupt that indicates a valid key press was detected and the key location can be read from the Keypad Column and Row registers. When HWSCEN = 0, this bit

KSTAT.1 KEYDET

is an interrupt which indicates a falling edge on any Row input if all Row inputs had been high previously (note: multiple Key Detect interrupts may occur in this case due to the keypad switch bouncing). In all cases, this bit is cleared when read. When HWSCEN = 0 and the keypad interface 1kHz clock is disabled, a key press will still set this bit and cause an interrupt.

Key Detect Enable – When set, the KEYDET bit can cause an interrupt and

KSTAT.0 KYDTEN

when cleared the KEYDET cannot cause an interrupt. KEYDET can still get set even if the interrupt is not enabled.

Rev. 1.4 65

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73S1210F Data Sheet DS_1210F_001

Keypad Scan Time Register (KSIZE): 0xD5  0x00

This register is not applicable when HWSCEN is not set. Unused row inputs should be connected to VDD.

Table 68: The KSIZE Register

MSB LSB

– – ROWSIZ.2 ROWSIZ.1 ROWSIZ.0 COLSIZ.2 COLSIZ.1 COLSIZ.0

Bit Symbol Function

KSIZE.7 – KSIZE.6 – KSIZE.5 ROWSIZ.2 KSIZE.4 ROWSIZ.1 KSIZE.3 ROWSIZ.0 KSIZE.2 COLSIZ.2 KSIZE.1 COLSIZ.1 KSIZE.0 COLSIZ.0

Defines the number of rows in the keypad. Maximum number is 6 given the number of row pins on the package. Allows for a reduced keypad size for scanning.

Defines the number of columns in the keypad. Maximum number is 5 given the number of column pins on the package. Allows for a reduced keypad size for scanning.

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DS_1210F_001 73S1210F Data Sheet

Keypad Column LS Scan Order Register (KORDERL): 0xD6  0x00

In the KORDERL and KORDERH registers, Column Scan Order(14:0) is grouped into 5 sets of 3 bit s each. Each set determines which column (COL(4:0) pin) to activate by loading the column number into the 3 bits. When in HW_Scan_Enable mode, the hardware will step through the sets from 1Col to 5Col (up to the number of columns in Colsize) and scan the column defined in the 3 bits. To scan in sequential order, set a counting pattern with 0 in set 0, and 1 in set 1,and 2 in set 2, and 3 in set 3, and 4 in set 4. The firmware should update this as part of the interrupt service routine so that the new scan order is loaded prior to the next key being pressed. For example, to scan COL(0) first, 1Col(2:0) should be loaded with 000’b. To scan COL(4) fifth, 5Col(2:0) should be loaded with 100’b.

Table 69: The KORDERL Register

MSB LSB

3COL.1 3COL.0 2COL.2 2COL.1 2COL.0 1COL.2 1COL.1 1COL.0

Bit Symbol Function

KORDERL.7 3COL.1 KORDERL.6 3COL.0

Column to scan 3

(lsb’s).

KORDERL.5 2COL.2

Column to scan 2

. KORDERL.4 2COL.1 KORDERL.3 2COL.0 KORDERL.2 1COL.2

Column to scan 1

. KORDERL.1 1COL.1

KORDERL.0 1COL.0

Keypad Column MS Scan Order Register (KORDERH): 0xD7  0x00

Table 70: The KORDERH Register

MSB LSB

– 5COL.2 5COL.1 5COL.0 4COL.2 4COL.1 4COL.0 3COL.2

Bit Symbol Function

KORDERH.7 – KORDERH.6 5COL.2

Column to scan 5

. KORDERH.5 5COL.1 KORDERH.4 5COL.0 KORDERH.3 4COL.2

Column to scan 4

. KORDERH.2 4COL.1 KORDERH.1 4COL.0 KORDERH.0 3COL.2 Column to scan 3

(msb).

Rev. 1.4 67

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73S1210F Data Sheet DS_1210F_001

External Interrupt Control Register (INT5Ctl): 0xFF94  0x00

Table 71: The INT5Ctl Register

MSB LSB

PDMUX – – – – – KPIEN KPINT

Bit Symbol Function

INT5Ctl.7 PDMUX Power down multiplexer control. INT5Ctl.6 – INT5Ctl.5 – INT5Ctl.4 – INT5Ctl.3 – INT5Ctl.2 – INT5Ctl.1 KPIEN Enables Keypad interrupt when set = 1.

INT5Ctl.0 KPINT

This bit indicates the Keypad logic has set Key_Detect bit and a key location may be read. Cleared on read of register.

1.7.14 Emulator Port

The emulator port, consisting of the pins E_RST, E_TCLK and E_RXTX, provides control of the MPU through an external in-circuit emulator. The E_TBUS[3:0] pins, together wit h the E_ISYNC/BRKRQ, add trace capability to the emulator. The emulator port is compatible with the ADM51 emulators manufactured by Signum Systems™.

The signals of the emulator port have weak pull-ups. Adding resistor footprints for signals E_RST, E_TCLK and E_RXTX on the PCB is recommended. If necessary, adding 10kΩ pull-up resistors on E_TCLK and E_RXTX and a 3kΩ on E_RST will help the emulator operate normally i f a problem arises. If code trace capability is needed on this interface, 20pF capacitors ( (to ground) need to be added to allow the trace function capability to run properly. These capacitors should be attached to the TBUS0:3 and ISBR signals.

68 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

Direct Mode

Card

Insertion

Activation /

Deactivation

Sequencer

VCC

Buffer / Level

Shifter

RST

Buffer / Level

Shifter

CLK

I/O

Buffer / Level

Shifter

Buffer / Level

Shifter

Buffer / Level

Shifter

VCC Card

Generation

ICC Event

ICC Pwr_event

I/O ICC#1

I/OExt. ICC

CLK ICC

CLKExt. ICC

Card Clock

Management

7.2MHz

SCCLK/

SCSCLK

PRES

Serial UART

Internal ICC Interface

SCSel

UART

T=0 T=1

RLength

STSTO

ATRMsB/LsB

BGT/EGT

SRXData

SRXCtl

STXData

STXCtl

SCPrtcol

SCCtl

FDReg

SByteCtl

SParCtl

Card Interrupt

Management

SCInt

SCIE

External ICC Interface

Bypass

Mode

XRAM Registers

VccCtl/

VccTMR

SCCLK/SCSCLK

Timers

2-Byte

Tx FIFO

2-Byte

Rx FIFO

Card and

Mode

Selection

SCDir

SCECtl

BGT0/1/2/3/

CWT0/1

SIO

SCLK

SCCLK

SCSCLK

1.7.15 Smart Card Interface Function

The 73S1210F integrates one ISO-7816 (T=0, T=1) UART, one complete ICC electrical interface as well as an external smart card interface to allow multiple smart cards to be connected using the Teridian 8010 family of interface devices. Figure 14 shows the simplified block diagram of the card circuitry (UART + interfaces), with detail of dedicated XRAM registers.

Figure 14: Smart Card Interface Block Diagram

Card interrupts are managed through two dedicated registers: SCIE (Interrupt Enable to define which interrupt is enabled) and SCInt (Interrupt status). They allow the firmware to determine the source of an interrupt, that can be a card insertion / removal, card power fault, or a transmission (TX) or reception (RX) event / fault. It should be noted that even when card clock is disabled, an ICC int errupt can be generat ed

Rev. 1.4 69

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73S1210F Data Sheet DS_1210F_001

73S1210F

73S8010

SC3

SC2

73S8010

SC(n)

SC1

INT3 SDA

SCL

INT

SCL SDA

INT

SCL SDA

INT

SCL SDA

SAD(0:2)

I/O

RST CLK

C4 C8

VPC

PRES

IOUC

XTALIN

GND

PRES

VPC

PRES

SIO

SCLK

VCC

on a card insertion / removal to allow power saving modes. Card insertion / removal is generated from the respective card switch detection inputs (whose polarity is programmable).

The built-in ICC Interface has a linear regulator (V cards in accordance with the ISO 7816-3 and EMV4.1 standards. This converter uses the V

generator) capable of driving 1.8, 3.0 and 5.0V smart

(5.5V

nominal) input supply source. See the power supply management section above for more detail. Auxiliary I/O lines C4 and C8 are only provided for the built-in interface. I f support for the auxiliary lines is necessary for the external smart card interface, they need to be handled manually through t he US R GP IO pins. The external 73S8010x devices directly connect the I/O (SIO) and clock (SCLK) signals and control is handled via the I

C interface.

Figure 15 shows how multiple 8010 devices can be connected to the 73S1210F.

Figure 15: External Smart Card Interface Block Diagram

70 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

1.7.15.1 ISO 7816 UART

An embedded ISO 7816 (hardware) UART is provided to control communications between a smart card and the 73S1210F MPU. The UART can be shared between the one built-in ICC interface and the external ICC interface. Selection of the desired interface is made by register SCSel. Control of the external interface is handled by the I

C interface for any external 73S8010x device. The following is a list

of features for the ISO 7816 UART:

• Two-byte FIFO for temporary data storage on both TX and Rx data.

• Parity checking in T=0. This feature can be enabled/disabled by firmware. Parity error reporting to

firmware and Break generation to ICC can be controlled independently.

• Parity error generation for test purposes.

• Retransmission of last byte if ICC indicates T=0 parity error. This feature can be enabled/disabled by

firmware.

• Deletion of last byte received if ICC indicates T=0 parity error. This feature can be enabled/disabled by firmware.

• CRC/LRC generation and checking. CRC/LRC is automatically inserted into T=1 data stream by the hardware. This feature can be enabled/disabled by firmware.

• Support baud rates: 115200, 57600, 38400, 28800, 19200, 14400, 9600 under firmware control (assuming 12MHz crystal) with various F/D settings.

• Firmware manages F/D. All F/D combinations are supported in which F/D is directly divisible by 31 or 32 (i.e. F/D is a multiple of either 31 or 32).

• Flexible ETU clock generation and control.

• Detection of convention (direct or indirect) character TS. This affects both polarity and order of bits in

byte. Convention can be overridden by firmware.

• Supports WTX Timeout with an expanded Wait Time Counter (28 bits).

• A Bypass Mode is provided to bypass the hardware UART in order for the software to emulate the

UART (for non-standard operating modes). In such a case, the I/O line value is reflected in S F R

SCCtl or SCECtl respectively for the built-in or external interfaces. This mode is appropriate for some

synchronous and non T=0 / T=1 cards.

The single integrated smart card UART is capable of supporting T=0 and T=1 cards in hardware therefore offloading the bit manipulation tasks from the firmware. The embedded f i rmware instructs the hardware which smart card it should communicate with at any point in time. Firmware reconfigures the UART as required when switching between smart cards. When the 73S1210F has transmitted a message with an expected response, the firmware should not switch the UART to another smart card until the first smart card has responded. If the smart card responds while another smart card is selected, that first smart card’s response will be ignored.

Rev. 1.4 71

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73S1210F Data Sheet DS_1210F_001

VCCSEL

bits

VCC

VCCOK bit

RSTCRD bit

RST

CLK

tto

See Note

ATR starts

SELSC

bits

1.7.15.2 Answer to Reset Processing

A card insertion event generates an interrupt to the firmware, which is then responsible for the configuration of the electrical interface, the UART and activation of the card. The activation sequencer goes through the power up sequence as defined in the ISO 7816-3 specification. An asynchronous activation timing diagram is shown in Figure 16. After the card reset is de-asserted, the firmware instructs the hardware to look for a TS byte that begins the ATR response. If a response is not provided within the pre-programmed timeout period, an interrupt is generated and the firmware can then take appropriate action, including instructing the 73S1210F to begin a deactivation sequence. Once commanded, the deactivation sequencer goes through the power down sequence as defined in the ISO 7816-3 specification. If an ATR response is received, the hardware looks for a TS byte that determines direct/inverse convention. The hardware handles the indirect convention conversion such that the embedded firmware only receives direct convention. This feature can be disabled by firmware within SByteCtl register. Parity checking and break generation is performed on the TS byte unless disabled by firmware. If during the card session, a card removal, over-current or other error event is detected, the hardware will automatically perform the deactivation sequence and then generate an interrupt to the firmware. The firmware can then perform any other error handling required for proper system operation. Smart card RST, I/O and CLK, C4, C8 shall be low before the end of the deactivation sequence. Figure 17 shows the timing for a deactivation sequence.

t1: SELSC.1 bit set (selects internal ICC interface) and a non-zero value in VCCSEL bits (calling for a value of Vcc of 1.8, 3.0, or 5.0 volts) will begin the activation sequence. t1 is the time for Vcc to rise to acceptable level, declared as Vcc OK (bit VCCOK gets set). This time depends on filter capacitor value and card Icc load.

tto: The time allowed for Vcc to rise to Vcc OK status after setti ng of the VCCSEL bits. This time is generated by the VCCTMR counter. If Vcc OK is not set, (bit VCCOK) at this time, a deactivation will be initiated. VCCSEL bits are not automatically cleared. The firmware m ust clear the VCCSEL bits before starting a new activation.

t2: Time from VccTmr timeout and VCC OK to IO reception (high), typically 2-3 CLK cycles if RDYST = 0. If RDYST = 1, t2 starts when VCCOK = 1.

t3: Time from IO = high to CLK start, typically 2-3 CLK cycles. t4: Time allowed for start of CLK to de-assertion of RST. Programmable by the RLength register. t5: Time allowed for ATR timeout, set by the STSTO register. Note: If the RSTCRD bit is set, RST is asserted (low). Upon clearing RSTCRD bit, RST will be

de-asserted after t4.

72 Rev. 1.4

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VCC

RST

CLK

t1 t2

Firmware sets

VCCSEL to 00

CMDVCCnB

t5 delay or

Card Event

Figure 16: Asynchronous Activation Sequence Timing

t1: Time after either a “card event” occurs or firmware sets the VCCSela and VCCSelb bits to 0 (see t5, VCCOff_tmr) occurs until RST is asserted low.

t2: Time after RST goes low until CLK stops. t3: Time after CLK stops until IO goes low. t4: Time after IO goes low until VCC is powered down. t5: Delayed VCC off time (in ETUs per VCCOff_tmr bits). Only i n effect due to firmware

deactivation.

Figure 17: Deactivation Sequence

1.7.15.3 Data Reception/Transmission

When a 12Mhz crystal is used, the smart card UART will generate a 3.69Mhz (default) clock to both smart card interfaces. This will allow approximately 9600bps (1/ETU) communication during ATR (ISO 7816 default). As part of the PPS negotiation between the smart card and t he reader, the firmware may determine that the smart card parameters F & D may be changed. After this negotiat i on, the firmware may change the ETU by writing to the SFR FDReg to adjust the ETU and CLK. The firmware may also change the smart card clock frequency by writing to the SFR SCCLK (SCECLK for external interface). Independent clock frequency control is provided to each smart card interface. Clock stop high or Clock stop low is supported in asynchronous mode. Figure 18 shows the ETU and CLK control circuits. The firmware determines when clock stop is supported by the smart card and when it is appropriate to go into that mode (and when to come out of it). The smart card UART is clocked by the same clock that is provided to the selected smart card. The transition between smart card clocks is handled in hardware to eliminate any glitches for the UART during switchover. The external smart card clock is not affected when switching the UART to communicate with the internal smart card.

Rev. 1.4 73

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73S1210F Data Sheet DS_1210F_001

PLL

ETU Divider

12 bits

FI Decoder

DIV

ETUCLK

CLK

DIV

SCLK

Pre-Scaler

6 bits

Pre-Scaler

6 bits

F/D Register

SCCLK(5:0)

SCSCLK(5:0)

MSCLK

MSCLKE

MCLK =

96MHz

FDReg(3:0)

FDReg(7:4)

9926

1/744

3.69M

1/13

7.38M

3.69M

7.38M

Defaults in Italics

SCSel(3:2)

1/13

SYNC

CENTER

EDGE

Figure 18: Smart Card CLK and ETU Generation

There are two, two-byte FIFOs that are used to buffer transmit and receive data. During a T=0 processing, if a parity error is detected by the 73S1210F during message reception, an error signal (BREAK) will be generated to the smart card. The byte received will be discarded and the firmware notified of the error. Break generation and receive byte dropping can be disabled under firmware control. During the transmission of a byte, if an error signal (BREAK) is detected, the last by te is retransmitted again and the firmware notified. Retransmission can be disabled by firmware. When a correct byte is received, an interrupt is generated to the firmware, which then reads the byte from the receive FIFO. Receive overruns are detected by the hardware and reported via an interrupt. During transmission of a message, the firmware will write bytes into the transmit FIFO. The hardware will send them t o the smart card. When the last byte of a message has been written, the firmware will need to set the LASTT X bi t in the STXCtl SFR. This will cause the hardware to insert the CRC/LRC if in a T=1 protocol mode. CRC/LRC generation/checking is only provided during T=1 processing. Firmware will need to instruct the smart function to go into receive mode after this last transmit data byte if it expects a response from the smart card. At the end of the smart card response, the firmware will put the interface back into transmit mode if appropriate.

The hardware can check for the following card-related timeouts:

• Character Waiting Time (CWT)

• Block Waiting Time (BWT)

• Initial Waiting Time (IWT)

The firmware will load the Wait Time with the appropriate value for the operating mode at the appropriate time. Figure 19 shows the guard, block, wait and ATR time definitions. If a timeout occurs, an interrupt will be generated and the firmware can take appropriate recovery steps. Support is provided for adding additional guard times between characters using the Extra Guard Time register (EGT), and between the last byte received by the 73S1210F and the first byte transmitt ed by the 73S1210F using the Block Guard Time register (BGT). Other than the protocol checks described above, the firmware is responsible for all protocol checking and error recovery.

74 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

> EGT

< WWT

CHAR 1 CHAR 2

CHAR

N+1

CHAR

N+2

CHAR

N+3

BLOCK1 BLOCK2

> BWT < CWT

RECEPTION

TRANSMISSION

T = 1 Mode

CHAR 1

CHAR 2

CHAR N

RST

TSTO(7:0)

ATRTO(15:0)

VCC_OK

RLen(7:0)

CHAR 1

CHAR 2

CHAR N

ATR Timing Parameters

IWT(15:0)

BGT(4:0)

T = 0 Mode

EGT

(By seting Last_TXByte and TX/RXB=0 during CHAR N, RX mode will start after last

TX byte)

WWT is set by the value in the BWT registers.

Figure 19: Guard, Block, Wait and ATR Time Definitions

1.7.15.4 Bypass Mode

It is possible to bypass the smart card UART in order for the firmware to support non-T=0/T=1 smart cards. This is called Bypass mode. In this mode the embedded firmware will communicate directly with the selected smart card and drive I/O during transmit and read I/O during receive in order to communicate with the smart card. In this mode, ATR processing is under firmware control. The firmware must sequence the interface signals as required. Firmware must perform TS processing, parity checking, break generation and CRC/LRC calculation (if required).

1.7.15.5 Synchronous Operation Mode

The 73S1210F supports synchronous operation. When sync mode is selected for either interface, the CLK signal is generated by the ETU counter. The values in c, SCCLK, and SCECLK must be set to obtain the desired sync CLK rate. There is only one ETU counter and therefore, in sync mode, the interface must be selected to obtain a smart card clock signal. In sync mode, input data is sampled on the rise of CLK, and output data is changed on the fall of CLK.

Rev. 1.4 75

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73S1210F Data Sheet DS_1210F_001

Special Notes Regarding Synchronous Mode Operation When the SCISYN or SCESNC bits (SPrtcol, bit 7, bit 5, respectively) are set, the selected smart card

interface operates in synchronous mode and there are changes in the definition and behavior of pertinent register bits and associated circuitry. The following requirements are to be noted:

1. The source for the smart card clock (CLK or SCLK) is the ETU counter. Only the actively selected interface can have a running synchronous clock. In contrast, an unselected interface may have a running clock in the asynchronous mode of operation.

2. The control bits CLKLVL, SCLKLVL, CLKOFF, and SCLKOFF are functional in sy nchronous mode. When the CLKOFF bit is set, it will not truncate either the logic low or logic high period when the (stop at) level is of opposite polarity. The CLK/SCLK signal will complet e a correct logi c l ow or logi c high duty cycle before stopping at the selected level. The CLK “start” is a result of t he falling edge of the CLKOFF bit. Setting clock to run when it is stopped low will result in a half period of low before going high. Setting clock to run when it is stopped high will result in the clock going low immediately and then running at the selected rate with 50% duty cycle (within the limit ations of the ETU divisor value).

3. The Rlen(7:0) is configured to count the falling edges of the ETU clock (CLK or SCLK) after it has been loaded with a value from 1 to 255. A value of 0 disables the counting functi on and RLen functions such as I/O source selection (I/O signal bypasses the FIFOs and is controlled by the

SCCLK/SCECLK SFRs). When the RLen counter reaches the “max” (loaded) value, it sets the

WAITTO interrupt (SCInt, bit 7), which is maskable via WTOIEN (SCIE, bit 7). It must be reloaded in order to start the counting/clocking process again. This allows the processor to select the number of CLK cycles and hence, the number of bits to be read or written to/from the card.

4. The FIFO is not clocked by the first CLK (falling) edge resulting from a CLKOFF de-assertion (a clock start event) when the CLK was stopped in the high state and RLen has been loaded but not yet clocked.

5. The state of the pin IO or SIO is sampled on the rising edge of CLK/SCLK and st ored i n bi t 5 of the

SCCtl/SCECtl register.

6. When Rlen = max or 0 and

I2CMODE= 1 (STXCtl, b7), the IO or SIO signal is directly controlled by the

data and direction bits in the respective SCCtl and SCECtl register. The state of the data in the TX FIFO is bypassed.

7. In the SPrtcol register, bit 6 (MODE9/8B) becomes active. When set, the RXData FIFO wil l read nine-bit words with the state of the ninth bit being readable in SRXCtl, bit 7 (B9DAT). The RXDAV interrupt will occur when the ninth bit has been clocked in (rising edge of CLK or SCLK).

8. Care must be taken to clear the RX and TX FIFOs at the start of any transaction. The user shall read the RX FIFO until it indicates empty status. Reading the TX FIFO twice will reset the input byte pointer and the next write to the TX FIFO will load the byt e to the “first out” position. Note that the bit pointer (serializer/deserializer) is reset to bit 0 on any change of the TX/RXD bit.

Special bits that are only active for sync mode include: SRXCtl, b7 “BIT9DAT”, SPrtcol, b6 “MODE9/8B”,

STXCtl, b7 “

I2CMODE”, and the definition of SCInt, b7, which was “WAITTO”, becomes RLenINT interrupt,

and SCIE, b7, which was “WTOIEN”, becomes RLenIEN.

76 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

VCC

VCCOK

RSTCRD

RST

CLK

tto

VCCSEL

bits

IO reception on

RST

CLK

CLKOFF

CLKLVL

Rlength Interrupt

RLength Count

RLenght = 1

TX/RXB Mode bit

(TX = '1')

1. Clear CLKOFF after Card is in reception mode.

2. Set RST bit.

3. Interrupt is generated when Rlength counter is MAX.

4. Read and clear Interrupt.

5. Clear RST bit.

6. Toggle TX/RXB to reset bit counter.

7. Reload RLength Counter.

Count MAX

t1. CLK wll start at least 1/2 ETU after CLKOFF is set low when CLKLVL = 0

t1: The time from setting VCCSEL bits until VCCOK = 1. tto: The time from setting VCCSEL bits until VCCTMR times out. At t1 (if RDYST = 1) or tto (if RDYST = 0),

activation starts. It is suggested to have RD Y ST = 0 and use the VCCTMR interrupt to let M PU know when sequence is starting.

t2: time from start of activation (no exter nal indication) until IO goes into recept ion mode (= 1). This is approximately 4 SCCLK (or SCECLK) clock cycles.

t3: minimum one half of ETU period. t4: ETU period. Note that in Sync mode, IO as input is sampled on the rising edge of CLK. IO changes on the falling edge of CLK,

either from the card or from the 73S1210F. T he RST signal to the card is directly controlled by the RSTCRD bit (non-inverted) via the MPU and is shown as an example of a possible RST pattern.

Figure 20: Synchronous Activation

Rev. 1.4 77

Figure 21: Example of Sync Mode Operation: Generating/Reading ATR Signals

Page 78

73S1210F Data Sheet DS_1210F_001

RLength Count

(Rlength = 9)

CLK

RLength Interrupt

CLK Stop

CLK Stop Level

IO Bit

IODir Bit

TX/RX Mode Bit

TX = '1'

I2CMode = 1: Data to/from Card I2CMode = 0: Data from TX fifo

I2CMode = 1:ACK Bit (to/from card)

I2CMode = 0: Data from TX fifo

RLength Count MAX

1. Interrupt generated when Rlength counter is MAX.

2. Read and clear Interrupt.

3. Set CLK Stop and CLK Stop level high.

4. Set IO Bit low and IODir = Output.

5. Set TX/RX Bit to TX mode.

6. Reload Rlength Counter.

7. Set IO Bit High and IODir = Output.

8. Clear CLK Stop and CLK Stop level. Note: Data in TX fifo should not be Empty here.

STOP Bit

TX/RX mode

Synchronous Clock Start/Stop Mode Stop bit procedure. This procedure should be used to

generate the Stop bit in Synchronous Mode. SYCKST is bit 7 of STXCTL register.

START Bit

CLK

Data from Card -end of ATR

RLength Count - was set for length of ATR

RLength Interrupt

CLK Stop

CLK Stop Level

IO Bit

IODir Bit

TX/RX Mode Bit

TX = '1'

RLength

Count MAX

RLen=0 Rlen=1

Data from TX FIFO

1. Interrupt generated when Rlength counter is MAX.

2. Read and clear Interrupt.

3. Set CLK Stop and CLK Stop level high in Interrupt routine.

4. Set TX/RX Bit to TX mode.

5. Reload Rlength Counter.

6. Set IO Bit low and IODir = Output. Since Rlen=(MAX or 0) and TX/RX =1, IO pin is controlled by IO bit.

7. Clear CLK Stop and CLK Stop level. Note: Data in TX fifo should not be Empty here.

Synchronous Clock Start/Stop Mode style Start bit procedure. This procedure should be used to

generate the start bit insertion in Synchronous mode for Synchronous Clock Start/Stop Mode protocol.

Figure 22: Creation of Synchronous Clock Start/Stop Mode Start Bit in Sync Mode

Figure 23: Creation of Synchronous Clock Start/Stop Mode Stop Bit in Sync Mode

78 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

RLength Count

RLength = 9

CLK

RLength Interrupt

RX data

TX/RX Mode Bit

TX = '1'

Data from Card

(Bit 8)

Data from Card

(Bit 1)

RLength Count MAX

Rlen=9

Protection Bit

(Bit 9)

RX FIFO

(Data from Card is ready for CPU read)

Protection Bit is ready for CPU read

Rlen=8

Rlen=0 Rlen =1

Protection Bit Data

(Bit 9)

1._ Interrupt generated

when Rlength counter is

Max

2._ Read and clear Interrupt

3._ Reload RLength counter

RLength Count

RLength = 9

RLength Count MAX

Rlen=9

Rlen=8

RLength Interrupt

CLK

CLK Stop

CLK Stop Level = 0

1._ Interrupt generated

when Rlength counter is Max

2._Stop CLK after the last byte and protection bit

Stop CLK after receiving the last byte and protection bit.

Receive data in 9 bit mode

Synchronous card operation is broken down into three primary types. These are commonly referred to as 2-wire, 3-wire and I2C synchronous cards. Each card type requires different control and timing and therefore requires different algorithms to access. Teridian has created an application note to provide

Figure 24: Operation of 9-bit Mode in Sync Mode

detailed algorithms for each card type. Refer to the application note titled “73S12xxF Synchronous Card Design Application Note”.

Rev. 1.4 79

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73S1210F Data Sheet DS_1210F_001

1.7.15.6 Smart Card SFRs

Smart Card Select Register (SCSel): 0xFE00  0x00

The Smart Card Select register is used to determine which smart card interface is using the ISO UART. The internal Smart Card has integrated 7816-3 compliant sequencer circuitry to drive an external smart card interface. The external smart card interface relies on 73S8010 parts to generate the ISO 7816-3 compatible signals and sequences. Multiple 73S8010 devices can be connected to the external smart card interface.

Table 72: The SCSel Register

MSB LSB

– – – – SELSC.1 SELSC.0 BYPASS –

Bit Symbol Function

SCSel.7 – SCSel.6 – SCSel.5 – SCSel.4 –

Select Smart Card Interface - These bits select the interface that is using

SCSel.3 SELSC.1

the IS0 UART. These bits do not activate the interface. Activ ation is performed by the VccCtl register.

00 = No smart card interface selected.

SCSel.2 SELSC.0

01 = External Smart Card Interface selected (using SCLK, SIO). 1X = Internal Smart Card Interface selected.

SCSel.1 BYPASS

1 = Enabled, 0 = Disabled. When enabled, ISO UART is bypassed and the I/O line is controlled via the SCCtl and SCECtl registers.

SCSel.0 –

80 Rev. 1.4

Page 81

DS_1210F_001 73S1210F Data Sheet

Smart Card Interrupt Register (SCInt): 0xFE01  0x00

When the smart card interrupt is asserted, the firmware can read this register to determine the actual cause of the interrupt. The bits are cleared when this register is read. Each interrupt can be disabled by the Smart Card Interrupt Enable register. Error processing must be handled by the firmware. This register relates to the interface that is active – see the SCSel register (above).

Table 73: The SCInt Register

MSB LSB

WAITTO CRDEVT VCCTMRI RXDAV TXEVT TXSENT TXERR RXERR

Bit Symbol Function

Wait Timeout - An ATR or card wait timeout has occurred. In sync mode, this interrupt is asserted when the RLen counter (it advances on falling

SCInt.7 WAITTO

edges of CLK/ETU) reaches the loaded (max) value. This bit is cleared when the SCInt register is read. When running in Synchronous Clock Stop Mode, this bit becomes RLenINT interrupt (set when the Rlen counter reaches the terminal count).

Card Event - A card event is signaled via pin DETCARD either when the Card was inserted or removed (read the CRDCtl register to determine

SCInt.6 CRDEVT

card presence) or there was a fault condition in the interface circuitry. This bit is functional even if the smart card logic clock is disabled and when the PWRDN bit is set. This bit is cleared when the SCInt register is read.

SCInt.5 VCCTMRI

VCC Timer - This bit is set when the VCCTMR times out. This bit is cleared when the SCInt register is read.

Rx Data Available - Data was received from the smart card because the Rx FIFO is not empty. In bypass mode, this interrupt is generated on a

SCInt.4 RXDAV

falling edge of the smart card I/O line. After receiving this int errupt i n bypass mode, firmware should disable it until the firmware has received the entire byte and is waiting for the next start delimiter. T hi s bit is cleared when there is no RX data available in the RX FIFO.

SCInt.3 TXEVNT

TX Event - Set whenever the TXEMTY or TXFULL bits are set in the

SRXCtl SFR. This bit is cleared when the STXCtl register is read.

TX Sent - Set whenever the ISO UART has successfully transmitted a byte to the smart card. Also set when a CRC/LRC byte is sent in T=1

SCInt.2 TXSENT

mode. Will not be set in T=0 when a break is detected at the end of a byte (when break detection is enabled). This bit is cleared when the SCInt register is read.

TX Error - An error was detected during the transmission of data to the

SCInt.1 TXERR

smart card as indicated by either BREAKD or TXUNDR bit being set in the STXCtl SFR. Additional information can be found in that register description. This bit is cleared when the STXCtl register is read.

RX Error - An error was detected during the reception of data from the

SCInt.0 RXERR

smart card. Additional information can be found in the SRXCtl register. This interrupt will be asserted for RXOVRR, or RX Parity error events. This bit is cleared when the SRXCtl register is read.

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73S1210F Data Sheet DS_1210F_001

Smart Card Interrupt Enable Register (SCIE): 0xFE02  0x00

When set to 1, the respective condition can cause a smart card interrupt. When set to a 0, the respective condition cannot cause an interrupt. When disabled, the respective bit in the Smart Card Interrupt register can still be set, but it will not interrupt the MPU.

Table 74: The SCIE Register

MSB LSB

WTOIEN CDEVEN VTMREN RXDAEN TXEVEN TXSNTEN TXEREN RXEREN

Bit Symbol Function

SCIE.7 WTOIEN

Wait Timeout Interrupt Enable - Enable for ATR or Wait Timeout Interrupt.

In sync mode, function is RLIEN (RLen = max.) interrupt enable. SCIE.6 CDEVEN Card Event Interrupt Enable. SCIE.5 VTMREN VCC Timer Interrupt Enable. SCIE.4 RXDAEN Rx Data Available Interrupt Enable. SCIE.3 TXEVEN TX Event Interrupt Enable. SCIE.2 TXSNTEN TX Sent Interrupt Enable. SCIE.1 TXEREN TX Error Interrupt Enable. SCIE.0 RXEREN RX Error Interrupt Enable.

82 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

Smart Card VCC Control/Status Register (VccCtl): 0xFE03  0x00

This register is used to control the power up and power down of the integrated smart card interface. It is used to determine whether to apply 5V, 3V, or 1.8 to the smart card. P erf orm the voltage selection with one write operation, setting both VCCSEL.1 and VCCSEL.0 bits simultaneously. The VDDFLT bit (if enabled) will provide an emergency deactivation of the internal smart card slot. See t he VDD Fault

Detect Function section for more detail.

Table 75: The VccCtl Register

MSB LSB

VCCSEL.1 VCCSEL.0 VDDFLT RDYST VCCOK – – SCPWRDN

Bit Symbol Function

Setting non-zero value for bits 7,6 will begin activation sequence with target Vcc as given below:

VccCtl.7 VCCSEL.1

State VCCSEL.1 VCCSEL.0 VCC 1 0 0 0V 2 0 1 1.8V 3 1 0 3.0V 4 1 1 5V

VccCtl.6 VCCSEL.0

A card event or VCCOK going low will initiate a deactivation sequence. When the deactivation sequence for RST, CLK and I/O is complete, V

will be turned off. When this type of deactivation occurs, the bits must be reset before initiating another activation.

When there is a VDD Fault event, this bit will be set = 0. This causes

VccCtl.5 VDDFLT

VCCSEL.1 and VCCSEL.0 bits to be immediately set = 0 to begin deactivation.

If this bit is set = 1, the activation sequence will start when bit VCCOK is set =

VccCtl.4 RDYST

1. If not set, the deactivation sequence shall start when the VCCTMR times out.

VccCtl.3 VCCOK (Read only). Indicates that VCC output voltage is stable. VccCtl.2 – VccCtl.1 –

This bit controls the power-off mode of the 73S1210F circuit. 1 = power off, 0 = normal operation. When in power down mode,

VccCtl.0 SCPWRDN

= 0V. VDD can only be turned on by pressing the ON/OFF switch or by

application of 5V to V it has no effect until V

. If V

BUS

is removed and VDD will shut off.

BUS

power is available and SCPWRDN bit is set,

BUS

Rev. 1.4 83

Page 84

73S1210F Data Sheet DS_1210F_001

VCC Stable Timer Register (VccTmr): 0xFE04  0x0F

A programmable timer is provided to set the time from activation st art (setting the VCCSEL.1 and VCCSEL.0 bits to non-zero) to when VCC_OK is evaluated. VCC_OK must be true at the end of this timers programmed interval (tto in Figure 16) in order for the activation sequence to continue. I f VCC_OK is not true and the end of the interval (tto), the Card Event interrupt will be set, and a deactivation sequence shall begin including clearing of the VCCSEL bits.

Table 76: The VccTmr Register

MSB LSB

OFFTMR.3 OFFTMR.2 OFFTMR.1 OFFTMR.0 VCCTMR.3 VCCTMR.2 VCCTMR.1 VCCTMR.0

Bit Symbol Function

VccTmr.7 OFFTMR.3 VccTmr.6 OFFTMR.2 VccTmr.5 OFFTMR.1

VccTmr.4 OFFTMR.0 VccTmr.3 VCCTMR.3

VccTmr.2 VCCTMR.2 VccTmr.1 VCCTMR.1

VccTmr.0 VCCTMR.0

VCC Off Timer - The bits set the delay (in number of ETUs) for deactivation after the VCCSEL.1 and VCC SEL.0 have been set to 0. The time value is a count of the 32768Hz clock and is given by tto = OFFTMR(7:4) * 30.5µs. This delay does not affect emergency deactivations due to VDD Fault or card events. A value of 0000 results in no additional delay.

VCC Timer - VCCOK must be true at the time set by the value in these bits in order for the activation sequence to continue. If not, the VCCSEL bits will be cleared. The time value is a count of the 32768Hz clock and is given by tto = VCCTMR(3:0) * 30.5µs. A value of 0000 results in no timeout, not zero time, and activation requires that RDYST is set and RDY goes high.

84 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

Card Status/Control Register (CRDCtl): 0xFE05  0x00

This register is used to configure the card detect pin (DETCARD) and monitor card detect status. This register must be written to properly configure Debounce, Detect_Polarity (= 0 or = 1), and the pullup/down enable before setting CDETEN. The card detect logic is functional even without smart card logic clock. When the PWRDN bit is set = 1, no debounce is provided but card presence is operable.

Table 77: The CRDCtl Register

MSB LSB

DEBOUN CDETEN – – DETPOL PUENB PDEN CARDIN

Bit Symbol Function

Debounce - When set = 1, this will enable hardware debounce of the card detect pin. The debounce function shall wait for 64ms of

CRDCtl.7 DEBOUN

stable card detect assertion before setting the CARDIN bit. This counter/timer uses the keypad clock as a source of 1kHz signal. De-assertion of the CARDIN bit is immediate upon de-assertion of the card detect pin(s).

CRDCtl.6 CDETEN

Card Detect Enable - When set = 1, activates card detection

input. Default upon power-on reset is 0. CRDCtl.5 – CRDCtl.4 –

CRDCtl.3 DETPOL

Detect Polarity - When set = 1, the DETCARD pin shall interpret

a logic 1 as card present. CRDCtl.2 PUENB Enable pull-up current on DETCARD pin (active low). CRDCtl.1 PDEN Enable pull-down current on DETCARD pin.

Card Inserted - (Read only). 1 = card inserted, 0 = card not CRDCtl.0 CARDIN

inserted. A change in the value of this bit is a “card event.” A

read of this bit indicates whether smart card is inserted or not

inserted in conjunction with the DETPOL setting.

Rev. 1.4 85

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73S1210F Data Sheet DS_1210F_001

TX Control/Status Register (STXCtl): 0xFE06  0x00

This register is used to control transmission of data to the smart card. Some control and some status bits are in this register.

Table 78: The STXCtl Register

MSB LSB I2CMODE – TXFULL TXEMTY TXUNDR LASTTX TX/RXB BREAKD

Bit Symbol Function

I2C Mode - When in sync mode and this bit is set, and when the RLen count

STXCtl.7 I2CMODE

value = max or 0, the source of the smart card data for IO pin (or SIO pin) will be connected to the IO bit in SCCtl (or SCECtl) register rather than the TX FIFO. See the description for the Protocol Mode Register for more detail.

STXCtl.6 –

TX FIFO is full. Additional writes may corrupt the contents of the FI FO . This

STXCtl.5 TXFULL

bit it will remain set as long as the TX FIFO is full. Generates a TX_Event interrupt upon going full.

1 = TX FIFO is empty, 0 = TX FIFO is not empty. I f there is data in the TX FIFO, the circuit will transmit it to the smart card if in transmit mode. In T=1 mode, if the LASTTX bit is set and the hardware is configured to transmit the

STXCtl.4 TXEMTY

CRC/LRC, the TXEMTY will not be set until the CRC/LRC is transmitted. I n T=0, if the LASTTX bit is set, TXEMTY will be set after the last word has been successfully transmitted to the smart card. Generates a TXEVNT interrupt upon going empty.

TX Underrrun - (Read only) Asserted when a transmit under-run condition has occurred. An under-run condition is defined as an empty TX FIFO when

STXCtl.3 TXUNDR

the last data word has been successfully transmitted to the smart card and the LASTTX bit was not set. No special processing is performed by the hardware if this condition occurs. Cleared when read by firmware. This bit generates a TXERR interrupt.

Last TX Byte - Set by firmware (in both T=0 and T=1) when the last byte in the current message has been written into the transmit FIFO. In T=1 mode,

STXCtl.2 LASTTX

the CRC/LRC will be appended to the message. Should be set after the last byte has been written into the transmit FIFO. Should be cleared by firmware before writing first byte of next message into the transmit FIFO . Used in T=0 to determine when to set TXEMTY.

1 = Transmit mode, 0 = Receive mode. Configures the hardware to be receiving from or transmitting to the smart card. Determines which counters should be enabled. This bit should be set to receive mode prior to switching

STXCtl.1 TX/RXB

to another interface. Setting and resetting this bit shall initi al i ze t he CRC logic. If LASTTX is set, this bit can be reset to RX mode and UART logic will automatically change mode to RX when TX operation is completed (TX_Empty = 1).

Break Detected - (Read only) 1 = A break has been detected on the I/O line

STXCtl.0 BREAKD

indicating that the smart card detected a parity error. Cleared when read. This bit generates a TXERR interrupt.

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DS_1210F_001 73S1210F Data Sheet

STX Data Register (STXData): 0xFE07  0x00

Table 79: The STXData Register

MSB LSB

STXDAT.7 STXDAT.6 STXDAT.5 STXDAT.4 STXDAT.3 STXDAT.2 STXDAT.1 STXDAT.0

Bit Function

STXData.7 STXData.6 STXData.5 STXData.4 STXData.3 STXData.2

Data to be transmitted to smart card. Gets stored in the TX FIFO and t hen extracted by the hardware and sent to the selected smart card. When the MPU reads this register, the byte pointer is changed to effectively “read out” the data. Thus, two reads will always result in an “empty” FIFO condition. The contents of the FIFO regist ers are not

cleared, but will be overwritten by writes. STXData.1 STXData.0

SRX Control/Status Register (SRXCtl): 0xFE08  0x00

This register is used to monitor reception of data from the smart card.

Table 80: The SRXCtl Register

MSB LSB

BIT9DAT – LASTRX CRCERR RXFULL RXEMTY RXOVRR PARITYE

Bit Symbol Function

Bit 9 Data - When in sync mode and with MODE9/8B set, this bit will contain

SRXCtl.7 BIT9DAT

the data on IO (or SIO) pin that was sampled on the ninth CLK (or SCLK) rising edge. This is used to read data in synchronous 9-bit formats.

SRXCtl.6 –

Last RX Byte - User sets this bit during the reception of the last byte. When

SRXCtl.5 LASTRX

byte is received and this bit is set, logic checks CRC to match 0x1D0F (T=1 mode) or LRC to match 00h (T=1 mode), otherwise a CRC or LRC error is

asserted. SRXCtl.4 CRCERR (Read only) 1 = CRC (or LRC) error has been detected. SRXCtl.3 RXFULL (Read only) RX FIFO is full. Stat us bit to indicate RX FIFO is full.

SRXCtl.2 RXEMTY

(Read only) RX FIFO is empty. This is only a status bit and does not generate

an RX interrupt.

RX Overrun - (Read Only) Asserted when a receive-over-run condition has

occurred. An over-run is defined as a byte was received from the smart card SRXCtl.1 RXOVRR

when the RX FIFO was full. Invalid data may be in the receive FIFO.

Firmware should take appropriate action. Cleared when read. Additional

writes to the RX FIFO are discarded when a RXOVRR occurs until the overrun

condition is cleared. Will generate an RXERR interrupt.

Parity Error - (Read only) 1 = The logic detected a parity error on incoming SRXCtl.0 PARITYE

data from the smart card. Cleared when read. Will generate an RXERR

interrupt.

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73S1210F Data Sheet DS_1210F_001

SRX Data Register (SRXData): 0xFE09  0x00

Table 81: The SRXData Register

MSB LSB

SRXDAT.7 SRXDAT.6 SRXDAT.5 SRXDAT.4 SRXDAT.3 SRXDAT.2 SRXDAT.1 SRXDAT.0

Bit Function

SRXData.7 SRXData.6 SRXData.5 SRXData.4 SRXData.3

(Read only) Data received from the smart card. Data received from the smart card gets stored in a FIFO that is read by the firmware.

SRXData.2 SRXData.1 SRXData.0

88 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

mode.

Smart Card Control Register (SCCtl): 0xFE0A  0x21

This register is used to monitor reception of data from the smart card.

Table 82: The SCCtl Register

MSB LSB

RSTCRD – IO IOD C8 C4 CLKLVL CLKOFF

Bit Symbol Function

1 = Asserts the RST (set RST = 0) to the smart card interface, 0 = De-assert

the RST (set RST = 1) to the smart card interface. Can be used to extend

RST to the smart card. Refer to RLength register description. This bit is

operational in all modes and can be used to extend RST during activation or

SCCtl.7 RSTCRD

perform a “Warm Reset” as required. In auto-sequence mode, this bit should

be set = 0 to allow the sequencer to de-assert RST per the RLength

parameters.

In sync mode (see the SPrtcol

set = 1, RST = 1, if set = 0, RST = 0. Rlen has no effect on Reset in sync

SCCtl.6 –

Smart Card I/O. Read is state of I/O signal (Caution, this signal is not

SCCtl.5 IO

synchronized to the MPU clock). In Bypass mode, write value is state of

signal on I/O. In sync mode, this bit will contain the value of I/ O pi n on the

latest rising edge of CLK.

SCCtl.4 IOD

Smart Card I/O Direction control Bypass mode or sync mode. 1 = input

(default), 0 = output.

Smart Card C8. When C8 is an output, the value written to this bit will appear

on the C8 line. The value read when C8 is an output is the value stored in

SCCtl.3 C8

the register. When C8 is an input, the value read is the value on the C8 pin

(Caution, this signal is not synchronized to the MPU clock). When C8 is an

input, the value written will be stored in the register but not presented to the

C8 pin.

Smart Card C4. When C4 is an output, the value written to this bit will appear

on the C4 line. The value read when C4 is an output is the value stored in

SCCtl.2 C4

the register. When C4 is an input, the value read is the value on the C4 pin

(Caution, this signal is not synchronized to the MPU clock). When C4 is an

input, the value written will be stored in the register but not presented to the

C4 pin.

1 = High, 0 = Low. If CLKOFF is set = 1, the CLK to smart card will be at the

SCCtl.1 CLKLVL

logic level indicated by this bit. If in bypass mode, this bit direct ly controls the

state of CLK.

0 = CLK is enabled. 1 = CLK is not enabled. When asserted, the CLK will

SCCtl.0 CLKOFF

stop at the level selected by CLKLVL. This bit has no effect if i n bypass

mode.

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73S1210F Data Sheet DS_1210F_001

External Smart Card Control Register (SCECtl): 0xFE0B  0x00

This register is used to directly set and sample signals of External Smart Card interface. There are three modes of asynchronous operation, an “automatic sequence” mode, and bypass mode. Clock stop per the ISO 7816-3 interface is also supported but firmware must handle the protocol for SIO and SCLK for

C clock stop and start. Control for Reset (to make RST signal), activation control, voltage select, et c.

I should be handled via the I

C interface when using external 73S8010 devices. USR(n) pins shall be

used for C4, C8 functions if necessary.

Table 83: The SCECtl Register

MSB LSB

– – SIO SIOD – – SCLKLVL SCLKOFF

Bit Symbol Function

SCECtl.7 – SCECtl.6 –

External Smart Card I/O. Bit when read indicates state of pin SI O for SIOD

= 1 (Caution, this signal is not synchronized to the MPU clock), when SCECtl.5 SIO

written, sets the state of pin SIO for SIOD = 0. Ignored if not i n bypass or

sync modes. In sync mode, this bit will contain the value of IO pin on the

latest rising edge of SCLK. SCECtl.4 SIOD

1 = input, 0 = output. External Smart Card I/O Direction control. Ignored if

not in bypass or sync modes. SCECtl.3 – SCECtl.2 –

SCECtl.1 SCLKLVL

SCECtl.0 SCLKOFF

Sets the state of SCLK when disabled by SCLKOFF bit. If in bypass mode,

this bit directly controls the state of SCLK.

0 = SCLK enabled, 1 = SCLK disabled. When disabled, SCLK level is

determined by SCLKLVL. This bit has no effect if in bypass mode.

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DS_1210F_001 73S1210F Data Sheet

C4/C8 Data Direction Register (SCDIR): 0xFE0C  0x00

This register determines the direction of the internal interface C4/C8 lines. After reset, all signals are tri-stated.

Table 84: The SCDIR Register

MSB LSB

– – – – C8D C4D – –

Bit Symbol Function

SCDIR.7 – SCDIR.6 – SCDIR.5 – SCDIR.4 – SCDIR.3 C8D 1 = input, 0 = output. Smart Card C8 direction. SCDIR.2 C4D 1 = input, 0 = output. Smart Card C4 direction. SCDIR.1 – SCDIR.0 –

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73S1210F Data Sheet DS_1210F_001

Protocol Mode Register (SPrtcol): 0xFE0D  0x03

This register determines the protocol to be use when communicating with the selected smart card. This register should be updated as required when switching between smart card interfaces.

Table 85: The SPrtcol Register

MSB LSB

SCISYN MOD9/8B SCESYN 0 TMODE CRCEN CRCMS RCVATR

Bit Symbol Function

Smart Card Internal Synchronous mode - Configures internal smart card SPrtcol.7 SCISYN

interface for synchronous mode. This mode routes the internal interface

buffers for RST, IO, C4, C8 to the SCCtl register bits for direct firmware

control. CLK is generated by the ETU counter.

Synchronous 8/9 bit mode select - For sync mode, in protocols with 9-bit SPrtcol.6 MOD9/8B

words, set this bit. The first eight bits read go into the RX FIFO and the

ninth bit read will be stored in the IO (or SIO) data bit of the SRXCtl register.

Smart Card External Synchronous mode - Configures External Smart Card SPrtcol.5 SCESYN

interface for synchronous mode. This mode routes the external smart card

interface buffers for SIO to SCECtl register bits for direct firmware control.

SCLK is generated by the ETU counter. SPrtcol.4 0 Reserved bit, must always be set to 0.

SPrtcol.3 TMODE

Protocol mode select - 0: T=0, 1: T=1. Determines which smart card

protocol is to be used during message processing.

CRC Enable – 1 = Enabled, 0 = Disabled. Enables the checking/generation

of CRC/LRC while in T=1 mode. Has no effect in T=0 mode. If enabled and SPrtcol.2 CRCEN

a message is being transmitted to the smart card, the CRC/LRC will be

inserted into the message stream after the last TX byte is transmitted to t he

smart card. If enabled, CRC/LRC will be checked on incoming messages

and the value made available to the firmware via the CRC LS/MS registers. SPrtcol.1 CRCMS

CRC Mode Select – 1 = CRC, 0 = LRC. Determines type of checking

algorithm to be used.

Receive ATR – 1 = Enable ATR timeout, 0 = Disable ATR timeout. Set by SPrtcol.0 RCVATR

firmware after the smart card has been turned on and the hardware is

expecting ATR.

92 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

SC Clock Configuration Register (SCCLK): 0xFE0F  0x0C

This register controls the internal smart card (CLK) clock generation.

Table 86: The SCCLK Register

MSB LSB

– – ICLKFS.5 ICLKFS.4 ICLKFS.3 ICLKFS.2 ICLKFS.1 ICLKFS.0

Bit Symbol Function

SCCLK.7 – SCCLK.6 – SCCLK.5 ICLKFS.5 SCCLK.4 ICLKFS.4 SCCLK.3 ICLKFS.3 SCCLK.2 ICLKFS.2 SCCLK.1 ICLKFS.1 SCCLK.0 ICLKFS.0

Internal Smart Card CLK Frequency Select - Division factor to determine internal smart card CLK frequency. MCLK clock is divided by (register value + 1) to clock the ETU divider, and then by 2 to generate CLK. Default ratio is 13. The programmed value in this register is applied to the divider after this value is written, in such a manner as to produce a glitch-free output, regardless of the selection of active interface. A register value = 0 will default to the same effect as register value = 1.

External SC Clock Configuration Register (SCECLK): 0xFE10  0x0C

This register controls the external smart card (SCLK) clock generation.

Table 87: The SCECLK Register

MSB LSB

– – ECLKFS.5 ECLKFS.4 ECLKFS.3 ECLKFS.2 ECLKFS.1 ECLKFS.0

Bit Symbol Function

SCECLK.7 – SCECLK.6 – SCECLK.5 ECLKFS.5 SCECLK.4 ECLKFS.4 SCECLK.3 ECLKFS.3 SCECLK.2 ECLKFS.2 SCECLK.1 ECLKFS.1 SCECLK.0 ECLKFS.0

External Smart Card CLK Frequency Select - Division factor to determine external smart card CLK frequency. MCLK clock is divided by (register value + 1) to clock the ETU divider, and then by 2 to generate SCLK. Default ratio is 13. The programmed value in this register is applied to the divider after this value is written, in such a manner as to produce a glitch-free output, regardless of the selection of active interface. A register value = 0 will default to the same effect as register value = 1.

Rev. 1.4 93

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73S1210F Data Sheet DS_1210F_001

Parity Control Register (SPa r Ctl): 0xFE11  0x00

This register provides the ability to configure the parity circuitry on the smart card int erf ace. T he set tings apply to both integrated smart card interfaces.

Table 88: The SParCtl Register

MSB LSB

– DISPAR BRKGEN BRKDET RETRAN DISCRX INSPE FORCPE

Bit Symbol Function

SParCtl.7 –

Disable Parity Check – 1 = disabled, 0 = enabled. If enabled, the UART will

SParCtl.6 DISPAR

check for even parity (the number of 1’s including the parity bit is even) on

every character. This also applies to the TS during ATR.

Break Generation Disable – 1 = disabled, 0 = enabled. If enabled, and T=0

SParCtl.5 BRKGEN

protocol, the UART will generate a Break to the smart card if a parity error is

detected on a receive character. No Break will be generated if parity

checking is disabled. This also applies to TS during ATR.

SParCtl.4 BRKDET

Break Detection Disable – 1 = disabled, 0 = enabled. If enabled, and T=0

protocol, the UART will detect the generation of a Break by the smart card.

Retransmit Byte – 1 = enabled, 0 = disabled. If enabled and a Break is

SParCtl.3 RETRAN

detected from the smart card (Break Detection must be enabled), the last

character will be transmitted again. This bit applies to T=0 protocol.

Discard Received Byte – 1 = enabled, 0 = disabled. If enabled and a parity

SParCtl.2 DISCRX

error is detected (Parity checking must be enabled), the last character

received will be discarded. This bit applies to T=0 protocol.

Insert Parity Error – 1 = enabled, 0 = disabled. Used for test purposes. If

SParCtl.1 INSPE

enabled, the UART will insert a parity error in every character transmitted by

generating odd parity instead of even parity for the character.

Force Parity Error – 1 = enabled, 0 = disabled. Used for test purposes. If

SParCtl.0 FORCPE

enabled, the UART will generate a parity error on a character received from

the smart card.

94 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

Byte Control Register (SBy te Ctl): 0xFE12  0x2C

This register controls the processing of characters and the detection of the TS byte. When receiving, a Break is asserted at 10.5 ETU after the beginning of the start bit. Break f rom the card is sampled at 11 ETU.

Table 89: The SByteCtl Register

MSB LSB

– DETTS DIRTS BRKDUR.1 BRKDUR.0 – – –

Bit Symbol Function

SByteCtl.7 –

Detect TS Byte – 1 = Next Byte is TS, 0 = Next byte is not TS. When set, the hardware will treat the next character received as the TS and determine if direct or indirect convention is being used. Direct convention is the default

SByteCtl.6 DETTS

used if firmware does not set this bit prior to transmission of TS by the smart card to the firmware. The hardware will check parity and generate a break as defined by the DISPAR and BRKGEN bits in the parity control register. T hi s bit is cleared by hardware after TS is received. TS is decoded prior to the FIFO and is stored in the receive FIFO.

Direct Mode TS Select – 1 = direct mode, 0 = indirect mode. Set/cleared by hardware when TS is processed indicating either direct/indirect mode of

SByteCtl.5 DIRTS

operation. When switching between smart cards, the firmware should write the bit appropriately since this register is not unique to an individual smart card (firmware should keep track of this bit).

SByteCtl.4 BRKDUR.1

Break Duration Select – 00 = 1 ETU, 01 = 1.5 ETU, 10 = 2 ETU, 11 = reserved. Determines the length of a Break signal which is generated

SByteCtl.3 BRKDUR.0

when detecting a parity error on a character reception in T=0 mode. SByteCtl.2 – SByteCtl.1 – SByteCtl.0 –

Rev. 1.4 95

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73S1210F Data Sheet DS_1210F_001

FD Control Register (FDReg): 0xFE13  0x11

This register uses the transmission factors F and D to set the ETU (baud) rate. The values in this register are mapped to the ISO 7816 conversion factors as described below. The CLK signal for each interface is created by dividing a high-frequency, intermediate signal (MSCLK) by 2. The ETU baud rat e is created by dividing MSCLK by 2 times the Fi/Di ratio specified by the codes below. For example, if FI = 0001 and DI = 0001, the ratio of Fi/Di is 372/1. Thus the ETU divider is configured to di vide by 2 * 372 = 744. The maximum supported F/D ratio is 4096.

Table 90: The FDReg Register

MSB LSB

FVAL.3 FVAL.2 FVAL.1 FVAL.0 DVAL.3 DVAL.2 DVAL.1 DVAL.0

Table 91: The FDReg Bit Functions

Bit Symbol Function

FDReg.7 FVAL.3 FDReg.6 FVAL.2 FDReg.5 FVAL.1 FDReg.4 FVAL.0

Refer to the Table 93 above. This value is converted per the table to set the divide ratio used to generate the baud rate (ETU). Default, also used for ATR, is 0001 (Fi = 372). This value is used by the selected interface.

FDReg.3 DVAL.3 FDReg.2 DVAL.2 FDReg.1 DVAL.1

Refer to Table 93 above. This value is used to set the divide ratio used to generate the smart card CLK. Default, also used for ATR, is 0001 (Di = 1).

FDReg.0 DVAL.0

Table 92: Divider Ratios Provided by the ETU Counter

FI (code) 0000 0001 0010 0011 0100 0101 0110 0111 Fi (ratio) 372 372 558 744 1116 1488 1860 FCLK max 4 5 6 8 12 16 20

1860⊕ 20⊕

FI(code) 1000 1001 1010 1011 1100 1101 1110 1111 Fi(ratio) FCLK max

512⊕ 5⊕

512 768 1024 1536 2048 5 7.5 10 15 20

2048⊕ 2048⊕ 20⊕ 20⊕

DI(code) 0000 0001 0010 0011 0100 0101 0110 0111 Di(ratio)

1⊕

1 2 4 8 16 32

32⊕

DI(code) 1000 1001 1010 1011 1100 1101 1110 1111 Di(ratio) 12 20

16⊕ 16⊕ 16⊕ 16⊕ 16⊕ 16⊕

Note: values marked with ⊕ are not included in the ISO definition and arbitrary v al ues have been assigned.

The values given below are used by the ETU divider to create the ETU clock. The entries that are not shaded will result in precise CLK/ETU per ISO requirements. Shaded areas are not precise but are within 1% of the target value.

96 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

0110

116

128

Table 93: Divider Values for the ETU Clock

Fi code 0000 0001 0010 0011 0100 0101 Di

code

F→ D↓

372 372 558 744 1116 1488

0001 1 744 744 1116 1488 2232 2976 0010 2 372 372 558 744 1116 1488 0011 4 186 186 279 372 558 744 0100 8 93 93 138 186 279 372 1000 12 62 62 93 124 186 248 0101 16 47 47 70 93 140 186 1001 20 37 37 56 74 112 149 0110 32 23 23 35 47 70 93

Fi code 0110 1001 1010 1011 1100 1101 Di

code

F→ D↓

1860 512 768 1024 1536 2048

0001 1 3720 1024 1536 2048 3072 4096 0010 2 1860 512 768 1024 1536 2048 0011 4 930 256 384 512 768 1024 0100 8 465 128 192 256 384 512 1000 12 310 85 128 171 256 341 0101 16 233 64 96 128 192 256 1001 20 186 51 77 102 154 205

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73S1210F Data Sheet DS_1210F_001

CRC MS Value Registers (CRCMsB): 0xFE14  0xFF, (CRCLsB): 0xFE15  0xFF

Table 94: The CRCMsB Register

MSB LSB

CRC.15 CRC.14 CRC.13 CRC.12 CRC.11 CRC.10 CRC.9 CRC.8

MSB LSB

CRC.7 CRC.6 CRC.5 CRC.4 CRC.3 CRC.2 CRC.1 CRC.0

The 16-bit CRC value forms the TX CRC word in TX mode (write value) and the RX CRC in RX mode (read value). The initial value of CRC to be used when generating a CRC to be transmitted at t he end of a message (after the last TX byte is sent) when enabled in T=1 mode. Should be reloaded at the beginning of every message to be transmitted. When using CRC, both CRC registers should be initialized to FF. When using LRC, the CRCLsB value register should be loaded to 00. When receiving a message, the firmware should load this with the initial value and then read this register to get the final value at the end of the message. These registers need to be reloaded for each new message to be received. When in LRC mode, bits (7:0) are used and bits (15:8) are undefined. During LRC/CRC checking and generation, this register is updated with the current value and can be read to aid in debugging. This information will be transmitted to the smart card using the tim i ng specif i ed by the Guard Time register. When checking CRC/LRC on an incoming message (CRC/LRC is checked against the data and CRC/LRC), the firmware reads the final value after the message has been received and determines if an error occurred (= 0x1D0F (CRC) no error, else error; = 0 (LRC) no error, else error). When a message is received, the CRC/LRC is stored in the FIFO. The polynomial used to generate and check CRC is x

+ x12+ x5 +1. When in indirect convention, the CRC is generated prior to the conversion into indirect convention. When in indirect convention, the CRC is checked after the conversion out of indirect convention. For a given message, the CRC generated (and readable from this register) will be the same whether indirect or direct convention is used to transmit the data to the smart card. T he CRCLsB / CRCMsB registers will be updated with CRC/LRC whenever bits are being received or transmitted from/to the smart card (even if CRCEN is not set and in mode T1). They are available to the firmware to use if desired.

98 Rev. 1.4

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DS_1210F_001 73S1210F Data Sheet

Block Guard Time Register (BGT): 0xFE16  0x10

This register contains the Extra Guard Time Value (EGT) most-significant bit. The Extra Guard Time indicates the minimum time between the leading edges of the start bit of consecutive characters. The delay is depends on the T=0/T=1 mode. Used in transmit mode. This register also contains the Block Guard Time (BGT) value. Block Guard Time is the minimum time between the leadi ng edge of the start bit of the last character received and the leading edge of the start bit of the first character transmitted. This should not be set less than the character length. The transmission of the first character will be held off until BGT has elapsed regardless of the TX data and TX/RX control bit tim i ng.

Table 95: The BGT Register

MSB LSB

EGT.8 – – BGT.4 BGT.3 BGT.1 BGT.2 BGT.0

Bit Symbol Function

BGT.7 EGT.8 Most-significant bit for 9-bit EGT timer. See the EGT register. BGT.6 – BGT.5 – BGT.4 BGT.4 BGT.3 BGT.3 BGT.2 BGT.2 BGT.1 BGT.1

Time in ETUs between the start bit of the last received character to start bit of the first character transmitted to the smart card. Default value is 22.

BGT.0 BGT.0

Extra Guard Time Register (EGT): 0xFE17  0x0C

This register contains the Extra Guard Time Value (EGT) least-significant byte. The Ex tra Guard Time indicates the minimum time between the leading edges of the start bit of consecutive characters. The delay depends on the T=0/T=1 mode. Used in transmit mode.

Table 96: The EGT Register

MSB LSB

EGT.7 EGT.6 EGT.5 EGT.4 EGT.3 EGT.1 EGT.2 EGT.0

Bit Function

EGT.7 EGT.6 EGT.5 EGT.4 EGT.3 EGT.2

Time in ETUs between start bits of consecutive characters. In T=0 mode, the minimum is 1. In T=0, the leading edge of the next st art bit may be delayed if there is a break detected from the smart card. Default value is 12. In T=0 mode, regardless of the value loaded, the minimum value is 12, and for T=1 mode, the minimum value is 11.

EGT.1 EGT.0

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73S1210F Data Sheet DS_1210F_001

Block Wait Time Registers (BWTB0): 0xFE1B  0x00, (BWTB1): 0xFE1A  0x00, (BWTB2): 0xFE19

 0x00, (BWTB3): 0xFE18  0x00

These registers are used to set the Block Waiting Time(27:0) (BWT). All of these parameters define the maximum time the 73S1210F will have to wait for a character from the smart card. T hese regist ers serve a dual purpose. When T=1, these registers are used to set up the block wait time. The block wait time defines the time in ETUs between the beginning of the last character sent to smart card and the start bit of the first character received from smart card. It can be used to detect an unresponsive card and should be loaded by firmware prior to writing the last TX byte. When T=0, these registers are used to set up the work wait time. The work wait time is defined as the time between the leading edge of two consecutive characters being sent to or from the card. If a timeout occurs, an interrupt is generated to the firmware. The firmware can then take appropriate action. A Wait Time Extension (WTX) is supported with t he 28bit BWT.

Table 97: The BWTB0 Register

MSB LSB

BWT.7 BWT.6 BWT.5 BWT.4 BWT.3 BWT.1 BWT.2 BWT.0

Table 98: The BWTB1 Register

MSB LSB

BWT.15 BWT.14 BWT.13 BWT.12 BWT.11 BWT.10 BWT.9 BWT.8

Table 99: The BWTB2 Register

MSB LSB

BWT.23 BWT.22 BWT.21 BWT.20 BWT.19 BWT.18 BWT.17 BWT.16

Table 100: The BWTB3 Register

MSB LSB

– – – – BWT.27 BWT.26 BWT.25 BWT.24

Character Wait Time Registers (CWTB0): 0xFE1D  0x00, (CWTB1): 0xFE1C  0x00

These registers are used to hold the Character Wait Time(15:0) (CWT) or Initial Waiting Time(15:0) (IWT) depending on the situation. Both the IWT and the CWT measure the time in E TUs bet ween t he l eadi ng edge of the start of the current character received from the smart card and the leading edge of the start of the next character received from the smart card. The only difference is the mode in which the card is operating. When T=1 these registers are used to configure the CWT and these registers configure the IWT when the ATR is being received. These registers should be loaded prior to receiving characters from the smart card. Firmware must manage which time is stored in the register. If a timeout occurs, an interrupt i s generated to the firmware. The firmware can then take appropriate action.

Table 101: The CWTB0 Register

MSB LSB

CWT.7 CWT.6 CWT.5 CWT.4 CWT.3 CWT.1 CWT.2 CWT.0

Table 102: The CWTB1 Register

MSB LSB

CWT.15 CWT.14 CWT.13 CWT.12 CWT.11 CWT.10 CWT.9 CWT.8

100 Rev. 1.4

Datasheet 73S1210F Datasheet (TERIDIAN Semiconductor)

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Hardware Description

1.7.5.1 Interrupt Overview

1.7.5.2 Special Function Registers for Interrupts

1.7.5.3 External Interrupts

1.7.5.4 Power Down Interrupt Logic

1.7.5.5 Interrupt Priority Level Structure

1.7.5.6 Interrupt Sources and Vectors

1.7.6.1 Serial Interface 0

1.7.6.2 Serial Interface 1