Page 1
SN54ACT16240, 74ACT16240
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS137C – JULY 1989 – REVISED NOVEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
Family
D
Inputs Are TTL-Voltage Compatible
D
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
D
Flow-Through Architecture Optimizes
PCB Layout
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Spacings
description
The SN54ACT16240 and 74ACT16240 are 16-bit
buffers or line drivers designed specifically to
improve both the performance and density of
3-state memory address drivers, clock drivers,
and bus-oriented receivers and transmitters. The
devices can be used as four 4-bit buffers, two 8-bit
buffers, or one 16-bit buffer. These devices
provide inverting outputs and symmetrical
active-low output-enable (OE
) inputs.
The 74ACT16240 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The SN54ACT16240 is characterized for operation over the full military temperature range of –55°C to 125°C.
The 74ACT16240 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each section)
INPUTS
OUTPUT
OE A
Y
L H L
L LH
H X Z
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Y1
1Y2
GND
1Y3
1Y4
V
CC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
V
CC
4Y1
4Y2
GND
4Y3
4Y4
4OE
2OE
1A1
1A2
GND
1A3
1A4
V
CC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
V
CC
4A1
4A2
GND
4A3
4A4
3OE
SN54ACT16240 . . . WD PACKAGE
74ACT16240 . . . DL PACKAGE
(TOP VIEW)
Page 2
SN54ACT16240, 74ACT16240
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS137C – JULY 1989 – REVISED NOVEMBER 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
47
1A1
46
1A2
44
1A3
43
1A4
1Y1
2
1Y2
3
1Y3
5
1Y4
6
41
2A1
40
2A2
38
2A3
37
2A4
2Y1
8
2Y2
9
2Y3
11
2Y4
12
36
3A1
35
3A2
33
3A3
32
3A4
3Y1
13
3Y2
14
3Y3
16
3Y4
17
30
4A1
29
4A2
27
4A3
26
4A4
4Y1
19
4Y2
20
4Y3
22
4Y4
23
EN1
1
EN4
24
1
2
3
4
1
1
1
1
1OE
2OE
3OE
4OE
EN2
48
EN3
25
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Page 3
SN54ACT16240, 74ACT16240
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS137C – JULY 1989 – REVISED NOVEMBER 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1OE
1
1A1
1A2
1A3
1A4
47
46
44
43
1Y1
1Y2
1Y3
1Y4
2
3
5
6
2OE
48
2A1
2A2
2A3
2A4
41
40
38
37
2Y1
2Y2
2Y3
2Y4
8
9
11
12
3OE
25
3A1
3A2
3A3
3A4
36
35
33
32
3Y1
3Y2
3Y3
3Y4
13
14
16
17
4OE
24
4A1
4A2
4A3
4A4
30
29
27
26
4Y1
4Y2
4Y3
4Y4
19
20
22
23
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package 1.2 W. . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Page 4
SN54ACT16240, 74ACT16240
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS137C – JULY 1989 – REVISED NOVEMBER 1996
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54ACT16240 74ACT16240
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
V
I
Input voltage 0 V
CC
0 V
CC
V
V
O
Output voltage 0 V
CC
0 V
CC
V
I
OH
High-level output current –24 –24 mA
I
OL
Low-level output current 24 24 mA
∆t/∆v Input transition rise or fall rate 0 10 0 10 ns/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ACT16240 74ACT16240
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
4.5 V 4.4 4.4 4.4
I
OH
= –50 µ
A
5.5 V 5.4 5.4 5.4
4.5 V 3.94 3.7 3.8
V
OH
I
OH
= –24
mA
5.5 V 4.94 4.7 4.8
V
IOH = –50 mA
†
5.5 V 3.85
IOH = –75 mA
†
5.5 V 3.85
4.5 V 0.1 0.1 0.1
I
OL
= 50 µ
A
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.5 0.44
V
OL
I
OL
= 24
mA
5.5 V 0.36 0.5 0.44
V
IOL = 50 mA
†
5.5 V 1.65
IOL = 75 mA
†
5.5 V 1.65
I
I
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
I
OZ
VO = VCC or GND 5.5 V ±0.5 ±10 ±5 µA
I
CC
VI = VCC or GND, IO = 0 5.5 V 8 160 80 µA
∆I
CC
‡
One input at 3.4 V ,
Other inputs at VCC or GND
5.5 V 0.9 1 1 mA
C
i
VI = VCC or GND 5.5 V 4.5 pF
C
o
VO = VCC or GND 5 V 12 pF
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Page 5
SN54ACT16240, 74ACT16240
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS137C – JULY 1989 – REVISED NOVEMBER 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
FROM TO
TA = 25°C SN54ACT16240 74ACT16240
PARAMETER
(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
UNIT
t
PLH
2.3 5 7.7 2 9.5 2.3 8.5
t
PHL
A
Y
4.1 6.7 9.2 3 11.5 4.1 10.2
ns
t
PZH
2.6 5.6 8.5 2 10.1 2.6 9.4
t
PZL
OE
Y
3.3 6.7 10.2 2.5 12.2 3.3 11.4
ns
t
PHZ
5.9 8.3 11 4.5 12.7 5.9 12
t
PLZ
OE
Y
5.1 7.4 9.9 4 12 5.1 10.7
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
p
p
p
Outputs enabled
p
38
p
CpdPower dissipation capacitance per driver
Outputs disabled
C
L
=
50 pF
,
f
= 1 MHz
9
pF
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2 × V
CC
500 Ω
500 Ω
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
t
PHL
t
PLH
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V
1.5 V
1.5 V 1.5 V
[
V
CC
3 V
0 V
50% V
CC
50% V
CC
V
OH
V
OL
0 V
50% V
CC
20% V
CC
50% V
CC
80% V
CC
[
0 V
3 V
GND
Open
Input
Output
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Page 6
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
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In order to minimize risks associated with the customer’s applications, adequate design and operating
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intellectual property right of TI covering or relating to any combination, machine, or process in which such
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Copyright 1998, Texas Instruments Incorporated
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