Datasheet 5962R8960101SSA, 5962R8960101SRA, 5962R8960101S2A, 5962R8960101BSA, 5962R8960101BRA Datasheet (NSC)

54AC574•54ACT574
Octal D-Type Flip-Flop with TRI-STATE

®

Outputs

General Description

The ’AC/’ACT574 is a high-speed, low power octal flip-flop
with a buffered common Clock (CP) and a buffered common
Output Enable (OE). The information presented to the D in­puts is stored in the flip-flops on the LOW-to-HIGH Clock
(CP) transition.

The ’AC/’ACT574isfunctionally identical to the ’AC/’ACT374
except for the pinouts.

Features

n ICCand IOZreduced by 50

%

n Inputs and outputs on opposite sides of package

allowing easy interface with microprocessors

n Useful as input or output port for microprocessors
n Functionally identical to ’AC/’ACT374
n TRI-STATE outputs for bus-oriented applications
n Outputs source/sink 24 mA
n ’ACT574 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)

— ’ACT574: 5962-89601

Logic Symbols

Pin Names Description

D

0–D7

Data Inputs
CP Clock Pulse Input
OE

TRI-STATE Output Enable Input
O

0–O7

TRI-STATE Outputs

TRI-STATE®is a registered trademark of National Semiconductor Corporation.
FACT

™

is a trademark of Fairchild Semiconductor Corporation.

DS100256-1

IEEE/IEC

DS100256-4

September 1998

54AC574

•

54ACT574 Octal D-Type Flip-Flop with TRI-STATE Outputs

© 1998 National Semiconductor Corporation DS100256 www.national.com

Connection Diagrams

Functional Description

The ’AC/’ACT574 consists of eight edge-triggered flip-flops
with individual D-type inputs and TRI-STATE true outputs.
The buffered clock and buffered Output Enable are common
to all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time require­ments on the LOW-to-HIGH Clock (CP) transition. With the
Output Enable (OE) LOW, the contents of the eight flip-flops
are available at the outputs. When OE is HIGH, the outputs
go to the high impedance state. Operation of the OE input
does not affect the state of the flip-flops.

Function Table

Inputs Internal Outputs Function

OE

CP D Q O

N

H H L NC Z Hold
H H H NC Z Hold
H N L L Z Load
H N H H Z Load
L N L L L Data Available
L N H H H Data Available
L H L NC NC No Change in Data
L H H NC NC No Change in Data

H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
Z=High Impedance
N=LOW-to-HIGH Transition
NC=No Change

Pin Assignment for DIP,

and Flatpak

DS100256-2

Pin Assignment

for LCC

DS100256-3

www.national.com 2

Logic Diagram

DS100256-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

www.national.com3

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V

CC

) −0.5V to +7.0V

DC Input Diode Current (I

IK

)

V

I

=

−0.5V −20 mA

V

I

=

V

CC

+0.5V +20 mA

DC Input Voltage (V

I

) −0.5V to VCC+0.5V

DC Output Diode Current (I

OK

)

V

O

=

−0.5V −20 mA

V

O

=

V

CC

+0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to VCC+0.5V

DC Output Source or Sink Current

(I

O

)

±

50 mA

DC V

CC

or Ground Current

Per Output Pin (I

CC

or I

GND

)

±

50 mA

Storage Temperature (T

STG

) −65˚C to +150˚C

Junction Temperature (T

J

)

CDIP 175˚C

Recommended Operating
Conditions

Supply Voltage (VCC)

(Unless Otherwise Specified) (AC) 2.0V to 6.0V

(ACT) 4.5V to 5.5V

Input Voltage (V

I

) 0VtoV

CC

Output Voltage (VO) 0VtoV

CC

Operating Temperature (TA)

54AC/ACT −55˚C to +125˚C

Minimum Input Edge Rate (∆V/∆t)

’AC Devices
V

IN

from 30%to 70%of V

CC

V

CC

@

3.3V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate (∆V/∆t)

’ACT Devices
V

IN

from 0.8V to 2.0V

V

CC

@

4.5V, 5.5V 125 mV/ns

Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom­mend operation of FACT

™

circuits outside databook specifications.

DC Characteristics for ’AC Family Devices

54AC

Symbol Parameter V

CC

T

A

=

Units Conditions

(V) −55˚C to +125˚C

Guaranteed Limits

V

IH

Minimum High 3.0 2.1 V

OUT

=

0.1V

Level Input 4.5 3.15 V or V

CC

− 0.1V

Voltage 5.5 3.85

V

IL

Maximum Low 3.0 0.9 V

OUT

=

0.1V

Level Input 4.5 1.35 V or V

CC

− 0.1V

Voltage 5.5 1.65

V

OH

Minimum High 3.0 2.9 I

OUT

=

−50 µA
Level Output 4.5 4.4 V
Voltage 5.5 5.4

(Note 2)
V

IN

=

V

IL

or V

IH

3.0 2.4 −12 mA

4.5 3.7 V I

OH

−24 mA

5.5 4.7 −24 mA

V

OL

Maximum Low 3.0 0.1 I

OUT

=

50 µA
Level Output 4.5 0.1 V
Voltage 5.5 0.1

(Note 2)
V

IN

=

V

IL

or V

IH

3.0 0.50 12 mA

4.5 0.50 V I

OL

24 mA

5.5 0.50 24 mA

I

IN

Maximum Input 5.5

±

1.0 µA V

I

=

V

CC

, GND

Leakage Current

I

OZ

Maximum VI(OE)=VIL,V

IH

TRI-STATE 5.5

±

5.0 µA V

I

=

V

CC,VGND

Leakage Current V

O

=

V

CC

, GND

www.national.com 4

DC Characteristics for ’AC Family Devices (Continued)

54AC

Symbol Parameter V

CC

T

A

=

Units Conditions

(V) −55˚C to +125˚C

Guaranteed Limits

I

OLD

(Note 3) Minimum
Dynamic Output
Current

5.5 50 mA V

OLD

=

1.65V

I

OHD

5.5 −50 mA V

OHD

=

3.85V

I

CC

Maximum Quiescent 5.5 80.0 µA V

IN

=

V

CC

Supply Current or GND

Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

DC Characteristics for ’ACT Family Devices

54ACT

Symbol Parameter V

CC

T

A

=

Units Conditions

(V) −55˚C to +125˚C

Guaranteed Limits

V

IH

Minimum High
Level Input
Voltage

4.5 2.0

V

V

OUT

=

0.1V

5.5 2.0 or V

CC

− 0.1V

V

IL

Maximum Low
Level Input
Voltage

4.5 0.8

V

V

OUT

=

0.1V

5.5 0.8 or V

CC

− 0.1V

V

OH

Minimum High
Level

4.5 4.4 V I

OUT

=

−50 µA

5.5 5.4
(Note 4)

V

IN

=

V

IL

or V

IH

4.5 3.70 V I

OH

−24 mA

5.5 4.70 −24 mA

V

OL

Maximum Low
Level Output
Voltage

4.5 0.1 V I

OUT

=

50 µA

5.5 0.1
(Note 4)

V

IN

=

V

IL

or V

IH

4.5 0.50 V I

OL

24 mA

5.5 0.50 24 mA

I

IN

Maximum Input 5.5

±

1.0 µA V

I

=

V

CC

, GND

Leakage Current

I

OZ

Maximum
TRI-STATE
Leakage Current

5.5

±

5.0 µA

V

I

=

V

IL,VIH

V

O

=

V

CC

, GND

I

CCT

Maximum ICC/Input 5.5 1.6 mA V

I

=

V

CC

− 2.1V

I

OLD

(Note 5) Minimum
Dynamic Output
Current

5.5 50 mA V

OLD

=

1.65V

I

OHD

5.5 −50 mA V

OHD

=

3.85V

I

CC

Maximum Quiescent 5.5 80.0 µA V

IN

=

V

CC

Supply Current or GND

Note 4: All outputs loaded; thresholds on input associated with output under test.
Note 5: Maximum test duration 2.0 ms, one output loaded at a time.

www.national.com5

AC Electrical Characteristics for ’AC Family Devices

54AC

V

CC

T

A

=

−55˚C

Symbol Parameter (V) to +125˚C Units

(Note 6) C

L

=

50 pF

Min Max

f

MAX

Maximum Clock 3.3 55 MHz
Frequency 5.0 85

t

PLH

Propagation Delay 3.3 1.0 16.5 ns
CP to O

n

5.0 1.5 11.5

t

PHL

Propagation Delay 3.3 1.0 15.0 ns
CP to O

n

5.0 1.5 10.5

t

PZH

Output Enable Time 3.3 1.0 13.0 ns

5.0 1.5 9.5

t

PZL

Output Enable Time 3.3 1.0 12.5 ns

5.0 1.5 9.5

t

PHZ

Output Disable Time 3.3 1.0 14.0 ns

5.0 1.5 11.5

t

PLZ

Output Disable Time 3.3 1.0 10.5 ns

5.0 1.5 9.0

Note 6: Voltage Range 3.3 is 3.3V±0.3V

Voltage Range 5.0 is 5.0V

±

0.5V

AC Operating Requirements for ’AC Family Devices

54AC

V

CC

T

A

=

−55˚C

Symbol Parameter (V) to +125˚C Units

(Note 7) C

L

=

50 pF

Guaranteed Minimum

t

s

Set-Up Time, HIGH or LOW 3.3 4.5 ns
D

n

to CP 5.0 3.5

t

h

Hold Time, HIGH or LOW 3.3 2.5 ns
D

n

to CP 5.0 2.5

t

w

CP Pulse Width 3.3 7.5 ns
HIGH or LOW 5.0 5.0

Note 7: Voltage Range 3.3 is 3.3V±0.3V

Voltage Range 5.0 is 5.0V

±

0.5V

www.national.com 6

AC Electrical Characteristics for ’ACT Family Devices

54ACT

V

CC

T

A

=

−55˚C

Symbol Parameter (V) to +125˚C Units

(Note 8) C

L

=

50 pF

Min Max

f

MAX

Maximum Clock
Frequency

5.0 70 ns

t

PLH

Propagation Delay 5.0 1.5 13.5 ns
CP to O

n

t

PHL

Propagation Delay 5.0 1.5 12.5 ns
CP to O

n

t

PZH

Output Enable Time 5.0 1.5 11.0 ns

t

PZL

Output Enable Time 5.0 1.5 11.0 ns

t

PHZ

Output Disable Time 5.0 1.5 12.0 ns

t

PLZ

Output Disable Time 5.0 1.5 10.0 ns

Note 8: Voltage Range 5.0 is 5.0V±0.5V

AC Operating Requirements for ’ACT Family Devices

54ACT

V

CC

T

A

=

−55˚C

Symbol Parameter (V) to +125˚C Units

(Note 9) C

L

=

50 pF

Guaranteed Minimum

t

s

Set-Up Time, HIGH or LOW 5.0 3.5 ns
D

n

to CP

t

h

Hold Time, HIGH or LOW 5.0 2.0 ns
D

n

to CP

t

w

CP Pulse Width 5.0 5.0 ns
HIGH or LOW

Note 9: Voltage Range 5.0 is 5.0V±0.5V

Capacitance

Symbol Parameter Typ Units Conditions

C

IN

Input Capacitance 4.5 pF V

CC

=

OPEN

C

PD

Power Dissipation Capacitance 40.0 pF V

CC

=

5.0V

www.national.com7

Physical Dimensions inches (millimeters) unless otherwise noted

20 Terminal Ceramic Leadless Chip Carrier (L)

NS Package Number E20A

www.national.com 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20 Lead Ceramic Dual-In-Line Package (D)

NS Package Number J20A

20 Lead Ceramic Flatpak (F)

NS Package Number W20A

www.national.com9

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE­VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI­CONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or sys­tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail­ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.

2. A critical component in any component of a life support
device or system whose failure to perform can be rea­sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

National Semiconductor
Corporation

Americas
Tel: [phone]
Fax: [phone]
Email: [e-mail]

www.national.com

National Semiconductor
Europe

Fax: [phone]

Email: [e-mail]
Deutsch Tel: [phone]
English Tel: [phone]
Français Tel: [phone]
Italiano Tel: [phone]

National Semiconductor
Asia Pacific Customer
Response Group

Tel: [phone]
Fax: [phone]
Email: [e-mail]

National Semiconductor
Japan Ltd.

Tel: [phone]
Fax: [phone]

54AC574

•

54ACT574 Octal D-Type Flip-Flop with TRI-STATE Outputs

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.