Datasheet 56F801 Datasheet (Freescale)

56F801

Data Sheet

Preliminary Technical Data

56F800
16-bit Digital Signal Controllers

DSP56F801
Rev. 15
10/2005

freescale.com

56F801 General Description

• Up to 30 MIPS operation at 60MHz core frequency

• Up to 40 MIPS operation at 80MHz core frequency

• DSP and MCU functionality in a unified,
C-efficient architecture

• MCU-friendly instruction set supports both DSP and
controller functions: MAC, bit manipulation unit, 14
addressing modes

• Hardware DO and REP loops

• 6-channel PWM Module

• Two 4-channel, 12-bit ADCs

• Serial Communications Interface (SCI)

• Serial Peripheral Interface (SPI)

6

PWM Outputs

Fault Input

A/D1

4

A/D2

4

3

2

4

ADC

VREF

Quad Timer C

Quad Timer D

or GPIO

SCI0

or

GPIO

SPI

or

GPIO

*includes TCS pin which is reserved for factory use and is tied to VSS

PWMA

Interrupt

Controller

Program Memory

8188 x 16 Flash

1024 x 16 SRAM

Boot Flash

2048 x 16 Flash

Data Memory

2048 x 16 Flash

1024 x 16 SRAM

COP/

Watchdog

Applica-

tion-Specific

Memory &

Peripherals

RESET

IRQA

Program Controller

and

Hardware Looping Unit

•

•

•

COP RESET

MODULE CONTROLS

ADDRESS BUS [8:0]

DATA BUS [15:0]

PAB

PDB

XDB2

CGDB

XAB1

XAB2

6

JTAG/
OnCE

Port

Address

Generation

Unit

•

•

INTERRUPT
CONTROLS

IPBus Bridge

•8K × 16-bit words (16KB) Program Flash

•1K × 16-bit words (2KB) Program RAM

•2K × 16-bit words (4KB) Data Flash

•1K × 16-bit words (2KB) Data RAM

•2K × 16-bit words (4KB) Boot Flash

• General Purpose Quad Timer

• JTAG/OnCE

TM

port for debugging

• On-chip relaxation oscillator

• 11 shared GPIO

• 48-pin LQFP Package

VCAPC VDDVSSV

24 5*

Digital Reg

Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers

Two 36-bit Accumulators

Low Voltage

Supervisor

16-Bit
56800

Core

DDAVSSA

Analog Reg

Manipulation

Clock Gen
or Optional

Internal

Relaxation Osc.

Bit

Unit

PLL

•

•

•

IPBB

CONTROLS

16 16

(IPBB)

GPIOB3/XTAL

GPIOB2/EXTAL

56F801 Block Diagram

56F801 Technical Data, Rev. 15

Freescale Semiconductor 3

Part 1 Overview

1.1 56F801 Features

1.1.1 Digital Signal Processing Core

• Efficient 16-bit 56800 family controller engine with dual Harvard architecture

• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Two 36-bit accumulators including extension bits

• 16-bit bidirectional barrel shifter

• Parallel instruction set with unique processor addressing modes

• Hardware DO and REP loops

• Three internal address buses and one external address bus

• Four internal data buses and one external data bus

• Instruction set supports both DSP and controller functions

• Controller style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/OnCE debug programming interface

1.1.2 Memory

• Harvard architecture permits as many as three simultaneous accesses to Program and Data memory

• On-chip memory including a low-cost, high-volume Flash solution

—8K × 16 bit words of Program Flash

—1K × 16-bit words of Program RAM

—2K × 16-bit words of Data Flash

—1K × 16-bit words of Data RAM

—2K × 16-bit words of Boot Flash

• Programmable Boot Flash supports customized boot code and field upgrades of stored code through a
variety of interfaces (JTAG, SPI)

1.1.3 Peripheral Circuits for 56F801

• Pulse Width Modulator (PWM) with six PWM outputs, two Fault inputs, fault-tolerant design with deadtime
insertion; supports both center- and edge-aligned modes

• Two 12-bit, Analog-to-Digital Converters (ADCs), which support two simultaneous conversions with two
4-multiplexed inputs; ADC and PWM modules can be synchronized

• General Purpose Quad Timer: Timer D with three pins (or three additional GPIO lines)

• Serial Communication Interface (SCI) with two pins (or two additional GPIO lines)

• Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines)

56F801 Technical Data, Rev. 15

4 Freescale Semiconductor

56F801 Description

• Eleven multiplexed General Purpose I/O (GPIO) pins

• Computer-Operating Properly (COP) watchdog timer

• One dedicated external interrupt pin

• External reset pin for hardware reset

• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging

• Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock

• Oscillator flexibility between either an external crystal oscillator or an on-chip relaxation oscillator for
lower system cost and two additional GPIO lines

1.1.4 Energy Information

• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs

• Uses a single 3.3V power supply

• On-chip regulators for digital and analog circuitry to lower cost and reduce noise

• Wait and Stop modes available

1.2 56F801 Description

The 56F801 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and
compact program code, the 56F801 is well-suited for many applications. The 56F801 includes many
peripherals that are especially useful for applications such as motion control, smart appliances, steppers,
encoders, tachometers, limit switches, power supply and control, automotive control, engine
management, noise suppression, remote utility metering, and industrial control for power, lighting, and
automation.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.

The 56F801 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F801 also provides one external
dedicated interrupt lines and up to 11 General Purpose Input/Output (GPIO) lines, depending on peripheral
configuration.

The 56F801 controller includes 8K words (16-bit) of Program Flash and 2K words of Data Flash (each
programmable through the JTAG port) with 1K words of both Program and Data RAM. A total of 2K
words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines
that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash
memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory
can also be either bulk or page erased.

56F801 Technical Data, Rev. 15

Freescale Semiconductor 5

A key application-specific feature of the 56F801 is the inclusion of a Pulse Width Modulator (PWM)
module. This modules incorporates six complementary, individually programmable PWM signal outputs
to enhance motor control functionality. Complementary operation permits programmable dead-time
insertion, and separate top and bottom output polarity control. The up-counter value is programmable to
support a continuously variable PWM frequency. Both edge- and center-aligned synchronous pulse width
control (0% to 100% modulation) are supported. The device is capable of controlling most motor types:
ACIM (AC Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM
(Switched and Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection
and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard
opto-isolators. A “smoke-inhibit”, write-once protection feature for key parameters is also included. The
PWM is double-buffered and includes interrupt control to permit integral reload rates to be programmable
from 1 to 16. The PWM modules provide a reference output to synchronize the Analog-to-Digital
Converters.

The 56F801 incorporates an 8 input, 12-bit Analog-to-Digital Converter (ADC). A full set of standard
programmable peripherals is provided that include a Serial Communications Interface (SCI), a Serial
Peripheral Interface (SPI), and two Quad Timers. Any of these interfaces can be used as General-Purpose
Input/Outputs (GPIO) if that function is not required. An on-chip relaxation oscillator provides flexibility
in the choice of either on-chip or externally supplied frequency reference for chip timing operations.
Application code is used to select which source is to be used.

1.3 State of the Art Development Environment

• Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.

• The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.

56F801 Technical Data, Rev. 15

6 Freescale Semiconductor

Product Documentation

1.4 Product Documentation

The four documents listed in Table 1-1 are required for a complete description and proper design with the
56F801. Documentation is available from local Freescale distributors, Freescale semiconductor sales
offices, Freescale Literature Distribution Centers, or online at www.freescale.com.

Table 1-1 56F801 Chip Documentation

Topic Description Order Number

56800E
Family Manual

DSP56F801/803/805/807
User’s Manual

56F801
Technical Data Sheet

56F801
Errata

Detailed description of the 56800 family architecture, and
16-bit core processor and the instruction set

Detailed description of memory, peripherals, and interfaces
of the 56F801, 56F803, 56F805, and 56F807

Electrical and timing specifications, pin descriptions, and
package descriptions (this document)

Details any chip issues that might be present 56F801E

56800EFM

DSP56F801-7UM

DSP56F801

1.5 Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is

active when low.

“asserted” A high true (active high) signal is high or a low true (active low) signal is low.

“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.

Examples: Signal/Symbol Logic State Signal State

Voltage

1

PIN True Asserted VIL/V

PIN False Deasserted VIH/V

PIN True Asserted VIH/V

PIN False Deasserted VIL/V

1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

56F801 Technical Data, Rev. 15

Freescale Semiconductor 7

OL

OH

OH

OL

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F801 are organized into functional groups, as shown in Table 2-1
and as illustrated in Figure 2-1. In Table 2-2 through Table 2-12, each table row describes the signal or
signals present on a pin.

Table 2-1 Functional Group Pin Allocations

Functional Group

Power (VDD or V

Ground (VSS or V

Supply Capacitors 2 Table 2-4

PLL and Clock 2 Table 2-5

Interrupt and Program Control 2 Table 2-6

Pulse Width Modulator (PWM) Port 7 Table 2-7

Serial Peripheral Interface (SPI) Port

Serial Communications Interface (SCI) Port

Analog-to-Digital Converter (ADC) Port 9 Table 2-10

Quad Timer Module Port 3 Table 2-11

JTAG/On-Chip Emulation (OnCE) 6 Table 2-12

1. Alternately, GPIO pins

) 5 Table 2-2

DDA

) 6 Table 2-3

SSA

1

1

Number of

Pins

4 Table 2-8

2 Table 2-9

Detailed

Description

56F801 Technical Data, Rev. 15

8 Freescale Semiconductor

Power Port

Ground Port

Power Port

Ground Port

Introduction

V

DD

V

SS

V

DDA

V

SSA

4

5*

1

1

Other

Supply

Port

PLL and Clock

or GPIO

VCAPC

EXTAL (GPIOB2)

XTAL (GPIOB3)

2

1

1

6

1

PWMA0-5

FAULTA0

56F801

1

SCLK (GPIOB4)

1

1

1

1

1

8

1

MOSI (GPIOB5)

MISO (GPIOB6)

SS

(GPIOB7)

TXD0 (GPIOB0)

RXD0 (GPIOB1)

ANA0-7

VREF

SPI Port
or GPIO

SCI0 Port
or GPIO

ADCA Port

Quad
Timer D
or GPIO

Interrupt/
Program
Control

JTAG/OnCE™

Port

TCK

TMS

TDI

TDO

TRST

DE

3

TD0-2 (GPIOA0-2)

1

1

1

1

1

1

1

IRQA

RESET

1

*includes TCS pin which is reserved for factory use and is tied to VSS

Figure 2-1 56F801 Signals Identified by Functional Group

1. Alternate pin functionality is shown in parenthesis.

1

56F801 Technical Data, Rev. 15

Freescale Semiconductor 9

2.2 Power and Ground Signals

Table 2-2 Power Inputs

No. of Pins Signal Name Signal Description

4 V

1 V

DD

DDA

Power—These pins provide power to the internal structures of the chip, and should all be

attached to V

Analog Power—This pin is a dedicated power pin for the analog portion of the chip and
should be connected to a low noise 3.3V supply.

DD.

Table 2-3 Grounds

No. of Pins Signal Name Signal Description

4 VSS GND—These pins provide grounding for the internal structures of the chip, and should all

be attached to V

1 V

1 TCS TCS—This Schmitt pin is reserved for factory use and must be tied to VSS for normal use.

SSA

Analog Ground—This pin supplies an analog ground.

In block diagrams, this pin is considered an additional V

SS.

SS.

Table 2-4 Supply Capacitors and VPP

No. of

Pins

2 VCAPC Supply Supply VCAPC—Connect each pin to a 2.2 µFor greater bypass capacitor in order

Signal

Name

Signal

Type

State

During Reset

Signal Description

to bypass the core logic voltage regulator (required for proper chip
operation). For more information, refer to

Section 5.2.

2.3 Clock and Phase Locked Loop Signals

Table 2-5 PLL and Clock

No. of

Pins

1 EXTAL

10 Freescale Semiconductor

Signal

Name

GPIOB2

Signal

Type

Input

Input/

Output

State

During Reset

Input

Input

Signal Description

External Crystal Oscillator Input—This input should be connected to an

8MHz external crystal or ceramic resonator. For more information, please
refer to

Port B GPIO—This multiplexed pin is a General Purpose I/O (GPIO) pin that
can be programmed as an input or output pin. This I/O can be utilized when
using the on-chip relaxation oscillator so the EXTAL pin is not needed.

56F801 Technical Data, Rev. 15

Section 3.5.

Table 2-5 PLL and Clock (Continued)

Interrupt and Program Control Signals

No. of

Pins

1 XTAL

Signal

Name

GPIOB3

Signal

Type

Output

Input/

Output

State

During Reset

Chip-

driven

Input

Signal Description

Crystal Oscillator Output—This output should be connected to an 8MHz

external crystal or ceramic resonator. For more information, please refer to

Section 3.5.

This pin can also be connected to an external clock source. For more
information, please refer to

Port B GPIO—This multiplexed pin is a General Purpose I/O (GPIO) pin that
can be programmed as an input or output pin. This I/O can be utilized when
using the on-chip relaxation oscillator so the XTAL pin is not needed.

Section 3.5.3.

2.4 Interrupt and Program Control Signals

Table 2-6 Interrupt and Program Control Signals

No. of

Pins

1 IRQA Input

1 RESET Input

Signal

Name

Signal

Type

(Schmitt)

(Schmitt)

State

During Reset

Input External Interrupt Request A—The IRQA input is a synchronized

external interrupt request that indicates that an external device is
requesting service. It can be programmed to be level-sensitive or
negative-edge- triggered.

Input Reset—This input is a direct hardware reset on the processor. When

RESET is asserted low, the controller is initialized and placed in the
Reset state. A Schmitt trigger input is used for noise immunity. When the
RESET pin is deasserted, the initial chip operating mode is latched from
the EXTBOOT pin. The internal reset signal will be deasserted
synchronous with the internal clocks, after a fixed number of internal
clocks.

Signal Description

To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.

2.5 Pulse Width Modulator (PWM) Signals

Table 2-7 Pulse Width Modulator (PWMA) Signals

No. of

Pins

6 PWMA0-5 Output Tri-stated PWMA0-5— These are six PWMA output pins.

1 FAULTA0 Input

Freescale Semiconductor 11

Signal

Name

Signal

Type

(Schmitt)

State During

Reset

Input FAULTA0— This fault input pin is used for disabling selected PWMA

outputs in cases where fault conditions originate off-chip.

56F801 Technical Data, Rev. 15

Signal Description

2.6 Serial Peripheral Interface (SPI) Signals

Table 2-8 Serial Peripheral Interface (SPI) Signals

No. of

Pins

1 MISO

1 MOSI

1 SCLK

Signal

Name

GPIOB6

GPIOB5

GPIOB4

Signal

Type

Input/Output

Input/Output

Input/Output

Input/Output

Input/Output

Input/Output

State During

Reset

Input

Input

Input

Input

Input

Input

Signal Description

SPI Master In/Slave Out (MISO)—This serial data pin is an input to

a master device and an output from a slave device. The MISO line of
a slave device is placed in the high-impedance state if the slave
device is not selected.

Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
be individually programmed as input or output pin.

After reset, the default state is MISO.

SPI Master Out/Slave In (MOSI)—This serial data pin is an output
from a master device and an input to a slave device. The master
device places data on the MOSI line a half-cycle before the clock
edge that the slave device uses to latch the data.

Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
be individually programmed as input or output pin.

After reset, the default state is MOSI.

SPI Serial Clock—In master mode, this pin serves as an output,
clocking slaved listeners. In slave mode, this pin serves as the data
clock input.

Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
be individually programmed as an input or output pin.

1 SS

GPIOB7

Input

Input/Output

After reset, the default state is SCLK.

Input

Input

56F801 Technical Data, Rev. 15

SPI Slave Select—In master mode, this pin is used to arbitrate

multiple masters. In slave mode, this pin is used to select the slave.

Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
be individually programmed as an input or output pin.

After reset, the default state is SS.

12 Freescale Semiconductor

Serial Communications Interface (SCI) Signals

2.7 Serial Communications Interface (SCI) Signals

Table 2-9 Serial Communications Interface (SCI0) Signals

No. of

Pins

1 TXD0

1 RXD0

Signal

Name

GPIOB0

GPIOB1

Signal

Type

Output

Input/Output

Input

Input/Output

State During

Reset

Input

Input

Input

Input

Signal Description

Transmit Data (TXD0)—SCI0 transmit data output

Port B GPIO—This pin is a General Purpose I/O (GPIO) pin that

can be individually programmed as an input or output pin.

After reset, the default state is SCI output.

Receive Data (RXD0)—SCI0 receive data input

Port B GPIO—This pin is a General Purpose I/O (GPIO) pin that

can be individually programmed as an input or output pin.

After reset, the default state is SCI input.

2.8 Analog-to-Digital Converter (ADC) Signals

Table 2-10 Analog to Digital Converter Signals

No. of

Pins

4 ANA0-3 Input Input ANA0-3—Analog inputs to ADC, channel 1

4 ANA4-7 Input Input ANA4-7—Analog inputs to ADC, channel 2

Signal

Name

Signal

Type

State During

Reset

Signal Description

1 VREF Input Input VREF—Analog reference voltage for ADC. Must be set to

-0.3V for optimal performance.

V

DDA

2.9 Quad Timer Module Signals

Table 2-11 Quad Timer Module Signals

No. of

Pins

3 TD0-2

Signal

Name

GPIOA0-2

Signal Type

Input/Output

Input/Output

State During

Reset

Input

Input

Signal Description

TD0-2—Timer D Channel 0-2

Port A GPIO—This pin is a General Purpose I/O (GPIO) pin that

can be individually programmed as an input or output pin.

After reset, the default state is the quad timer input.

56F801 Technical Data, Rev. 15

Freescale Semiconductor 13

2.10 JTAG/OnCE

Table 2-12 JTAG/On-Chip Emulation (OnCE) Signals

No. of

Pins

1 TCK Input

1 TMS Input

1 TDI Input

1 TDO Output Tri-stated Test Data Output—This tri-statable output pin provides a serial output data

1 TRST Input

1 DE Output Output Debug Event—DE provides a low pulse on recognized debug events.

Signal

Name

Signal

Type

(Schmitt)

(Schmitt)

(Schmitt)

(Schmitt)

State During

Reset

Input, pulled

low internally

Input, pulled

high internally

Input, pulled

high internally

Input, pulled

high internally

Signal Description

Test Clock Input—This input pin provides a gated clock to synchronize the

test logic and shift serial data to the JTAG/OnCE port. The pin is connected
internally to a pull-down resistor.

Test Mode Select Input—This input pin is used to sequence the JTAG
TAP controller’s state machine. It is sampled on the rising edge of TCK and
has an on-chip pull-up resistor.

Test Data Input—This input pin provides a serial input data stream to the
JTAG/OnCE port. It is sampled on the rising edge of TCK and has an
on-chip pull-up resistor.

stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR
controller states, and changes on the falling edge of TCK.

Test Reset—As an input, a low signal on this pin provides a reset signal to
the JTAG TAP controller. To ensure complete hardware reset,
be asserted whenever
debugging environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
but do not assert

RESET is asserted. The only exception occurs in a

TRST.

TRST should

RESET,

Part 3 Specifications

3.1 General Characteristics

The 56F801 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The
term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process technology,
to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V- compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.

Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.

The 56F801 DC and AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.

56F801 Technical Data, Rev. 15

14 Freescale Semiconductor

General Characteristics

CAUTION

This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.

Table 3-1 Absolute Maximum Ratings

Characteristic Symbol Min Max Unit

Supply voltage V

All other input voltages, excluding Analog inputs V

Voltage difference V

Voltage difference V

DD

SS

to V

to V

DDA

SSA

∆V

∆V

Analog inputs ANA0-7 and VREF V

Analog inputs EXTAL, XTAL V

DD

IN

DD

SS

IN

IN

VSS – 0.3 VSS + 4.0 V

VSS – 0.3 VSS + 5.5V V

- 0.3 0.3 V

- 0.3 0.3 V

V

V

SSA

SSA

– 0.3 V

– 0.3 V

+ 0.3 V

DDA

+ 3.0 V

SSA

Current drain per pin excluding VDD, VSS, & PWM ouputs I — 10 mA

Table 3-2 Recommended Operating Conditions

Characteristic Symbol Min Typ Max Unit

Supply voltage, digital V

Supply Voltage, analog V

Voltage difference V

Voltage difference V

ADC reference voltage

DD

SS

to V

to V

1

DDA

SSA

∆V

∆V

VREF 2.7 – 3.3V V

Ambient operating temperature T

1. VREF must be 0.3 below V

DDA

.

DD

DDA

DD

SS

A

3.0 3.3 3.6 V

3.0 3.3 3.6 V

-0.1 - 0.1 V

-0.1 - 0.1 V

–40 – 85 °C

56F801 Technical Data, Rev. 15

Freescale Semiconductor 15

Characteristic

Table 3-3 Thermal Characteristics

Comments

Symbol

6

Value

Unit Notes

48-pin LQFP

Junction to ambient
Natural convection

Junction to ambient (@1m/sec) R

Junction to ambient
Natural convection

Junction to ambient (@1m/sec) Four layer board (2s2p) R

Junction to case R

Junction to center of case Ψ

I/O pin power dissipation P

Power dissipation P

Junction to center of case P

Four layer board (2s2p) R

R

θJA

θJMA

θJMA

(2s2p)

θJMA

θJC

JT

I/O

D

DMAX

50.6 °C/W 2

47.4 °C/W 2

39.1 °C/W 1,2

37.9 °C/W 1,2

17.3 °C/W 3

1.2 °C/W 4, 5

User Determined W

P D = (IDD x VDD + P

(TJ - TA) /RθJA

I/O

) W

Notes:

1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.

2. Junction to ambient thermal resistance, Theta-JA (R
specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on

a thermal test board with two internal planes (2s2p where s is the number of signal layers and p is the number
of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the
non-single layer boards is Theta-JMA.

3. Junction to case thermal resistance, Theta-JC (R
using the cold plate technique with the cold plate temperature used as the "case" temperature. The basic cold

plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal
metric to use to calculate thermal performance when the package is being used with a heat sink.

4. Thermal Characterization Parameter, Psi-JT (Ψ

JT

thermocouple on top center of case as defined in JESD51-2. Ψ
temperature in steady state customer environments.

5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and
board thermal resistance.

6. See Section 5.1 from more details on thermal design considerations.

7. TJ = Junction Temperature
TA = Ambient Temperature

) was simulated to be equivalent to the JEDEC

θJA

), was simulated to be equivalent to the measured values

θJC

), is the "resistance" from junction to reference point

is a useful value to use to estimate junction

JT

W 7

56F801 Technical Data, Rev. 15

16 Freescale Semiconductor

3.2 DC Electrical Characteristics

Table 3-4 DC Electrical Characteristics

Operating Conditions: V

Characteristic Symbol Min Typ Max Unit

SS

= V

= 0 V, VDD = V

SSA

DC Electrical Characteristics

= 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF

DDA

Input high voltage (XTAL/EXTAL) V

Input low voltage (XTAL/EXTAL) V

Input high voltage [GPIOB(2:3)]

Input low voltage [GPIOB(2:3)]

Input high voltage (Schmitt trigger inputs)

Input low voltage (Schmitt trigger inputs)

1

1

2

2

Input high voltage (all other digital inputs) V

Input low voltage (all other digital inputs) V

Input current high (pullup/pulldown resistors disabled, VIN=VDD) I

Input current low (pullup/pulldown resistors disabled, VIN=VSS) I

Input current high (with pullup resistor, VIN=VDD) I

Input current low (with pullup resistor, VIN=VSS) I

Input current high (with pulldown resistor, VIN=VDD) I

Input current low (with pulldown resistor, VIN=VSS) I

IHC

ILC

V

IH[GPIOB(2:3)]

V

IL[GPIOB(2:3)]

V

IHS

V

ILS

IH

IL

IH

IL

IHPU

ILPU

IHPD

ILPD

Nominal pullup or pulldown resistor value RPU, R

Output tri-state current low I

Output tri-state current high I

Input current high (analog inputs, VIN=V

Input current low (analog inputs, VIN=V

DDA

SSA

3

)

3

)

Output High Voltage (at IOH) V

Output Low Voltage (at IOL) V

Output source current I

Output sink current I

PWM pin output source current

PWM pin output sink current

4

5

OZL

OZH

I

IHA

I

ILA

OH

I

OHP

I

OLP

OH

OL

OL

PD

2.25 — 2.75 V

0 — 0.5 V

2.0 — 3.6 V

-0.3 — 0.8 V

2.2 — 5.5 V

-0.3 — 0.8 V

2.0 — 5.5 V

-0.3 — 0.8 V

-1 — 1 µA

-1 — 1 µA

-1 — 1 µA

-210 — -50 µA

20 — 180 µA

-1 — 1 µA

30 KΩ

-10 — 10 µA

-10 — 10 µA

-15 — 15 µA

-15 — 15 µA

VDD – 0.7 — — V

— — 0.4 V

4 — — mA

4 — — mA

10 — — mA

16 — — mA

Input capacitance C

Output capacitance C

IN

OUT

— 8 — pF

— 12 — pF

56F801 Technical Data, Rev. 15

Freescale Semiconductor 17

Table 3-4 DC Electrical Characteristics (Continued)

Operating Conditions: V

Characteristic Symbol Min Typ Max Unit

SS

= V

= 0 V, VDD = V

SSA

= 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF

DDA

VDD supply current

Run7 (80MHz operation)

Run7 (60MHz operation)

8

Wait

I

DDT

6

— 120 130 mA

— 102 111 mA

— 96 102 mA

Stop — 62 70 mA

Low Voltage Interrupt, external power supply

Low Voltage Interrupt, internal power supply

= IDD + I

EIC

11

(Total supply current for VDD + V

DDA

= 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait IDD;

L

drops below V

DDA

DDA>VEIO

, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated

(between the minimum specified VDD and the point when the V

Power on Reset

1. Since the GPIOB[2:3] signals are shared with the XTAL/EXTAL function, these inputs are not 5.5 volt tolerant.

2. Schmitt Trigger inputs are: FAULTA0, IRQA, RESET, TCS, TCK, TMS, TDI, and TRST.

3. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.

4. PWM pin output source current measured with 50% duty cycle.

5. PWM pin output sink current measured with 50% duty cycle.

6. I

DDT

7. Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as
inputs; measured with all modules enabled.

8. Wait IDD measured using external square wave clock source (f
less than 50pF on all outputs. C
measured with PLL enabled.

9. This low voltage interrupt monitors the V
via separate traces. If V
conditions when V

10. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator
drops below V
unless the external power supply drops below the minimum specified value (3.0V).

11. Power–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping
up, this signal remains active for as long as the internal 2.5V is below 1.5V typical no matter how long the ramp up rate is. The
internally regulated voltage is typically 100 mV less than V

9

10

)

DDA

= 8MHz) into XTAL; all inputs 0.2V from rail; no DC loads;

osc

external power supply. V

DDA

, an interrupt is generated. Functionality of the device is guaranteed under transient

EIO

during ramp up until 2.5V is reached, at which time it self regulates.

DD

V

EIO

V

EIC

V

POR

is generally connected to the same potential as V

DDA

2.4 2.7 3.0 V

2.0 2.2 2.4 V

— 1.7 2.0 V

interrupt is generated).

EIO

DD

56F801 Technical Data, Rev. 15

18 Freescale Semiconductor

160

AC Electrical Characteristics

IDD Digital

IDD Analog

IDD Total

120

80

IDD (mA)

40

0

10 20

30

40

50

60 70

Freq. (MHz)

Figure 3-1 Maximum Run IDD vs. Frequency (see Note 7. in Table 3-15)

80

3.3 AC Electrical Characteristics

Timing waveforms in Section 3.3 are tested using the VIL and V
table. In Figure 3-2 the levels of VIH and VIL for an input signal are shown.

V

IH

Input Signal

Midpoint1

Fall Time

Note: The midpoint is VIL + (VIH – VIL)/2.

Low High

V

IL

Figure 3-2 Input Signal Measurement References

Figure 3-3 shows the definitions of the following signal states:

• Active state, when a bus or signal is driven, and enters a low impedance state.

• Tri-stated, when a bus or signal is placed in a high impedance state.

• Data Valid state, when a signal level has reached VOL or V

• Data Invalid state, when a signal level is in transition between VOL and V

levels specified in the DC Characteristics

IH

Rise Time

OH.

OH.

90%

50%

10%

56F801 Technical Data, Rev. 15

Freescale Semiconductor 19

Data1 Valid

Data2 Valid

Data3 Valid

Data1

Data2 Data3

Data Invalid State

Data Active Data Active

Figure 3-3 Signal States

3.4 Flash Memory Characteristics

Table 3-5 Flash Memory Truth Table

Mode

Standby L L L L L L L L

Read H H H H L L L L

Word Program H H L L H L L H

Page Erase H L L L L H L H

Mass Erase H L L L L H H H

1. X address enable, all rows are disabled when XE = 0

2. Y address enable, YMUX is disabled when YE = 0

3. Sense amplifier enable

4. Output enable, tri-state Flash data out bus when OE = 0

5. Defines program cycle

6. Defines erase cycle

7. Defines mass erase cycle, erase whole block

8. Defines non-volatile store cycle

XE

1

YE

2

SE

3

OE

4

Data

Tri-stated

PROG

5

ERASE

6

MAS1

7

NVSTR

8

Table 3-6 IFREN Truth Table

Mode IFREN = 1 IFREN = 0

Read Read information block Read main memory block

Word program Program information block Program main memory block

Page erase Erase information block Erase main memory block

Mass erase Erase both block Erase main memory block

56F801 Technical Data, Rev. 15

20 Freescale Semiconductor

Flash Memory Characteristics

Table 3-7 Flash Timing Parameters

Operating Conditions: V

Characteristic Symbol Min Typ Max Unit Figure

SS

= V

= 0 V, VDD = V

SSA

= 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF

DDA

Program time

Erase time

Mass erase time

Endurance

Data Retention

PROG/ERASE to NVSTR set
up time

NVSTR hold time

NVSTR hold time (mass erase)

NVSTR to program set up time

Recovery time

Cumulative program

HV period

1

1

The following parameters should only be used in the Manual Word Programming Mode

2

Tprog*

Terase*

Tme*

E

CYC

D

RET

Tnvs*

Tnvh*

Tnvh1*

Tpgs*

Trcv*

Thv

20 – – us Figure 3-4

20 – – ms Figure 3-5

100 – – ms Figure 3-6

10,000 20,000 – cycles

10 30 – years

– 5 – us Figure 3-4,

Figure 3-5,

Figure 3-6

– 5 – us Figure 3-4,

Figure 3-5

– 100 – us Figure 3-6

– 10 – us Figure 3-4

– 1 – us Figure 3-4,

Figure 3-5,

Figure 3-6

– 3 – ms Figure 3-4

Program hold time

Address/data set up time

Address/data hold time

1. One cycle is equal to an erase program and read.

2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be
programmed twice before next erase.

3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.

*The Flash interface unit provides registers for the control of these parameters.

Freescale Semiconductor 21

3

3

3

Tpgh

Tads

Tadh

56F801 Technical Data, Rev. 15

– – – Figure 3-4

– – – Figure 3-4

– – – Figure 3-4

IFREN

XADR

XE

YADR

YE

DIN

PROG

NVSTR

IFREN

XADR

Tnvs

Tadh

Tads

Tprog

Tpgs

Thv

Figure 3-4 Flash Program Cycle

Tpgh

Tnvh

Trcv

XE

YE=SE=OE=MAS1 =0

ERASE

NVSTR

Tnvs

Ter a s e

Tnvh

Trcv

Figure 3-5 Flash Erase Cycle

56F801 Technical Data, Rev. 15

22 Freescale Semiconductor

X

N

IFREN

ADR

XE

MAS1

YE=SE=OE=0

External Clock Operation

ERASE

VSTR

Tnvs

Tme

Tnvh 1

Trc v

Figure 3-6 Flash Mass Erase Cycle

3.5 External Clock Operation

The 56F801 device clock is derived from either 1) an internal crystal oscillator circuit working in
conjunction with an external crystal, 2) an external frequency source, or 3) an on-chip relaxation oscillator.
To generate a reference frequency using the internal crystal oscillator circuit, a reference crystal external
to the chip must be connected between the EXTAL and XTAL pins. Paragrahs
these methods of clocking. Whichever type of clock derivation is used provides a reference signal to a
phase-locked loop (PLL) within the 56F801. In turn, the PLL generates a master reference frequency that
determines the speed at which chip operations occur.

Application code can be set to change the frequency source between the relaxation oscillator and crystal
oscillator or external source, and power down the relaxation oscillator if desired. Selection of which clock
is used is determined by setting the PRECS bit in the PLLCR (phase-locked loop control register) word
(bit 2). If the bit is set to 1, the external crystal oscillator circuit is selected. If the bit is set to 0, the internal
relaxation oscillator is selected, and this is the default value of the bit when power is first applied.

3.5.1 and 3.5.4 describe

3.5.1 Crystal Oscillator

The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in

Table 3-10. Figure 3-7 shows a recommended crystal

oscillator circuit. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal
parameters determine the component values required to provide maximum stability and reliable start-up.
The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL
pins to minimize output distortion and start-up stabilization time. The internal 56F80x oscillator circuitry

56F801 Technical Data, Rev. 15

Freescale Semiconductor 23

is designed to have no external load capacitors present. As shown in Figure 3-8 no external load capacitors
should be used.

The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a
capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and
process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF
as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as
determined by the following equation:

CL =

CL1 * CL2

CL1 + CL2

+ Cs =

12 * 12

+ 3 = 6 + 3 = 9pF

12 + 12

This is the value load capacitance that should be used when selecting a crystal and determining the actual
frequency of operation of the crystal oscillator circuit.

EXTAL XTAL

R

z

f

c

Recommended External Crystal
Parameters:

= 1 to 3 MΩ

R

z

f

= 8MHz (optimized for 8MHz)

c

Figure 3-7 External Crystal Oscillator Circuit

3.5.2 Ceramic Resonator

It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system
design can tolerate the reduced signal integrity. In
shown. Refer to supplier’s recommendations when selecting a ceramic resonator and associated
components. The resonator and components should be mounted as close as possible to the EXTAL and
XTAL pins. The internal 56F80x oscillator circuitry is designed to have no external load capacitors
present. As shown in

Figure 3-7 no external load capacitors should be used.

Figure 3-8, a typical ceramic resonator circuit is

EXTAL XTAL

R

z

f

c

Recommended Ceramic Resonator
Parameters:
R

= 1 to 3 MΩ

z

= 8MHz (optimized for 8MHz)

f

c

Figure 3-8 Connecting a Ceramic Resonator

Note: Freescale recommends only two terminal ceramic resonators vs. three terminal resonators
(which contain an internal bypass capacitor to ground).

56F801 Technical Data, Rev. 15

24 Freescale Semiconductor

External Clock Operation

3.5.3 External Clock Source

The recommended method of connecting an external clock is given in Figure 3-9. The external clock
source is connected to XTAL and the EXTAL pin is grounded.

56F801

XTAL

EXTAL

External Clock

V

SS

Figure 3-9 Connecting an External Clock Signal

Table 3-8 External Clock Operation Timing Requirements

Operating Conditions: V

Characteristic Symbol Min Typ Max Unit

Frequency of operation (external clock driver)

Clock Pulse Width

1. See Figure 3-9 for details on using the recommended connection of an external clock driver.

2. May not exceed 60MHz for the DSP56F801FA60 device.

3. The high or low pulse width must be no smaller than 6.25ns or the chip will not function.

4. Parameters listed are guaranteed by design.

External

Clock

3, 4

50%

10%

90%

t

PW

= V

SS

= 0 V, VDD = V

SSA

1

t

PW

f

t

osc

PW

= 3.0–3.6 V, TA = –40° to +85°C

DDA

0 —

6.25 — — ns

80

3

2

90%

50%

10%

MHz

V

IH

V

IL

Note: The midpoint is VIL + (VIH – VIL)/2.

Figure 3-10 External Clock Timing

3.5.4 Use of On-Chip Relaxation Oscillator

An internal relaxation oscillator can supply the reference frequency when an external frequency source or
crystal are not used. During a 56F801 boot or reset sequence, the relaxation oscillator is enabled by default,
and the PRECS bit in the PLLCR word is set to 0 (
relaxation oscillator can be deselected instead by setting the PRECS bit in the PLLCR to 1. When this
occurs, the PRECSS bit in the PLLSR (prescaler clock select status register) data word also sets to 1. If a
changeover between internal and external oscillators is required at startup, internal device circuits

56F801 Technical Data, Rev. 15

Freescale Semiconductor 25

Section 3.5). If an external oscillator is connected, the

compensate for any asynchronous transitions between the two clock signals so that no glitches occur in the
resulting master clock to the chip. When changing clocks, the user must ensure that the clock source is not
switched until the desired clock is enabled and stable.

To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator
can be incrementally adjusted to within ±0.25% of 8MHz by trimming an internal capacitor. Bits 0-7 of
the IOSCTL (internal oscillator control) word allow the user to set in an additional offset (trim) to this
preset value to increase or decrease capacitance. The default value of this trim is 128 units, making the
power-up default capacitor size 432 units. Each unit added or deleted changes the output frequency by
about 0.2%, allowing incremental adjustment until the desired frequency accuracy is achieved.

Table 3-9 Relaxation Oscillator Characteristics

Operating Conditions: V

Characteristic Symbol Min Typ Max Unit

Frequency Accuracy

Frequency Drift over Temp ∆f/∆t — +0.1 —

Frequency Drift over Supply ∆f/∆V — 0.1 — %/V

Trim Accuracy ∆f

1. Over full temperature range.

1

= V

SS

= 0 V, VDD = V

SSA

∆f — +2 +5 %

T

= 3.0–3.6 V, TA = –40° to +85°C

DDA

— +0.25 — %

%/oC

56F801 Technical Data, Rev. 15

26 Freescale Semiconductor

Output Frequency

External Clock Operation

8.2

8.1

8.0

7.9

7.8

7.7

7.6

Temperature (

o

C)

7555-40 35-25 15-5 85

Figure 3-11 Typical Relaxation Oscillator Frequency vs. Temperature

(Trimmed to 8MHz @ 25

11

10

9

8

7

6

o

C)

5

0 102030405060708090A0B0C0D0E0F0

Figure 3-12 Typical Relaxation Oscillator Frequency vs. Trim Value @ 25oC

56F801 Technical Data, Rev. 15

Freescale Semiconductor 27

3.5.5 Phase Locked Loop Timing

Table 3-10 PLL Timing

Operating Conditions: V

Characteristic Symbol Min Typ Max Unit

= V

SS

SSA

= 0 V, VDD = V

= 3.0–3.6 V, TA = –40° to +85°C

DDA

External reference crystal frequency for the PLL

1

PLL output frequency2

PLL stabilization time4 0o to +85oC

PLL stabilization time4 -40o to 0oC

1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.

2. ZCLK may not exceed 80MHz. For additional information on ZCLK and f
User Manual. ZCLK = f

3. Will not exceed 60MHz for the DSP56F801FA60 device.

4. This is the minimum time required after the PLL setup is changed to ensure reliable operation.

op

f

osc

f

/2 40 —

out

t

plls

t

plls

4 8 10 MHz

— 10 — ms

— 100 200 ms

/2, please refer to the OCCS chapter in the

out

80

3

MHz

56F801 Technical Data, Rev. 15

28 Freescale Semiconductor

Reset, Stop, Wait, Mode Select, and Interrupt Timing

3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Operating Conditions: V

Characteristic Symbol Min Max Unit See

RESET Assertion to Address, Data and Control
Signals High Impedance

Minimum RESET Assertion Duration
OMR Bit 6 = 0
OMR Bit 6 = 1

RESET De-assertion to First External Address
Output

Edge-sensitive Interrupt Request Width t

IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the interrupt service routine

IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine

IRQA Low to First Valid Interrupt Vector Address

Out recovery from Wait State

IRQA Width Assertion to Recover from Stop State

3

= V

SS

2

= 0 V, VDD = V

SSA

4

t

RAZ

t

RA

t

RDA

IRW

t

IDM

t

t

IRI

t

IW

1, 5

= 3.0–3.6 V, TA = –40° to +85°C, C

DDA

≤ 50pF

L

— 21 ns Figure 3-13

Figure 3-13

275,000T

128T

—
—

ns
ns

33T 34T ns Figure 3-13

1.5T — ns Figure 3-14

15T — ns Figure 3-15

IG

16T — ns Figure 3-15

13T — ns Figure 3-16

2T — ns Figure 3-17

Delay from IRQA Assertion to Fetch of first

t

IF

Figure 3-17

instruction (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1

Duration for Level Sensitive IRQA Assertion to
Cause the Fetch of First

IRQA Interrupt Instruction

t

IRQ

—
—

275,000T

12T

ns
ns

Figure 3-18

(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1

Delay from Level Sensitive IRQA Assertion to First

t

II

—
—

275,000T

12T

ns
ns

Figure 3-18

Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1

1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.

2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:

• After power-on reset

• When recovering from Stop state

3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not

the minimum required so that the IRQA interrupt is accepted.

4. The interrupt instruction fetch is visible on the pins only in Mode 3.

5. Parameters listed are guaranteed by design.

—
—

275,000T

12T

ns
ns

56F801 Technical Data, Rev. 15

Freescale Semiconductor 29

RESET

t

RAZ

t

RA

t

RDA

A0–A15,

D0–D15

, DS,

PS

RD

, WR

IRQA,
IRQB

A0–A15,

PS, DS,
RD, WR

IRQA,

IRQB

First Fetch

First Fetch

Figure 3-13 Asynchronous Reset Timing

t

IRW

Figure 3-14 External Interrupt Timing (Negative-Edge-Sensitive)

First Interrupt Instruction Execution

t

IDM

a) First Interrupt Instruction Execution

General

Purpose

I/O Pin

t

IG

IRQA,

IRQB

b) General Purpose I/O

Figure 3-15 External Level-Sensitive Interrupt Timing

56F801 Technical Data, Rev. 15

30 Freescale Semiconductor

IRQA,

IRQB

Reset, Stop, Wait, Mode Select, and Interrupt Timing

t

IRI

A0–A15,

PS

, DS,

RD

, WR

First Interrupt Vector
Instruction Fetch

Figure 3-16 Interrupt from Wait State Timing

t

IW

IRQA

t

IF

A0–A15,

PS

, DS,

RD

, WR

First Instruction Fetch

Not IRQA Interrupt Vector

Figure 3-17 Recovery from Stop State Using Asynchronous Interrupt Timing

t

IRQ

IRQA

t

II

A0–A15
PS

, DS,

RD

, WR

First IRQA Interrupt

Instruction Fetch

Figure 3-18 Recovery from Stop State Using IRQA Interrupt Service

56F801 Technical Data, Rev. 15

Freescale Semiconductor 31

3.7 Serial Peripheral Interface (SPI) Timing

Operating Conditions: V

Characteristic Symbol Min Max Unit See Figure

Cycle time
Master
Slave

Enable lead time
Master
Slave

Enable lag time
Master
Slave

Clock (SCK) high time
Master
Slave

Clock (SCK) low time
Master
Slave

Data setup time required for inputs
Master
Slave

Table 3-12 SPI Timing

SS

= V

= 0 V, VDD = V

SSA

t

ELD

t

ELG

t

t

t

t

CH

CL

DS

DDA

C

1

= 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF

Figures 3-19, 3-20,
50
25

—
—

ns
ns

3-21, 3-22

Figure 3-22
—
25

—
—

ns
ns

Figure 3-22
—

100

—
—

ns
ns

Figures 3-19, 3-20,

17.6

12.5

—
—

ns
ns

3-21, 3-22

Figures 3-19, 3-20,

24.1
25

—
—

ns
ns

3-21, 3-22

Figures 3-19, 3-20,

20

0

—
—

ns
ns

3-21, 3-22

Data hold time required for inputs
Master
Slave

Access time (time to data active from
high-impedance state)
Slave

Disable time (hold time to high-impedance state)
Slave

Data Valid for outputs
Master
Slave (after enable edge)

Data invalid
Master
Slave

Rise time
Master
Slave

Fall time
Master
Slave

1. Parameters listed are guaranteed by design.

t

t

t

DH

t

t

DV

DI

t

t

Figures 3-19, 3-20,
0
2

A

—
—

ns
ns

3-21, 3-22

Figure 3-22

4.8 15 ns

D

Figure 3-22

3.7 15.2 ns

Figures 3-19, 3-20,

—
—

4.5

20.4

ns
ns

3-21, 3-22

Figures 3-19, 3-20,
0
0

R

—
—

F

—
—

—
—

11.5

10.0

9.7

9.0

ns
ns

ns
ns

ns
ns

3-21, 3-22

Figures 3-19, 3-20,

3-21, 3-22

Figures 3-19, 3-20,

3-21, 3-22

56F801 Technical Data, Rev. 15

32 Freescale Semiconductor

Serial Peripheral Interface (SPI) Timing

SS

(Input)

SCLK (CPOL = 0)

(Output)

SCLK (CPOL = 1)

(Output)

MISO

(Input)

MOSI

(Output)

SS is held High on master

t

DS

t

C

t

CL

t

CH

t

CL

t

DH

t

CH

t

R

t

F

MSB in Bits 14–1 LSB in

t

DI

t

DV

Master MSB out Bits 14–1 Master LSB out

t

F

Figure 3-19 SPI Master Timing (CPHA = 0)

t

F

t

R

t

(ref)

DI

t

R

SS

(Input)

SCLK (CPOL = 0)

(Output)

SCLK (CPOL = 1)

(Output)

MISO

(Input)

MOSI

(Output)

SS is held High on master

t

t

C

t

CL

t

CH

t

CL

t

CH

t

R

F

MSB in Bits 14–1 LSB in

t

t

(ref)

DV

DI

t

Master MSB out Bits 14– 1 Master LSB out

t

F

Figure 3-20 SPI Master Timing (CPHA = 1)

DV

t

R

t

F

t

DS

t

DH

t

R

56F801 Technical Data, Rev. 15

Freescale Semiconductor 33

SS

(Input)

SCLK (CPOL = 0)

(Input)

t

ELD

t

t

CH

CL

t

C

t

CL

t

F

t

R

t

ELG

SCLK (CPOL = 1)

(Input)

MISO

(Output)

MOSI

(Input)

SS

(Input)

SCLK (CPOL = 0)

(Input)

t

A

t

CH

t

R

Slave MSB out Bits 14–1

t

DS

t

DV

t

DH

MSB in Bits 14–1 LSB in

Figure 3-21 SPI Slave Timing (CPHA = 0)

t

C

t

t

ELD

CL

t

CH

t

CL

t

R

t

F

Slave LSB out

t

DI

t

F

t

ELG

t

D

t

DI

SCLK (CPOL = 1)

(Input)

MISO

(Output)

MOSI

(Input)

t

DV

t

CH

t

A

t

F

Slave MSB out Bits 14–1

t

t

DS

t

DV

DH

t

R

Slave LSB out

t

DI

t

D

MSB in Bits 14–1 LSB in

Figure 3-22 SPI Slave Timing (CPHA = 1)

56F801 Technical Data, Rev. 15

34 Freescale Semiconductor

3.8 Quad Timer Timing

Quad Timer Timing

Operating Conditions: V

Characteristic Symbol Min Max Unit

Timer input period P

Timer input high/low period P

Timer output period P

Timer output high/low period P

1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.

2. Parameters listed are guaranteed by design.

Timer Inputs

P

IN

Timer Outputs

P

OUT

Table 3-13 Timer Timing

SS

= V

= 0 V, VDD = V

SSA

IN

INHL

OUT

OUTHL

= 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF

DDA

4T+6 — ns

2T+3 — ns

2T — ns

1T — ns

P

INHL

P

OUTHL

1, 2

P

P

OUTHL

INHL

Figure 3-23 Timer Timing

3.9 Serial Communication Interface (SCI) Timing

Table 3-14 SCI Timing

Operating Conditions: V

Characteristic Symbol Min Max Unit

Baud Rate

RXD2 Pulse Width

TXD3 Pulse Width

1. f

2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.

3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.

4. Parameters listed are guaranteed by design.

1

is the frequency of operation of the system clock in MHz.

MAX

SS

= V

= 0 V, VDD = V

SSA

BR

RXD

TXD

DDA

PW

PW

4

= 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF

—

(f

MAX

0.965/BR 1.04/BR ns

0.965/BR 1.04/BR ns

*2.5)/(80) Mbps

56F801 Technical Data, Rev. 15

Freescale Semiconductor 35

RXD

SCI receive

data pin

(Input)

RXD

PW

Figure 3-24 RXD Pulse Width

TXD

SCI receive

data pin

(Input)

TXD

PW

Figure 3-25 TXD Pulse Width

3.10 Analog-to-Digital Converter (ADC) Characteristics

Table 3-15 ADC Characteristics

Characteristic Symbol Min Typ Max Unit

ADC input voltages V

Resolution R

Integral Non-Linearity

3

ADCIN

ES

INL — +/- 4 +/- 5

1

0

—

V

REF

12 — 12 Bits

Differential Non-Linearity DNL — +/- 0.9 +/- 1

Monotonicity GUARANTEED

ADC internal clock

5

Conversion range R

Conversion time t

Sample time t

Input capacitance C

Gain Error (transfer gain)

Offset Voltage

5

5

f

ADIC

ADC

ADS

ADI

E

GAIN

V

OFFSET

AD

0.5 — 5 MHz

V

SSA

— V

DDA

— 6 —

— 1 —

— 5 —

1.00 1.10 1.15 —

+10 +230 +325 mV

2

V

LSB

LSB

4

4

V

cycles

cycles

6

pF

6

6

t

AIC

t

AIC

56F801 Technical Data, Rev. 15

36 Freescale Semiconductor

Analog-to-Digital Converter (ADC) Characteristics

Table 3-15 ADC Characteristics (Continued)

Characteristic Symbol Min Typ Max Unit

Total Harmonic Distortion

5

Signal-to-Noise plus Distortion

Effective Number of Bits

5

Spurious Free Dynamic Range

5

5

THD 55 60 — dB

SINAD 54 56 — dB

ENOB 8.5 9.5 — bit

SFDR 60 65 — dB

Bandwidth BW — 100 — KHz

ADC Quiescent Current (both ADCs) I

V

Quiescent Current (both ADCs) I

REF

1. For optimum ADC performance, keep the minimum V
a digital output code of 0 or cause erroneous conversions.

2. V

3. Measured in 10-90% range.

4. LSB = Least Significant Bit.

5. Guaranteed by characterization.

6. t

must be equal to or less than V

REF

= 1/f

AIC

ADIC

DDA

ADC

VREF

- 0.3V and must be greater than 2.7V.

ADC analog input

ADCIN

— 50 — mA

— 12 16.5 mA

value > 250mV. Inputs less than 250mV volts may convert to

3

1

1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)

2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)

3. Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)

4. Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only connected to it
at sampling time. (1pf)

2

4

Figure 3-26 Equivalent Analog Input Circuit

56F801 Technical Data, Rev. 15

Freescale Semiconductor 37

3.11 JTAG Timing

1, 3

= 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF

Operating Conditions: V

Table 3-16 JTAG Timing

SS

= V

= 0 V, VDD = V

SSA

DDA

Characteristic Symbol Min Max Unit

TCK frequency of operation

2

TCK cycle time t

TCK clock pulse width t

TMS, TDI data setup time t

TMS, TDI data hold time t

TCK low to TDO data valid t

TCK low to TDO tri-state t

TRST assertion time t

DE assertion time t

1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
operation, T = 12.5ns.

2. TCK frequency of operation must be less than 1/8 the processor rate.

3. Parameters listed are guaranteed by design.

f

OP

CY

PW

DS

DH

DV

TS

TRST

DE

DC 10 MHz

100 — ns

50 — ns

0.4 — ns

1.2 — ns

— 26.6 ns

— 23.5 ns

50 — ns

8T — ns

TCK

(Input)

VM = V

+ (VIH – VIL)/2

IL

Figure 3-27 Test Clock Input Timing Diagram

t

CY

t

PW

V

IH

V

M

V

IL

tPW

V

M

56F801 Technical Data, Rev. 15

38 Freescale Semiconductor

TCK

(Input)

JTAG Timing

t

DS

t

DH

TDI

TMS

(Input)

TDO

(Output)

TDO

(Output

TDO

(Output)

TRST

(Input)

Input Data Valid

t

DV

Output Data Valid

t

TS

)

t

DV

Output Data Valid

Figure 3-28 Test Access Port Timing Diagram

t

TRST

DE

Figure 3-29 TRST Timing Diagram

t

DE

Figure 3-30 OnCE—Debug Event

56F801 Technical Data, Rev. 15

Freescale Semiconductor 39

Part 4 Packaging

4.1 Package and Pin-Out Information 56F801

This section contains package and pin-out information for the 48-pin LQFP configuration of the 56F801.

PWMA5

PWMA4

PWMA3

PWMA2

PWMA1

VSSVDD

VCAPC1

PWMA0

ANA7

ANA6

ANA5

TDO

TD1

TD2

/SS

MISO

MOSI

SCLK

TXDO

V

SS

VDD

RXD0

DE

PIN 1

TCS

ORIENTATION

PIN 13

TCK

TMS

IREQA

MARK

TDI

SS

V

VCAPC2

PIN 37

PIN 25

VDD

EXTAL

XTAL

TDO

TRST

ANA4

ANA3

VREF

ANA2

ANA1

ANA0

FAULTA0

V

SS

VDD

VSSA

VDDA

RESET

Figure 4-1 Top View, 56F801 48-pin LQFP Package

56F801 Technical Data, Rev. 15

40 Freescale Semiconductor

Package and Pin-Out Information 56F801

Table 4-1 56F801 Pin Identification by Pin Number

Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name

1 TD0 13 TCS 25 RESET 37 ANA5

2 TD1 14 TCK 26 V

3 TD2 15 TMS 27 V

4 SS 16 IREQA 28 V

5 MISO 17 TDI 29 V

DDA

SSA

DD

SS

6 MOSI 18 VCAPC2 30 FAULTA0 42 V

7 SCLK 19 V

8 TXD0 20 V

9 V

10 V

SS

DD

21 EXTAL 33 ANA2 45 PWMA2

22 XTAL 34 VREF 46 PWMA3

SS

DD

31 ANA0 43 V

32 ANA1 44 PWMA1

38 ANA6

39 ANA7

40 PWMA0

41 VCAPC1

DD

SS

11 RXD0 23 TDO 35 ANA3 47 PWMA4

12 DE 24 TRST 36 ANA4 48 PWMA5

56F801 Technical Data, Rev. 15

Freescale Semiconductor 41

NOTES:

4X

0.200 AB T-U

9

A1

48

1

T

B

B1

12

13

Z

A

37

36

DETAIL Y

P

U

V

AE AE

V1

25

24

Z

S1

S

4X

DETAIL Y

Z0.200 AC T-U

AB

AC

G

AD

BASE METAL

0.080 AC

°

M

TOP & BOTTOM

1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE AB IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING
LINE.

4. DATUMS T, U, AND Z TO BE DETERMINED AT
DATUM PLANE AB.

5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE AC.

6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH AND
ARE DETERMINED AT DATUM PLANE AB.

7. DIMENSION D DOES NOT INC LUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION
SHALL NOT CAUSE THE D DIMENSION TO
EXCEED 0.350.

8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076.

9. EXACT SHAPE OF EACH CORNER IS
OPTIONAL.

MILLIMETERS

MIN

T, U , Z

DIM

A1

B1

S1

V1

AA

A

B

C
D
E

F
G
H

J
K
L
M
N

P
R

S

V

W

MAX

7.000 BSC

3.500 BSC

7.000 BSC

3.500 BSC

1.400 1.600

0.170 0.270

1.350 1.450

0.170 0.230

0.500 BSC

0.050 0.150

0.090 0.200

0.500 0.700
0 7

°°

12 REF

°

0.090 0.160

0.250 BSC

0.150 0.250

9.000 BSC

4.500 BSC

9.000 BSC

4.500 BSC

0.200 REF

1.000 REF

R

N

J

0.250

E

C

GAUGE PLANE

F
D

M

0.080 ZAC

SECTION AE-AE

T-U

CASE 932-03

ISSUE F

H

DETAIL AD

W

°

L

K

AA

Figure 4-2 48-pin LQFP Mechanical Information

Please see www.freescale.com for the most current case outline.

56F801 Technical Data, Rev. 15

42 Freescale Semiconductor

Thermal Design Considerations

Part 5 Design Considerations

5.1 Thermal Design Considerations

An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:

Equation 1:T

JTAPDRθJA

×()+=

Where:

TA = ambient temperature °C
R

= package junction-to-ambient thermal resistance °C/W

θJA

PD = power dissipation in package

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:

Equation 2:R

θJARθJCRθCA

+=

Where:

R

= package junction-to-ambient thermal resistance °C/W

θJA

R

= package junction-to-case thermal resistance °C/W

θJC

R

= package case-to-ambient thermal resistance °C/W

θCA

R

is device-related and cannot be influenced by the user. The user controls the thermal environment to

θJC

change the case-to-ambient thermal resistance, R

. For example, the user can change the air flow around

θCA

the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where
the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the
device thermal performance may need the additional modeling capability of a system level thermal
simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which
the package is mounted. Again, if the estimations obtained from R

do not satisfactorily answer whether

θJA

the thermal performance is adequate, a system level model may be appropriate.

Definitions:

A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:

• Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the
chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation
across the surface.

56F801 Technical Data, Rev. 15

Freescale Semiconductor 43

• Measure the thermal resistance from the junction to where the leads are attached to the case. This definition
is approximately equal to a junction to board thermal resistance.

• Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case
determined by a thermocouple.

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.

5.2 Electrical Design Considerations

CAUTION

This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.

Use the following list of considerations to assure correct operation:

• Provide a low-impedance path from the board power supply to each VDD pin on the controller, and from the
board ground to each V

• The minimum bypass requirement is to place 0.1 µF capacitors positioned as close as possible to the
package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of
the ten V

performance tolerances.

• Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and V
pins are less than 0.5 inch per capacitor lead.

DD/VSS

pairs, including V

(GND) pin.

SS

DDA/VSSA.

Ceramic and tantalum capacitors tend to provide better

SS

(GND)

56F801 Technical Data, Rev. 15

44 Freescale Semiconductor

Electrical Design Considerations

• Bypass the VDD and V

layers of the PCB with approximately 100 µF, preferably with a high-grade

SS

capacitor such as a tantalum capacitor.

• Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal.

• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the V

• Take special care to minimize noise levels on the VREF, V

and GND circuits.

DD

DDA

and V

SSA

pins.

• Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or
debugging systems) should allow a means to assert
to assert

TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs

that do not require debugging functionality, such as consumer products,

TRST whenever RESET is asserted, as well as a means

TRST should be tied low.

• Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an
interface to this port to allow in-circuit Flash programming.

56F801 Technical Data, Rev. 15

Freescale Semiconductor 45

Part 6 Ordering Information

Table 6-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor

sales office or authorized distributor to determine availability and to order parts.

Table 6-1 56F801 Ordering Information

Part

56F801 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) 48 80 DSP56F801FA80

56F801 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) 48 60 DSP56F801FA60

56F801 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) 48 80 DSP56F801FA80E*

56F801 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) 48 60 DSP56F801FA60E*

Supply

Voltage

Package Type

Pin

Count

Ambient

Frequency

(MHz)

Order Number

*This package is RoHS compliant.

56F801 Technical Data, Rev. 15

46 Freescale Semiconductor

Electrical Design Considerations

56F801 Technical Data, Rev. 15

Freescale Semiconductor 47

How to Reach Us:

Home Page:

www.freescale.com

E-mail:

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[phone] (English)
[phone] (German)
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[e-mail]

Japan:

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For Literature Requests Only:

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1-800-441-2447 or 303-675-2140
Fax: [phone]
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RoHS-compliant and/or Pb-free versions of Freescale products have the
functionality and electrical characteristics of their non-RoHS-compliant
and/or non-Pb-free counterparts. For further information, see
http://www.freescale.com or contact your Freescale sales representative.

For information on Freescale’s Environmental Products program, go to
http://www.freescale.com/epp.

Information in this document is provided solely to enable system and
software implementers to use Freescale Semiconductor products. There are
no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
information in this document.

Freescale Semiconductor reserves the right to make changes without further
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particular purpose, nor does Freescale Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically
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incidental damages. “Typical” parameters that may be provided in Freescale
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parameters, including “Typicals”, must be validated for each customer
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Freescale Semiconductor products are not designed, intended, or authorized
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Inc. All other product or service names are the property of their respective owners.
This product incorporates SuperFlash® technology licensed from SST.

© Freescale Semiconductor, Inc. 2005. All rights reserved.

DSP56F801
Rev. 15
10/2005