Datasheet 32C408BRPFS30, 32C408BRPFS25, 32C408BRPFS20, 32C408BRPFS12, 32C408BRPFI30 Datasheet (MAXWELL)

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4 Megabit (512K x 8-Bit) SRAM

32C408B

©2002 Maxwell Technologies

All rights reserved.

05.02.02 Rev 7

FEATURES:

• 512k x 8-bit CMOS architecture

•R

AD-PAK® technology hardened against natural space radi-

ation

• Total dose hardness:

- > 100 krad (Si), depending upon space mission

• Single event effect:

- SEL

TH

: > 68 MeV/mg/cm

2

- SEUTH: < 3MeV/mg/cm

2

- SEU saturated cross section: 6E-9 cm2/bit

• Package:

-36 pin R

AD-PAK® flat pack

• Fast propagation time:

-20, 25, 30 ns maximum access time

• Single 5V +

10% power supply

• Low power dissipation:

- Standby: 60mA (TTL); 10mA (CMOS)

- Operating: 180 mA (20 ns); 170 mA (25 ns); 160 mA (30
ns)

• TTL compatible inputs and outputs

• Fully static operation

- No clock or refresh required

• Three state outputs

DESCRIPTION:

Maxwell Technologies’ 32C408B high-speed 4 Megabit SRAM
microcircuit features a greater than 100 krad (Si) total dose
tolerance, depending upon space mission. Using R

AD-PAK®

packaging technology, the 32C408B realizes higher density,
higher performance and lower power consumption, and is well
suited for high-speed system application. Its fully static design
eliminates the need for external clocks, while the CMOS cir­cuitry reduces power consumption and provides higher reli­ability. The 32C408B is equipped with eight common input/
output lines, chip select and output enable, allowing for
greater system flexibility and eliminating bus contention.

Maxwell Technologies' patented R

AD-PAK packaging technol-

ogy incorporates radiation shielding in the microcircuit pack­age. In a GEO orbit, R

AD-PAK can provides true greater than

100 krad (Si) total radiation dose tolerance; dependent upon
space mission. The patented radiation-hardened R

AD-PAK

technology incorporates radiation shielding in the microcircuit
package. It eliminates the need for box shielding while provid­ing the required radiation shielding for a lifetime in orbit or a
space mission. This product is available with packaging and
screening up to Class S.

NC

A18

A0
A1
A2
A3
A4

CS
I/O1
I/O2

Vcc

Vss

I/O3
I/O4

WE

A5
A6
A7
A8
A9

A17
A16
A15

OE
I/O8
I/O7

Vss
Vcc

A14
A13
A12
A11

NC

A10

I/O5

I/O6

1 36

18 19

ROW

DECODER

INPUT

DATA

CONTROL

MEMORY MATRIX

1024 ROWS x 4096 COLUMNS

COLUMN I/O

COLUMN DECODER

CS

A13

A0A1A3

DQ0

DQ7

DQ0

DQ7

A14A15A16A17A18

A2

A12
A11
A10

A9
A8
A7
A6
A5
A4

WE
OE

32C408B

Logic Diagram

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All data sheets are subject to change without notice

©2002 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

TABLE 1. 32C408B ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL MIN MAX UNIT
Voltage on any pin relative to V

SS

VIN, V

OUT

-0.5 VCC+0.5 V

Voltage on V

CC

supply relative to V

SS

V

CC

-0.5 7.0 V

Power Dissipation P

D

-- 1.0 W

Storage Temperature T

S

-65 +150

°

C

Operating Temperature T

A

-55 +125

°

C

TABLE 2. 32C408B RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL MIN MAX UNIT
Supply Voltage V

CC

4.5 5.5 V

Ground V

SS

00V

Input High Voltage

1

1. VIH(max) = VCC + 2.0V ac(pulse width < 10ns) for I < 20mA.

V

IH

2.2 VCC+0.5 V

Input Low Voltage

2

2. VIL (min) = -2.0V ac(pulse width < 10ns) for I < 20mA.

V

IL

-0.5 0.8 V

Thermal Impedance

Θ

JC

-- 0.63 °C/W

TABLE 3. 32C408B DC ELECTRICAL CHARACTERISTICS

(VCC=5V +/- 10%, TA = -55 TO +1‘25C, UNLESS OTERWISE SPECIFIED

PARAMETER CONDITION SYMBOL SUBGROUPS MIN TYP MAX UNIT
Input Leakage Current VIN = VSS to V

CC

I

LI

1, 2, 3 -2 -- 2 µA

Output Leakage Current CS

=VIH or OE=VIH or WE=VIL,

V

OUT

=VSS to V

CC

I

LO

1, 2, 3 -2 -- 2 µA

Output Low Voltage I

OL

= 8mA V

OL

1, 2, 3 -- -- 0.4 V

Output High Voltage I

OH

= -4mA V

OH

1, 2, 3 2.4 -- V

Average Operating Cur­rent

-20

-25

-30

Min cycle, 100% Duty, CS

=VIL,

I

OUT

=0mA, VIN = VIH or V

IL

I

CC

1, 2, 3

--

--

--

-­180
170
160

mA

Standby Power Supply
Current

CS

= V

IH

I

SB

1, 2, 3 -- -- 60 mA

f = 0MHz, CS

> VCC - 02V, VIN >

V

CC

- 0.2V or VIN < 0.2V

I

SB1

1, 2, 3 -- -- 10

Input Capacitance

1

1. Guaranteed by Design

V

IN

= 0V, f = 1MHz, TA = 25 ° C. C

IN

1, 2, 3 -- -- 7 pF

Output Capacitance

1

V

I/O

= 0V C

I/O

1, 2, 3 -- -- 8 pF

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All data sheets are subject to change without notice

©2002 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

TABLE 4. 32C408B AC CHARACTERISTICS FOR READ CYCLE

(VCC=5V +/- 10%, TA = -55 TO +1‘25C, UNLESS OTERWISE SPECIFIED

PARAMETER SYMBOL SUBGROUPS MIN TYP MAX UNIT
Read Cycle Time

-20

-25

-30

t

RC

9, 10, 11

20
25
30

--

--

--

--

--

--

ns

Address Access Time

-20

-25

-30

t

AA

9, 10, 11

--

--

--

--

--

--

20
25
30

ns

Chip Select Access Time

-20

-25

-30

t

CO

9, 10, 11

--

--

--

--

--

--

20
25
30

ns

Output Enable to Output Valid

-20

-25

-30

t

OE

9, 10, 11

--

--

--

--

--

--

10
12
14

ns

Chip Select to Output in Low-Z

-20

-25

-30

t

LZ

9, 10, 11

--

--

--

3
3
3

--

--

--

ns

Output Enable to Output in Low-Z

-20

-25

-30

t

OLZ

9, 10, 11

--

--

--

0
0
0

--

--

--

ns

Chip Deselect to Output in High-Z

-20

-25

-30

t

HZ

9, 10, 11

--

--

--

5
6
8

--

--

--

ns

Output Disable to Output in High-Z

-20

-25

-30

t

OHZ

9, 10, 11

--

--

--

5
6
8

--

--

--

ns

Output Hold from Address Change

-20

-25

-30

t

OH

9, 10, 11

3
5
5

--

--

--

--

--

--

ns

Chip Select to Power Up Time

-20

-25

-30

t

PU

9, 10, 11

--

--

--

0
0
0

--

--

--

ns

Chip Select to Power Down Time

-20

-25

-30

t

PD

9, 10, 11

--

--

--

10
15
20

--

--

--

ns

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All data sheets are subject to change without notice

©2002 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

TABLE 5. 32408B FUNCTIONAL DESCRIPTION

1

1. X = don’t care.

CS

WE OE MODE I/O PIN SUPPLY CURRENT

H X X Not Select High-Z ISB, I

SB1

L H H Output Disable High-Z I

CC

L H L Read D

OUT

I

CC

LLXWriteDINI

CC

TABLE 6. 32C408B AC CHARACTERISTICS FOR WRITE CYCLE

(VCC=5V +/- 10%, TA = -55 TO +1‘25C, UNLESS OTERWISE SPECIFIED

PARAMETER SYMBOL SUBGROUPS MIN TYP MAX UNIT
Write Cycle Time

-20

-25

-30

t

WC

9, 10, 11

20
25
30

--

--

--

--

--

--

ns

Chip Select to End of Write

-20

-25

-30

t

CW

9, 10, 11

14
15
17

--

--

--

--

--

--

ns

Address Setup Time

-20

-25

-30

t

AS

9, 10, 11

0
0
0

--

--

--

--

--

--

ns

Address Valid to End of Write

-20

-25

-30

t

AW

9, 10, 11

14
15
17

--

--

--

--

--

--

ns

Write Pulse Width (OE

High)

-20

-25

-30

t

WP

9, 10, 11

14
15
17

--

--

--

--

--

--

ns

Write Recovery Time

-20

-25

-30

t

WR

9, 10, 11

0
0
0

--

--

--

--

--

--

ns

Write to Output in High-Z

-20

-25

-30

t

WHZ

9, 10, 11

--

--

--

5
5
6

--

--

--

ns

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All data sheets are subject to change without notice

©2002 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

FIGURE 1. TIMING WAVEFORM OF WRITE CYCLE(1) (OE CLOCK)

Write Pulse Width(OE Low)

-20

-25

-30

t

WP1

9, 10, 11

--

--

--

20
25
30

--

--

--

ns

Data to Write Time Overlap

-20

-25

-30

t

DW

9, 10, 11

9
10
11

--

--

--

--

--

--

ns

End Write to Output Low-Z 1

-20

-25

-30

tOW 9, 10, 11

--

--

--

6
7
8

--

--

--

ns

Data Hold from Write Time

-20

-25

-30

t

DH

9, 10, 11

0

0

0

--

--

--

--

--

--

ns

TABLE 6. 32C408B AC CHARACTERISTICS FOR WRITE CYCLE

(VCC=5V +/- 10%, TA = -55 TO +1‘25C, UNLESS OTERWISE SPECIFIED

PARAMETER SYMBOL SUBGROUPS MIN TYP MAX UNIT

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All data sheets are subject to change without notice

©2002 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

FIGURE 2. TIMING WAVEFORM OF WRITE CYCLE (OE LOW FIXED)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS

and a low WE. A write begins at the latest transition among CS going low and

WE

going low: A write ends at the earliest transition among CS going high or WE going high. tWP is measured from beginning

of write to end of write.

3. t

CW

is measured from the later of CS going low to end of write.

4. t

AS

is measured from the address valid to the beginning of write.

5. t

WR

is measured from the end of write to the address change. TWR applied in case a write ends as CS or WE going high.

6. If OE

, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.

8. IC CS

goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state.

9. D

OUT

is the read data of the new address.

10.When CS

is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be

applied.

FIGURE 3. TIMING WAVEFORM OF READ CYCLE

(1)

(ADDRESS CONTROLLED, CS = OE = VIL, WE = VIH)

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All data sheets are subject to change without notice

©2002 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

FIGURE 4. TIMING WAVEFORM OF READ CYCLE

(2)

(WE = VIH)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. t

HZ

and t

OHZ

are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or

V

OL

levels.

4. At any given temperature and voltage condition, t

HZ(max)

is less than t

LZ(min)

both for a given device and from device to device.

5. Transition is measured +200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS

= VIL.

7. Address valid prior to coincident with CS

transition low.

8. For common I/O applications, minimization or elimination of bus contention is necessary during read and
write cycle.

FIGURE 5. SRAM HEAVY ION CROSS SECTION

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All data sheets are subject to change without notice

©2002 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

FIGURE 6. SRAM PROTON SEU CROSS SECTION STATIC

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All data sheets are subject to change without notice

©2002 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

F36-01

Note: All dimensions in inches

36 PIN FLAT RAD-PAK® PACKAGE

SYMBOL

DIMENSION

MIN NOM MAX

A 0.122 0.135 0.148
b 0.015 0.017 0.019

c 0.008 0.010 0.012
D -- 0.930 0.940
E 0.638 0.645 0.652

E1 -- -- 0.690
E2 0.560 0.565 -­E3 0.005 0.040 --

e 0.050 BSC
L 0.390 0.400 0.410
Q 0.088 0.098 0.108

S1 0.005 0.032 --

N36

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All data sheets are subject to change without notice

©2002 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

Important Notice:
These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies

functionality by testing key parameters either by 100% testing, sample testing or characterization.
The specifications presented within these data sheets represent the latest and most accurate information available to

date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.

Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.

Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech­nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.

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All data sheets are subject to change without notice

©2002 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

Product Ordering Options

Model Number

Feature

Option Details

2C408B

XX

F X

-XX
Access Time

Screening Flow

Package

Radiation Feature

Base Product
Nomenclature

20 = 20 ns
25 = 25 ns
30 = 30 ns

Monolithic
S = Maxwell Class S
B = Maxwell Class B
E = Engineering (testing @ +25°

C)

I = Industrial (testing @ -55°C,
+25°C, +125°C)

F = Flat Pack

RP = R

AD-PAK® package

CMOS 512kword x 8-bit Static
RAM