High-Current
Complementary Silicon
Power Transistors
These packages are designed for use in high-power amplifier and
switching circuit applications.
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Features
•High Current Capability - I
•DC Current Gain - h
FE
Continuous = 50 Amperes
C
= 15-60 @ IC = 25 Adc
•Low Collector-Emitter Saturation Voltage -
V
= 1.0 Vdc (Max) @ IC = 25 Adc
CE(sat)
•Pb-Free Packages are Available*
MAXIMUM RATINGS (Note 1)
RatingSymbolValueUnit
Collector-Emitter VoltageV
Collector-Base VoltageV
Emitter-Base VoltageV
Collector Current - ContinuousI
Base CurrentI
Total Power Dissipation @ TC = 25°C
Derate above 25°C
Operating and Storage Temperature
Range
CEO
P
TJ, T
CB
EB
C
B
D
stg
THERMAL CHARACTERISTICS
CharacteristicSymbolMaxUnit
Thermal Resistance, Junction-to-Case
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Indicates JEDEC Registered Data.
300
250
200
150
q
JC
80Vdc
80Vdc
5.0Vdc
50Adc
15Adc
300
1.715
-65 to +200°C
0.584°C/W
mW
mW/°C
50 AMPERE
COMPLEMENTARY SILICON
POWER TRANSISTORS
60-80 VOLTS, 300 WATTS
MARKING
DIAGRAM
2N568xG
AYYWW
MEX
TO-204 (TO-3)
CASE 197A
STYLE 1
2N568x= Device Code
G= Pb-Free Package
A= Location Code
YY= Year
WW= Work Week
MEX= Country of Orgin
ORDERING INFORMATION
DevicePackageShipping
2N5684GTO-3
2N5686TO-3100 Units/Tray
2N5686GTO-3
x = 4 or 6
100 Units/Tray
(Pb-Free)
100 Units/Tray
(Pb-Free)
100
, POWER DISSIPATION (WATTS)
50
D
P
0
020406080100120 140160 180200
TEMPERATURE (°C)
Figure 1. Power Derating
Safe Area Curves are indicated by Figure 5. All limits are applicable and must be observed.
2.0 3.07.0 10203050100
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
5.0
500 μs
5.0 ms
2N5684, 2N5686
Figure 5. Active-Region Safe Operating Area
4.0
3.0
2.0
1.0
0.8
t, TIME (s)μ
0.6
0.4
0.3
0.2
0.5
0.7 1.02.0 3.07.02050
2N5684 (PNP)
2N5686 (NPN)
t
s
t
f
5.0
IC, COLLECTOR CURRENT (AMP)
10
Figure 6. Turn-Off Time
1.0 ms
100 μs
70
TJ = 25°C
IB1 = I
B2
IC/IB = 10
VCE = 30 V
30
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate IC - V
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 5 is based on T
= 200_C; TC is
J(pk)
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T
v 200_C. T
may be calculated from the data in
J(pk)
J(pk)
Figure 4. At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the
limitations imposed by second breakdown.
5000
TJ = 25°C
3000
2000
C
ib
C
1000
C, CAPACITANCE (pF)
700
500
0.1
C
ib
2N5684 (PNP)
2N5686 (NPN)
2.05.01020100500.20.51.0
VR, REVERSE VOLTAGE (VOLTS)
Figure 7. Capacitance
ob
C
ob
CE
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3
Page 4
2N5684 (PNP), 2N5686 (NPN)
PNP
2N5684
500
300VCE = 2.0 V
200
100
70
50
30
, DC CURRENT GAIN
20
FE
h
10
7.0
5.0
TJ = +150°C
+25°C
-55°C
0.5
0.7 1.02.05.0 7.0 102050
3.030
IC, COLLECTOR CURRENT (AMP)
VCE = 10 V
Figure 8. DC Current Gain
2.0
TJ = 25°C
1.6
40 A
1.2
IC = 10 A
25 A
NPN
2N5686
500
300
200
100
70
50
30
, DC CURRENT GAIN
20
FE
h
10
7.0
5.0
2.0
1.6
1.2
0.5
TJ = +150°C
+25°C
-55°C
0.7 1.02.05.0 7.0 102050
IC = 10 A
3.030
IC, COLLECTOR CURRENT (AMP)
25 A
40 A
VCE = 2.0 V
VCE = 10 V
TJ = 25°C
0.8
0.4
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
CE
V
0
0.1
0.21.02.05.010
0.53.0
IB, BASE CURRENT (AMP)
Figure 9. Collector Saturation Region
2.5
TJ = 25°C
2.0
1.5
V
@ IC/IB = 10
BE(sat)
1.0
V, VOLTAGE (VOLTS)
0.5
0
0.5
0.7 1.02.03.05.0102050
VBE @ VCE = 2.0 V
V
@ IC/IB = 10
CE(sat)
IC, COLLECTOR CURRENT (AMP)
7.0
0.8
0.4
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
CE
V
0
0.1
2.0
1.6
1.2
0.8
V, VOLTAGE (VOLTS)
0.4
30
0
0.5
Figure 10. “On” Voltages
0.21.02.05.010
TJ = 25°C
V
@ IC/IB = 10
BE(sat)
0.7 1.02.03.05.0102050
0.53.0
0.3
IB, BASE CURRENT (AMP)
VBE @ VCE = 2.0 V
V
@ IC/IB = 10
CE(sat)
IC, COLLECTOR CURRENT (AMP)
30
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4
Page 5
2N5684 (PNP), 2N5686 (NPN)
PACKAGE DIMENSIONS
TO-204 (TO-3)
CASE 197A-05
ISSUE K
A
N
C
E
2 PLD
0.30 (0.012)Y
U
V
H
L
2
1
G
K
-Y-
-T-
M
SEATING
PLANE
M
Q
T
M
B
-Q-
0.25 (0.010)T
M
M
Y
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIM MINMAX MIN MAX
A1.530 REF38.86 REF
B 0.990 1.050 25.15 26.67
C 0.250 0.335 6.358.51
D 0.057 0.063 1.451.60
E 0.060 0.070 1.531.77
G0.430 BSC10.92 BSC
H0.215 BSC5.46 BSC
K 0.440 0.480 11.18 12.19
L0.665 BSC16.89 BSC
N 0.760 0.830 19.31 21.08
Q 0.151 0.165 3.844.19
U1.187 BSC30.15 BSC
V 0.131 0.188 3.334.77
STYLE 1:
PIN 1. BASE
2. EMITTER
CASE: COLLECTOR
MILLIMETERSINCHES
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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2N5684/D
5
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