Datasheet 29C8192 Datasheet (Turbo IC)

HIGH SPEED CMOS

8 Megabit PROGRAMMABLE and ERASABLE ROM

1024K X 8 BIT FLASH PEROM

DESCRIPTION:

The Turbo IC 29C8192 is a 1024K x 8 Flash programmable
and erasable read only memory (PEROM) fabricated with
T urbo IC’ s proprietary, high reliability , high performance CMOS
technology . Its 8192K bits of memory are organized as 1024K
by 8 bits. The device offers access time of 250 ns with
power dissipation below 50 mW .

The 29C8192 has a 4096 bytes sector program operation
enabling the entire memory to be programmed typically in
less than 10 seconds. During a program operation, the ad­dress and a complete sector (4096 bytes) of data are inter­nally latched, freeing the address and data bus for other
microprocessor operations. The programming process is au­tomatically controlled by the device using an internal con­trol timer. Data polling on I/O7 or a T oggle bit can be used to
detect the end of a programming cycle. In addition, the
29C8192 includes an user-optional software data write mode
offering additional protection against unwanted (false) write.

The 29C8192 does not require a separate high voltage to
program the device. The 1.8V to 3.6Vsource is all that is
required.

FEATURES:

• Single Supply V oltage f or Read and Program Operations

Vcc = 1.8V to 3.6V

• Fast Read Access Time
150ns for Vcc = 2.7V to 3.6V
200ns for Vcc = 1.8V to 3.6V

• Sector Program Operation
Single Cycle Reprogram (Erase & Program)
256 Sectors (4096 bytes/sector)
Internal Address and Data Latches for 4096 Bytes

• Automatic Sector Programming Operation
Internal Control Timer

• Fast Prog ram Times
Sector Program ( Erase & Write ) Cycles : 40 ms
Typical
T otal Time to Reprogram the Entire Memory ( 256
sectors ) : 10 s Typical
Typical Byte Program Cycle Time: 10 µs

• JEDEC Standard Software Data Protection

• Low Po wer Dissipation

15 mA Active Current
20 µA CMOS Standby Current

• Direct Microprocessor End of Program Detection
Data Polling

• High Reliability CMOS Technology
Endurance: 100,000 Cycles
Data Retention: 10 years

• JEDEC Approved Byte Pinout

PIN CONFIGURA TION:

29C8192

ADVANCE INFORMATION

Turbo IC, Inc.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

23

24

25

26

27

28

NC

A16

A15

A12

A7
A6
A5
A4

A3
A2
A1

A0
I/O0
I/O1

VCC

WE

A17

A14

A13

A8

A9

A11

OE

A10

CE

I/O7
I/O6
I/O5

29

30

31

32

I/O4

I/O3

I/O2

GND

33

34

35

36

37

38

39

41

44 pins SOIC

42

43

44

40

GND

NC

NC

RESET

RDY/BSY

NC

NC

NC

NC

VCC

A18
A19

CHIP ENABLE (CE)

The Chip Enable input must be low to enable all read/program operations
on the device. By setting CE high, the device is disabled and the power
consumption is extremely low with the standby current below 10 µA.

ADDRESSES (A0 - A19)

The Addresses are used to select an 8 bits memory location during a
program or read operation.

PIN DESCRIPTION

OUTPUT ENABLE (OE)

The Output Enable input activates the output buffers during the read op­erations.

DATA INPUT/OUTPUT (I/O0-I/O7)

Data Input/Output pins are used to read data out of the memory or to
program Data into the memory.

RESET

The RESET = HIGH puts the device in standard operating mode. The
RESET = LOW interrupts any interval activity in the device and puts it I/O
in high impedance condition. If the RESET pin makes a high to low
transition during a program cycle, the program operation is interrupted by
the RESET signal and it will have to be repeated in a new programming
cycle after RESET pin goes HIGH. After exercising a RESET function (
RESET = LOW ) and returning to normal standard operation (RESET =
HIGH) the device returns to a standby or read mode according to the
status of CE, OE, and WE pins.

RDY/BUSY

The RD Y/BUSY pin is an open drain output giving the user the opportunity
to have a single RDY/BUSY by more than one component during a pro­gram cycle the RDY/BUSY pin is actively pulled low. When the program
cycle is finished, the RD Y/BUSY pin becomes high impedance and can be
pulled HIGH by an external resistance connected between the VCC and
RDY/BUSY pins.

DEVICE OPERA TION

READ
The 29C8192 is accessed like a static RAM. Read operations are initiated

by both CE and OE on low and terminated by either CE or OE returning
high. The outputs are at the high impedance state whenever CE or OE
returns high. The two line control architecture gives designers flexibility in
preventing bus contention.

PROGRAM
A program cycle is initiated when CE and WE are low and OE is high. The

address is latched internally on the falling edge of the CE or WE, which­ever occurs last. The data is latched by the rising edge of CE or WE,
whichever occurs first. Once a programming cycle has been started, the
internal timer automatically generates the program sequence to the comple­tion of the program operation.

SECTOR PROGRAM OPERATION
The device is reprogrammed on a sector basis. When a byte of data within

a sector is to be changed, data for the entire sector must be loaded into the
device. Any b yte that is not loaded during the programming of its sector will
be erased to read FFh. The programming operation of the 29C8192 al­lows 4096 bytes of data to be serially loaded into the device and then
simultaneously written into memory during the internally generated pro­gram cycle. After the first byte has been loaded, successive bytes of data
must be loaded until the full sector of 4096 bytes is loaded. Each new byte
to be written must be loaded within 300 µs of the previously loaded byte.
The sector address defined by the addresses A0 - A7 is latched by the
first CE or WE falling edge which initiates a program cycle and they stay
latched until the completion of the program cycle. Any changes in the
sector addresses during the load-program cycle will not affect the initially
latched sector address. Addresses A8 - A19 are used to define which
bytes will be loaded within the 4096 bytes sector. The bytes may be
loaded in any order that is convenient to the user. All the 4096 bytes of the
page are serially loaded and are programmed in a single 40 ms program
cycle

DATA POLLING
The 29C8192 features DATA Polling to indicate the completion of a pro-

gram cycle to the host system. During a program cycle, an attempted
read of the last byte loaded into the page will result in the complement of
the loaded byte on I/O7, i.e., loaded 0 would be read 1. Once the program
cycle has been completed, true data is valid on all outputs and the next
cycle may be started. DATA Polling may begin at any time during the
programming cycle.

TOGGLE BIT

In addition to DATA Polling the 29C8192 provides another method for
determining the end of a programming or erase cycle. During a program
or erase operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the program cycle has
completed, I/O6 will stop toggling and valid data will be read. Examining
the toggle bit may begin at any time during a program cycle.

CHIP CLEAR
The content of the entire memory array of the 29C8192 may be altered to

HIGH by the use of the CHIP CLEAR operation. By setting CE to low, OE
to 12 V olts , and WE to low , the entire memory arra y can be cleared (written
HIGH) within 20 ms. The CHIP CLEAR operation is a latch operation mode.
After CE, WE, and OE get the CHIP CLEAR process started, the internal
chip timer takes over the CHIP CLEAR operation and CE, OE, or WE
becomes free to be used by the system for other purposes.

HARDWARE DATA PROTECTION
The 29C8192 has three hardware features to protect the written content

of the memory against inadvertent programming:
a) Vcc threshold detector - If Vcc is below 1.8 V the program capabilities

of the chip is inhibited for whatever input conditions.
b) Noise protection - A WE, OE, or CE pulse of less than 10 ns in width is
not able to initiate a program cycle.
c) Write inhibit - Holding OE at low , or CE at high, or WE at high inhibits the
program cycle.

SOFTWARE DATA PROTECTION
The 29C8192 offers a software controlled data program protection fea-

ture. The device is delivered to the user with the software data protection
DISABLED, i.e., the de vice will go to the progr am operation as long as Vcc
exceeds 1.8 V and CE, WE, and OE inputs are set at program mode
levels. The 29C8192 can be automatically protected against an accidental
write operation during power-up or power-down without any external cir­cuitry by enabling the software data protection feature. This feature is
enable after the first program cycle which includes the software algorithm.
After this operation is done the program function of the device may be
performed only if every program cycle is preceded by the software algo­rithm. The device will maintain its software protect feature for the rest of its
life, unless the software algorithm for disabling the protection is imple­mented.

ADVANCE INFORMATION

29C8192

Turbo IC, Inc.

WRITE ENABLE (WE)

The Write Enable input initiates the programming of data into the memory.

SOFTWARE ALGORITHM
The 29C8192 has an internal register for the software algorithm which

enables the memory to provide the user with additional features:
a) Software Data Protect Enable
A sequence of the three dummy data writes to the memory will activate

internal EEPROM fuses during the first page write cycle. These EEPROM
fuses will reject any write attempts of new pages of data, unless the three
dummy data writes are repeated at the beginning of any page writes.

The timing for the dummy data and addresses must be the same as for a
normal program operation. A violation of the three steps program protect
sequence in data or address timing and content will abort the procedure
and reset the device to the starting point condition.

Note: Software data protect enable procedure must be performed as part
of a standard program cycle. If no additional page data is added to the
three dummy data writes, the software data protect enable procedure will
be aborted. The data protect state will be activated at the end of the pro­gram cycle. 4096 bytes of data must be loaded during a Software Data
Protection Enable cycle.

Table 1 shows the required procedure for enabling the software data pro­tect:

TABLE 1

STEP MODE ADD.A14-A0 DATA I/O 7-0

1 Page Write 5555 Hex AA Hex
2 Page Write 2AAA Hex 55 Hex
3 Page Write 5555 Hex A0 Hex
4-131 Page Write Address Sector Data (4096 Bytes)

b) Software Data Protect Disable
The software algorithm of 29C8192 includes a six step sequence dummy

data programming sequence to disable the software data protect feature
described in a). The six step sequence shown in Table 2 must be per­formed at the beginning of a program cycle. A violation of the six step
program sequence in data or address timing and content will abort the
procedure and reset the chip to the starting point condition. After a soft­ware data protect disable cycle including the six step sequence has been
performed, the 29C8192 does not require the use of three dummy loads
described in a) for the following program cycle. The device is at the soft­ware data protect disabled state.

Note: When six step sequence of software data protect disable procedure
is performed, if no additional bytes of data is added after the six-step write
sequence, the software data protect disable procedure will be aborted.
The data protect state will be deactivated at the end of the program period.
4096 bytes of data must be loaded during a Software Data Protection
disable cycle.

Table 2 shows the required procedure for disabling the software data pro­tect:

TABLE 2

STEP MODE ADD.A14-A0 DATA I/O 7-0

1 Page Write 5555 Hex AA Hex
2 Page Write 2AAA Hex 55 Hex
3 Page Write 5555 Hex 80 Hex
4 Page Write 5555 Hex AA Hex
5 Page Write 2AAA Hex 55 Hex
6 Page Write 5555 Hex 20 Hex
7-134 Page Write Address Sector Data (4096 Bytes)

C) Software Chip Clear
The software algorithm of 29C8192 includes a sequence of six step

dummy data writing to perform a chip clear operation. Table 3 shows the
six step write sequence to perform the software chip clear operation:

TABLE 3

STEP MODE ADD.A14-A0 DATA I/O 7-0

1 Page Write 5555 Hex AA Hex
2 Page Write 2AAA Hex 55 Hex
3 Page Write 5555 Hex 80 Hex
4 Page Write 5555 Hex AA Hex
5 Page Write 2AAA Hex 55 Hex
6 Page Write 5555 Hex 10 Hex

At the end of the six step program sequence shown in Table 3, the
device automatically activates its internal timer to control the chip erase
cycle; typically takes 20 msec. After a software chip clear operation has
been completed, all 8192K bit locations of memory show high level at
read operation mode.

d) Software Autoclear Disable Mode
This software algorithm disables the internal automatic clear before a pro-

gram cycle. Table 4 shows the six steps needed to perform the autoclear
disable mode.

TABLE 4

STEP MODE ADD.A14-A0 DATA I/O 7-0

1 Page Write 5555 Hex AA Hex
2 Page Write 2AAA Hex 55 Hex
3 Page Write 5555 Hex 80 Hex
4 Page Write 5555 Hex AA Hex
5 Page Write 2AAA Hex 55 Hex
6 Page Write 5555 Hex 40 Hex
7-134 Page Write Address Sector Data (4096 Bytes)

Program operation using the software autoclear disable mode will reduce
programming time to typically 8 µs per byte. The program cycle using
software autoclear disable mode is usually used after a chip clear or a
software chip clear operation. At the end of the six step sequence, the
autoclear before program is disabled and will stay that way unless a power­down occurs or the software autoclear enable procedure is initiated.

e) Software Autoclear Enable Mode
Automatic page clear before page program can be restored to 29C8192

either by Vcc power-down or by software autoclear enable mode. Table 5
shows the six step page procedure needed to enable software autoclear
mode:

TABLE 5

STEP MODE ADD.A14-A0 DATA I/O 7-0

1 Page Write 5555 Hex AA Hex
2 Page Write 2AAA Hex 55 Hex
3 Page Write 5555 Hex 80 Hex
4 Page Write 5555 Hex AA Hex
5 Page Write 2AAA Hex 55 Hex
6 Page Write 5555 Hex 50 Hex
7-134 Page Write Address Sector Data (4096 Bytes)

29C8192

Turbo IC, Inc.

ADVANCE INFORMATION

A.C. CHARACTERISTICS - READ OPERATION

29C8192-1 29C8192-2 29C8192-3

Symbol Parameters Min Max Min Max Min Max Unit
tacc Address to 250 350 400 n s

Output Delay

tce CE to Output 250 350 400 n s

Delay
toe OE to Output 120 130 140 ns
tdf OE to Output 0 100 0 110 0 120 ns

In High Z
toh Output Hold 0 0 0 ns

from Address

Changes, Chip

Enable or

Output Enable

Whichever

Occurs First

Symbol Parameter Condition Min Max Units

Vcc Power Supply 1.8 3.6 V
Icc Active Vcc CE=OE=Vil; All I/O 15 (C ) mA

Current Open, Min Read or 17 (I ) mA

Write Cycle Time 20 (M) mA

Isb1 CMOS CE=Vcc-0.3 V to 20 (C) µA

Standby Vcc+1 V 50 (I&M) µA
Current

Isb2 TTL Standby CE=Vih, OE=Vil, 1 mA

Current All I/O Open, Other

Inputs=Vcc Max

Iil Input Vin=Vcc Max 1 µA

Leakage
Current

Iol Output 1 µA

Leakage
Current

Vil Input Low 0.6 V

V oltage

Vih Input High 1.8 V

Voltage

Vol Output Low Iol=1.6 mA 0.45 V

Voltage Vcc = 3V

Voh Output High Ioh = -100 uA 2 .4 V

Voltage Vcc = 3V

(C) = COMMERCIAL
(I) = INDUSTRIAL
(M) = MILITARY

tacc

ADDRESS VALIDADDRESS

CE

OE

OUTPUT HIGH-Z

toe

tce

tdf

toh

OUTPUT VALID

HIGH-Z

A.C. TEST CONDITIONS

Output Load : 1 TTL Load and Cl=100 pF
Input Rise and Fall Times : < 10 ns
Input Pulse Level : 0.45 V to 2.4V

D.C. CHARACTERISTICS

ABSOLUTE MAXIMUM STRESS RANGES *

A.C. Read Wave Forms

RECOMMENDED OPERATING CONDITIONS
Temperature Range: Commercial: 0° C to 70° C

Industrial: -40° C to 85° C
Military: -55° C to 125° C

Vcc Supply Voltage: 1.8V to 3.6V
Endurance: 10,000 Cycles/Byte (Typical)

Data Retention: 10 Y ears

* “Absolute Maximum Ratings” may cause permanent damage to the de-

vice. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operation sec­tion of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

TEMPERATURE

Storage: -65° C to 150° C
Under Bias: -55° C to 125° C

ALL INPUT OR OUTPUT VOLTAGES

with respect to Vss +6 V to -0.3 V

ADVANCE INFORMATION

29C8192

Turbo IC, Inc.

OE

ADDRESS

CE

WE

DATA

toes

tas

tcs tah

toeh

tch

twp

tds

tblc

twc

tdh

HIGH-Z

DATA VALID

HIGH-Z

VALID

OE

ADDRESS

CE

WE

DATA

toes

tas

tcs tah

toeh

tch

twp

tds

tblc

twc

tdh

HIGH-Z

DATA VALID

HIGH-Z

VALID

A.C. WRITE CHARACTERISTICS

Symbol Parameter Min Max Units
tas Address Set-up Time 20 ns
tah Address Hold Time 100 ns
tcs Wr ite Set-up Time 0 ns
tch Write Hold Time 0 ns
tcw CE Pulse Width 200 n s
twp WE Pulse Width 200 ns
toes OE Set-up Time 20 n s
toeh OE Hold Time 20 ns
tds Data Set-up Time 100 n s
tdh Data Hold Time 10 n s
tblc Byte Load Cycle 0.2 300 µs
tlp Last Byte Loaded to Data

Polling Output 500 µ s

twc Write Cycle Time 40 ms

A.C. Write W ave Forms WE-Controlled

A.C. Write W ave Forms CE-Controlled

29C8192

Turbo IC, Inc.

ADVANCE INFORMATION

OE

CE

WE

A0-A6

DATA

twp

twph

tah

tas

tds

tdh

BYTE-0

BYTE-1

BYTE-2

BYTE
ADDRESS

A7-A16

SECTOR
ADDRESS

//

//

//
//
//
//

//
//
//

BYTE- 126

BYTE-127

Sector Mode Write W ave Forms (1,2,3)

Note: 1. Addresses A0 to A7 define the 256 sectors and are latched by the first high to low transition of WE or CE of the first loading cycle.

2. OE must be high when WE and CE are both low.

3. All bytes that are not loaded within the sector being programmed will be erased to FF.

Turbo IC, Inc.

ADVANCE INFORMATION

29C8192

Note:

1. Toggling either OE or CE or both will operate toggle bit.

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

DATA Polling Characteristics

Symbol Parameter Min Max Unit

tdh Data Hold Time 10 ns
toeh OE Hold Time 10 ns
toe OE to Output Delay (1) ns
twr Write Recovery Time 0 ns

Note: 1. See toe Specification in AC Characteristics - Read Operation

DATA P olling Wave Forms

WE

CE

OE

A0-A16

An

An

An

//

//

//

//

//

//

I/O7

twr

tdh toe

toeh

An An

HIGH Z

Toggle Bit Characteristics

Symbol Parameter Min Max Unit

tdh Data Hold Time 10 ns
toeh OE Hold Time 10 ns
toe OE to Output Delay (1) ns
toeh OE High Pulse 150 ns

Note: 1. See toe Specification in AC Characteristics - Read Operation

Toggle Bit Wave Forms (1,2,3)

WE

CE

OE

//

//

//

//

I/O6

tdh

toe

HIGH Z

toeh

Turbo IC, Inc.

29C8192

ADVANCE INFORMATION

Turbo IC, Inc. 2365 Paragon Drive, Suite I, San Jose, CA 95131 Phone: [phone] Fax: [phone]

See us at www.turbo-ic.com

Rev . 2.0 - 10/28/

01

OE

ADDRESS

CE

WE

DATA

toes

tas

tcs tah

toeh

tch

twp

tds

tblc

twc

tdh

HIGH-Z

DATA VALID

HIGH-Z

VALID

Chip Clear Wave Form

The content of the 29C8192 may be altered to HIGH by the use of the
Chip Clear operation. By setting CE to low, OE to 12 volts, and WE to
low, the entire memory can be cleared (written HIGH) within 20 ms.
The Chip Clear operation is a latch operation mode. After the Chip
Clear starts, the internal chip timer takes over and completes the clear
without CE, OE and WE being held active.

TURBO IC PRODUCTS AND DOCUMENTS

1. All documents are subject to change without notice. Please contact Turbo IC for the latest
revision of documents.

2. T urbo IC does not assume any responsibility f or any damage to the user that may result from
accidents or operation under abnormal conditions.

3. Turbo IC does not assume any responsibility for the use of any circuitry other than what
embodied in a Turbo IC product. No other circuits, patents, licenses are implied.

4. T urbo IC products are not authorized f or use in lif e support systems or other critical systems
where component failure may endanger life. System designers should design with error
detection and correction, redundancy and back-up features.

ADVANCE INFORMATION

29C8192

Turbo IC, Inc.