Page 1
M
4K/8K 2.5 I2C™ Serial EEPROMs
24LC04B/08B
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current typical
-10 µA standby current typical at 5.5V
-5 µA standby current typical at 3.0V
• Organized as two or four blocks of 256 bytes
(2 x 256 x 8) and (4 x 256 x 8)
• 2-wire serial interface bus, I
• Schmitt trigger, filtered inputs for noise
suppression
• Output slope control to eliminate ground bounce
• 100 kHz (E-temp) and 400 kHz (C/I-temp.)
compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 erase/write cycles ensured
• Data retention > 200 years
• 8-pin DIP, 8-lead SOIC, 8-pin TSSOP packages
• Available temperature ranges:
- Commercial (C): 0°C to +70°C
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
2
C™ compatible
DESCRIPTION
The Microchip Technology Inc. 24LC04B/08B is a 4
Kbit or 8 Kbit Electrically Erasable PROM (EEPROM).
The device is organized as two or four blocks of 256 x
8-bit memory with a 2-wire serial in terface. L ow volt age
design permits operation down to 2.5 volts with typical
standby and active currents of only 5 µA and 1 mA
respectively. The 24LC04B/08B also has a page-write
capability fo r up to 1 6 byte s of da ta. T he 24L C04B/08B
is available in the standard 8-pin DIP, 8-lead surface
mount SOIC, MSOP and TSSOP packages.
PACKAGE TYPES
PDIP, SOIC
A0
1
A1
2
A2
3
Vss
TSSOP
A0
A1
A2
VSS
MSOP
VSS
Note: A0, A1 and A2 are not used
A0
A1
A2
4
1
2
3
4
1
2
3
4
BLOCK DIAGRAM
WP
I/O
CONTROL
LOGIC
SDA SCL
VCC
VSS
MEMORY
CONTROL
LOGIC
XDEC
24LC04B/08B
24LC04B/08B
24LC04B/08B
8
V
CC
7
WP
6
SCL
5
SDA
8
VCC
7
WP
6
SCL
5
SDA
8
VCC
7
WP
6
SCL
5
SDA
HV GENERATOR
EEPROM ARRAY
(2 x 256 x 8) or
(4 x 256 x 8)
PAGE LATCHES
YDEC
SENSE AMP
R/W CONTROL
2001 Microchip Technology Inc. DS21051H-page 1
Page 2
24LC04B/08B
1.0 ELECTRICAL CHARACTERISTICS
1.1 Maximum Ratings*
VCC........................................................................7.0V
All inputs and outputs w.r.t. V
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied.....-65°C to +125°C
Soldering temperature of leads (10 seconds)..+300°C
ESD protection on all pins .....................................≥ 4 KV
*Notice: Stresses above those listed under “Maximum
ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at those or any other
conditions above those indicated in the operational listings of this specification is not implied.
Exposure to maximum rating conditions for
extended periods may affect device reliability.
SS ....-0.3V to VCC + 1.0V
TABLE 1-1: PIN FUNCTION TABLE
Name Function
SS Ground
V
SDA Serial Address/Data I/O
SCL Serial Clock
WP Write Protect Input
CC +2.5V to 5.5V Power Supply
V
A0, A1, A2 No Internal Connection
TABLE 1-2: DC CHARACTERISTICS
Commercial (C): T
VCC = +2.5V to +5.5V
Industrial (I): T
Automotive (E): T
Parameter Symbol Min. Max. Units Conditions
WP, SCL and SDA pins:
High level input voltage
Low level input voltage
Hysteresis of Schmitt trigger
IH
V
VIL
VHYS
.05 V
Inputs
Low level output voltage
VOL
Input leakage current ILI -10 10 µAVIN = 0.1V to VCC
Output leakage current ILO -10 10 µAVOUT = 0.1V to VCC
Pin capacitance
CIN, COUT — 10 pF VCC = 5.0V (Note)
(all inputs/outpu t s)
Operating current ICC Write
I
CC Read
Standby current I
Note: This parameter is periodically sampled and not 100% tested.
CCS —
.7 VCC
—
CC
—
—
—
—
AMB = 0°C to +70°C
AMB = -40°C to +85°C
AMB = -40°C to +125°C
.3 V
.40
—
CC
—
3
V
V
V
V
mAmAV
1
30
100
µA
µA
—
—
(Note)
IOL = 3.0mA, VCC = 2.5V
AMB = 25°C, FCLK = 1 MHz
T
CC = 5.5V, SCL = 400 kHz
—
VCC = 3.0V, SDA = SCL = VCC
VCC = 5.5V, SDA = SCL = VCC
WP = VSS
FIGURE 1-1: BUS TIMING START/S TOP
VHYS
SCL
TSU:STA
SDA
START STOP
DS21051H-page 2 2001 Microchip Technology Inc.
THD:STA
TSU:STO
Page 3
TABLE 1-3: AC CHARACTERISTICS
24LC04B/08B
Commercial (C): TAMB = 0°C to +70°C
VCC = +2.5V to 5.5V
Industrial (I): T
Automotive (E): T
AMB = -40°C to +85°C
AMB = -40°C to +125°C
Parameter Symbol Min Max Units Conditions
Clock frequency F
Clock high time T
Clock low time T
SDA and SCL rise time
(Note 1)
SDA and SCL fall time T
START condition hold time T
START condition setup time T
Data input hold time T
Data input setup time T
STOP condition setup time T
Output valid from clock
(Note 2)
Bus free time: Time the bus must be
free before a new transmission can
start
Output fall time from V
IH
minimum to VIL maximum
Input filter spike suppression
CLK —
—
HIGH 600
LOW 1300
4000
4700
T
R —
—
F — 300 ns (Note 1)
HD:STA 600
SU:STA 600
4000
4700
HD:DAT 0 — ns (Note 2)
SU:DAT 100
250
SU:STO 600
T
AA —
4000
—
T
BUF 1300
4700
T
OF 20+0.1CB
—
T
SP — 50 ns (Notes 1 and 3)
400
100
—
—
—
—
300
1000
—
—
—
—
—
—
—
—
900
3500
—
—
250
250
kHz 4.5V ≤ VCC ≤ 5.5V
≤ VCC ≤ 5.5V (E-temp. range)
2.5V
ns 4.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (E-temp. range)
ns 4.5V ≤ VCC ≤ 5.5V
≤ VCC ≤ 5.5V (E-temp. range)
2.5V
ns 4.5V ≤ VCC ≤ 5.5V (Note 1)
2.5V
≤ VCC ≤ 5.5V (E-temp. range) (Note 1)
ns 4.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (E-temp. range)
ns 4.5V ≤ VCC ≤ 5.5V
≤ VCC ≤ 5.5V (E-temp. range)
2.5V
ns 4.5V ≤ VCC ≤ 5.5V
2.5V
≤ VCC ≤ 5.5V (E-temp. range)
ns 4.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (E-temp. range)
ns 4.5V ≤ VCC ≤ 5.5V
≤ VCC ≤ 5.5V (E-temp. range)
2.5V
ns 4.5V ≤ VCC ≤ 5.5V
2.5V
≤ VCC ≤ 5.5V (E-temp. range)
ns 4.5V
≤ VCC ≤ 5.5V (Note 1)
≤ VCC ≤ 5.5V (E-temp. range) (Note 1)
2.5V
(SDA and SCL pins)
Write cycle time (byte or page) T
WC — 5ms
—
Endurance 1M — cycles 25°C, VCC = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined Tsp and Vhys specifications are due to new Schmitt trigger inputs which provide improved noise spike
suppression. This eliminates the need for a T
I specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on Microchip’s website: www.microchip.com.
2001 Microchip Technology Inc. DS21051H-page 3
Page 4
24LC04B/08B
FIGURE 1-2: BUS TIMING DATA
TF
THIGH
TLOW
SCL
SDA
IN
SDA
OUT
TSU:STA
TSP
TAA
THD:STA
THD:STA
THD:DAT TSU:DAT
2.0 FUNCTIONAL DESCRIPTION
The 24LC04B/08B supports a bi-directional 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is d efined as trans mitter and if receiving data, as rece iver. The bus has to be co ntroll ed by a
master device which generates the serial clock (SCL),
controls the bus access an d genera tes the START and
STOP conditions, while the 24LC04B/08B works as
slave. Both master and slave can operate as transmitter or receiver, but the maste r d evice d etermi nes which
mode is activated.
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data l ine while the clock lin e i s HI GH w ill be
interpreted as a START or STOP condition
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1 Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determine s a ST AR T condition. All
commands must be preceded by a START condition.
3.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
TR
TSU:STO
TAA
TBUF
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The ma ster devi ce m ust gener at e an ex tr a cloc k
pulse which is associated with this acknowledge bit.
Note: The 24LC04B/08B does not generate
any acknowledge bits if an internal programming cy cle is in progress.
The device that acknowledges, has to pull down the
SDA line during the ackn owledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the dat a line HIGH to en able
the master to generate the STOP condition.
DS21051H-page 4 2001 Microchip Technology Inc.
Page 5
24LC04B/08B
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A) (B) (D) (D) (A)(C)
SCL
SDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
2001 Microchip Technology Inc. DS21051H-page 5
Page 6
24LC04B/08B
3.6 Device Addressing
A control byte is the first byte received following the
start conditi on from t he mast er device. The contr ol byte
consists of a 4-bit control code, for the 24LC04B/08B
this is set as 1010 binary f or read an d write operations.
The next three bits of the control byte are the block
select bits (B2, B1, B0). B2 i s a ‘don' t care ’ fo r bo th th e
24LC04B and 24LC08B; B1 is a ‘don't care’ for the
24LC04B. They are us ed by the master dev ice to select
which of the two or four 256 w ord blocks of mem ory are
to be accessed. The se bit s are in effec t the most significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to ‘1’, a read operation is
selected and when set to ‘0’, a write operation is
selected. Following the start condition, the 24LC04B/
08B monitors the SDA bus checking the device type
identifier being transmitted. Upon a 1010 code, the
slave device outputs an acknowledge signal on the
SDA line. Depending on the state of the R/W
24LC04B/08B will select a read or write operation.
Operation
Read 1010 Block Address 1
Write 1010 Block Address 0
Control
Code
Block Select R/W
bit, the
FIGURE 3-2: CONTROL BYTE
ALLOCATION
START READ/WRITE
SLAVE ADDRESS
1010XB1B0
X = ’Don’t care’. B1 is ‘don’t care’ for 24LC04B.
R/W A
DS21051H-page 6 2001 Microchip Technology Inc.
Page 7
24LC04B/08B
4.0 WRITE OPERATION
4.1 Byte Write
Following the start condition from the master, the
device code (4 bits), the block address (3 bits) and the
R/W
bit, which is a logic LOW is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow after it has generated an acknowl edge bit during
the ninth clock cycl e. Therefore, th e next byte trans mitted by the master is the word address and will be written into the address pointer of the 24LC04B/08B. After
receiving another acknowledge signal from the
24LC04B/08B, the master devi ce will transmit the data
word to be written into the addre ssed memory location.
The 24LC04B/08B acknowledges again and the master generates a stop conditi on. This i nitiates th e internal
write cycle. During this time, the 24LC04B/08B will not
generate acknowledge signals (Figure 4-1).
4.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC04B/08B in the same
way as in a b yte wr i te. But instead of generating a sto p
condition, the master transmits up to 16 data bytes to
the 24LC04B/08B which are temporarily stored in the
on-chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwri tten. As w ith the by te writ e
operation, once the stop condition is received an internal write cycle will begin (Figure 4-2).
Note: Page write operations are limited to
writing bytes within a single physical
page, regardless of the number of
bytes actually being written. Physical
page boundaries start at addresses
that are integer multiples of the page
buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write command attempts to write across a physical page boundary, the result is that the
data wraps around to the beginning of
the current page (overwriting data previously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for
the application software to prevent
page write operations that would
attempt to cross a page boundary.
FIGURE 4-1: BYTE WRITE
S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
T
A
R
T
S P
CONTROL
BYTE
FIGURE 4-2: PAGE WRITE
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
CONTROL
R
BYTE
T
S P
WORD
ADDRESS (n)
A
C
K
S
WORD
ADDRESS
A
C
K
DATA (n) DATA (n + 15)
A
C
K
A
C
K
DATA (n + 1)
A
C
K
DATA
A
C
K
T
O
P
A
C
K
S
T
O
P
A
C
K
2001 Microchip Technology Inc. DS21051H-page 7
Page 8
24LC04B/08B
5.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can
be initiated immedi ately . This in volves the master s ending a start condition followed by the control byte for a
write command (R/W
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.
FIGURE 5-1: ACKNOWLEDGE
Initiate Write Cycle
Send Control Byte
= 0). If the device is still busy with
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Send Sta rt
with R/W
= 0
7.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W
slave address is set to a ’1’. There are th ree basic type s
of read operations: current address read, random read
and sequential read.
7.1 Current Address Read
The 24LC04B/08B contains an address counter that
maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n + 1. Upo n receip t of
the slave address wi th R /W
08B issues an acknowledge and transmits the 8-bit
data word. The master will not acknowledge the transfer but does generate a stop condition and the
24LC04B/08B discontinues transmission (Figure7-1).
bit set to ’1’, the 24LC04 B/
7.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operat io n, fi rst the w o rd ad dres s m ust
be set. This is d one by sending the word a ddress to th e
24LC04B/08B as part of a write operation. After the
word address is sent, the ma ster generate s a start condition following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then the master issues the control byte
again but with the R/W
08B will then issue an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the
24LC04B/08B discontinues transmission (Figure7-2).
bit set to a ’1’. The 24LC04B/
bit of the
Did Device
Acknowledge
(ACK = 0)?
Yes
Next
Operation
No
6.0 WRITE PROTECTION
The 24LC04B/08B can be used as a seria l ROM when
the WP pin is connected to V
inhibited and the entire memory will b e writ e-prote cted.
DS21051H-page 8 2001 Microchip Technology Inc.
CC. Program ming wi ll be
7.3 Sequential Read
Sequential reads are ini tiated in the sam e way as a random read except that after the 24L C04B/ 08B transm it s
the first data byte, the master issues an acknowledge
as opposed to a stop condition in a random read. This
directs the 24LC04B/08B to transmit the next sequentially addressed 8-bit word (Figure 7-3).
T o provid e sequential reads the 24LC04B/08B cont ains
an internal address pointer which is incremented by
one at the completion of each operation. This address
pointer allows the entire memor y content s to be serially
read during one operation.
7.4 Noise Protection
The 24LC04B/08B employs a VCC threshold detector
circuit which disabl es the internal e rase/write logi c if the
VCC is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Sch mitt trigger and filt er
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
Page 9
FIGURE 7-1: CURRENT ADDRESS READ
S
BUS ACTIVITY
MASTER
T
A
R
T
CONTROL
BYTE
24LC04B/08B
S
T
DATA (n)
O
P
SDA LINE
BUS ACTIVITY
SP
FIGURE 7-2: RANDOM READ
S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
T
CONTROL
A
BYTE
R
T
S P
FIGURE 7-3: SEQUENTIAL READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CONTROL
BYTE
DATA (n) DA TA (n + 1) DATA (n + 2) DATA (n + X)
A
C
K
WORD
ADDRESS (n)
A
C
K
A
C
K
A
C
K
A
C
K
S
T
A
R
T
S
A
C
K
CONTROL
BYTE
A
C
K
A
C
K
DATA (n)
N
O
A
C
K
S
T
O
P
N
O
A
C
K
S
T
O
P
P
N
O
A
C
K
8.0 PIN DESCRIPTIONS
8.1 SDA Serial Address/Data Input/
Output
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal. Therefore, t he SDA bus r equires a pullup resistor to V
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL LO W. Changes du ri ng S CL HI GH are
reserved for indicating the START and STOP conditions.
CC (typical 10KΩ for 100 kHz, 2 KΩ for
8.3 WP
This pin must be connected to either VSS or VCC.
If tied to V
SS, normal memory operation is enabled
(read/write the entire memory).
If tied to V
CC, WRITE operations are inhibited. The
entire memory will be write -protect ed. Read operati ons
are not affected.
This feature allows the user to use the 24LC04B/08B
as a serial ROM when WP is enabled (tied to V
CC).
8.4 A0, A1, A2
These pins are not used by the 24LC04B/08B. They
may be left floating or tied to either V
SS or VCC.
8.2 SCL Serial Clock
This input is u sed t o sy nchron ize the d ata trans fer fro m
and to the device.
2001 Microchip Technology Inc. DS21051H-page 9
Page 10
24LC04B/08B
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
8-Lead SOIC (150 mil)
XXXXXXXX
XXXXYYWW
NNN
8-Lead TSSOP
XXXX
XYWW
NNN
Example
24LC04B
XXXXXNNN
0025
Example
24LC04B
XXXX0025
NNN
Example
4L04
IYWW
NNN
8-Lead MSOP
XXXXX
YWWNNN
Legend: XX...X Customer specific information*
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Mic rochi p part num ber can not be ma rked on one line , it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
* Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
Example
4L4BI
YWWNNN
DS21051H-page 10 2001 Microchip Technology Inc.
Page 11
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
24LC04B/08B
n
E
β
eB
Number of Pins
Pitch
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
Dimension Limits MIN NOM MAX MIN NOM MAX
1
α
A
c
Units INCHES* MILLIMETERS
n
p
c
α
β
.008 .012 .015 0.20 0.29 0.38
A1
B1
B
88
.100 2.54
51015 51015
51015 51015
A2
L
p
2001 Microchip Technology Inc. DS21051H-page 11
Page 12
24LC04B/08B
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
Number of Pins
Pitch
Standoff §
Foot Angle
Lead Thickness
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
n
45×
c
β
n
p
A1
f
c
α
β
1
h
A
f
L
048048
A1
MILLIMETERSINCHES*Units
1.27.050
α
A2
MAXNOMMINMAXNOMMINDimension Limits
88
1.751.551.35.069.061.053AOverall Height
1.551.421.32.061.056.052A2Mold ed Packag e Thickness
0.250.180.10.010.007.004
6.206.025.79.244.237.228EOverall Width
3.993.913.71.157.154.146E1Molded Package Width
5.004.904.80.197.193.189DOverall Length
0.510.380.25.020.015.010hChamfer Distance
0.760.620.48.030.025.019LFoot Length
0.250.230.20.010.009.008
0.510.420.33.020.017.013BLead Width
1512015120
1512015120
DS21051H-page 12 2001 Microchip Technology Inc.
Page 13
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
n
B
1
24LC04B/08B
A
c
A1
f
β
A1
n
p
f
c
α
β
048048
Number of Pins
Pitch
Standoff §
Foot Angle
Lead Thickne ss
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
L
MILLIMETERS*INCHESUnits
0.65.026
α
A2
MAXNOMMINMAXNOMMINDimension Limits
88
1.10.043AOverall Height
0.950.900.85.037.035.033A2Molded Package Thickness
0.150.100.05.006.004.002
6.506.386.25.256.251.246EOverall Width
4.504.404.30.177.173.169E1Mold ed Packag e Width
3.103.002.90.122.118.114DMolded Package Length
0.700.600.50.028.024.020LFoot Length
0.200.150.09.008.006.004
0.300.250.19.012.010.007BLead Width
10501050
10501050
2001 Microchip Technology Inc. DS21051H-page 13
Page 14
24LC04B/08B
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
B
n 1
α
A
c
(F)
β
Units
Dimension Limits
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Pa ra meter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
n
p
A
A2
A1
E
E1
D
L
φ
c
B
α
β
MIN
.030
.002
.184
.114
.114
.016
0
.004
.010
L
INCHES
NOM
.026
.034
.193
.118
.118
.022
.037.035FFootprint (Reference)
.006
.012
φ
A1
8
.044
.038
.006
.200
.122
.122
.028
6
.008
.016
7
7
MINMAX
0.76
0.05
4.67
2.90
2.90
0.40
0.10
0.25
MILLIMETERS*
NOM
0.65
0.86
4.90
3.00
3.00
0.55
0
0.15
0.30
A2
MAX
8
1.18
0.97
0.15
.5.08
3.10
3.10
0.70
1.000.950.90.039
6
0.20
0.40
7
7
Drawing No. C04-111
DS21051H-page 14 2001 Microchip Technology Inc.
Page 15
24LC04B/08B
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used b y Mic rochip as a me ans to m ake
files and information easily available to customers. To
view the site, the use r must have access to the Intern et
and a web browser, such as Netscape
Explorer. Files are also available for FTP download
from our FTP site.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A variety of Micr ochip specific bu siness informatio n is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for prod ucts, D evelopment Systems,
technical information and more
• Listing of seminars and events
®
or Microsoft
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
®
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
2001 Microchip Technology Inc. DS21051H-page 15
Page 16
24LC04B/08B
READER RESPONSE
It is our intentio n t o p r ov ide yo u with the best documentati on pos si ble to en su re s uc ce ss ful us e of y ou r Mic r oc hip pro duct. If you wish to pro vide your comm ents on org ani zation , clar ity, subject m atter, and ways in which our d ocum entatio n
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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From:
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Would you like a reply? Y N
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Questions:
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2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
Technical Publications Manager
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24LC04B/08B
Literature Number:
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DS21051H
4. What additions to the data sheet do you think would enhance the structure and subject?
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DS21051H-page 16 2001 Microchip Technology Inc.
Page 17
24LC04B/08B
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX XXX
Device
Device: 24LC04B: VDD range 1.8V to 5.5V
Temperature
Range:
Package: P = Plastic DIP (300 mil body), 8-lead
Range
24LC04BT: (Tape and Reel)
24LC08B: V
24LC08BT: (Tape and Reel)
-= 0°C to+70°C
I=-40°C to+85°C
E= -40°C to+125°C
SN = Plastic SOIC (150 mil body),
ST = Plastic TSSOP (4.4mm body),
MS = MSOP, 8-lead
DD range 2.5V to 5.5V
8-lead
8-lead
PatternPackageTemperature
Examples:
a) 24LC04B–I/P Industrial Temp,
PDIP package, normal V
b) 24LC08B/SN Commercial Temp.,
SOIC package, normal V
DD limits.
DD limits.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences
and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of
the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2001 Microchip Technology Inc. DS21051H-page 17
Page 18
24LC04B/08B
NOTES:
DS21051H-page 18 2001 Microchip Technology Inc.
Page 19
24LC04B/08B
“All rights reserved. Copyright © 2001, Microchip
Technology Incorporated, USA. Information contained
in this publicat ion regarding d evice applica tions and the
like is intended through suggestion only and may be
superseded by updates . No rep resent ati on or wa rranty
is given and no liabil ity is assume d by Microch ip
Technology Incorpora ted with re spect to t he accuracy
or use of such information, or inf ringement of paten ts or
other intellectual property rights arising from such use
or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized
except with express written approval by Microchip. No
licenses are conveyed, implicitly or otherwise, under
any intellectual proper ty righ ts. The Mi croch ip log o and
name are registered trademarks of Microchip
Technology Inc. in the U.S.A. and other count ries. All
rights reserve d. Al l ot her trademarks mentioned herein
are the property of their respective companies. No
licenses are conveyed, implicitly or otherwise, under
any intellectual property rights.”
Trademarks
The Microchip name, logo, PIC, PICmicro,
PICMASTER, PICSTART, PRO MATE, K
EELOQ,
SEEV AL, MPLAB and The Embedded Contr ol
Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and
other countries.
Total Endurance, ICSP, In-Circuit Serial Programming,
FilterLab, MXDEV, microID, FlexROM, fuzzyLAB,
MPASM, MPLINK, MPLIB, PICDEM, ICEPIC,
Migratable Memory, FanSense, ECONOMONITOR,
Select Mode and microPort are trademarks of
Microchip Technology Incorporated in the U.S.A.
Serialized Quick Term Programming (SQ TP) is a
service mark of Microchip Technology Incorporated in
the U.S.A.
All other trademarks mentioned herein are property of
their respective compa ni es.
© 2001, Microchip Technology Incorporated, Prin ted in
the U.S.A., All Rights Reserved.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
2001 Microchip Technology Inc. DS21051H-page 19
®
8-bit MCUs, KEELOQ
®
code hopping
Page 20
M
WORLDWIDE SALES AND SERVICE
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01/30/01
All rights reserved. © 2001 Microchip Technology Incorporated. Printed in the USA. 4/01 Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by
updates. It is your respo nsibilit y to en sure t hat you r app licatio n mee ts with y our sp ecifica tions . No re presen tation or warra nty is given and n o liability is
assumed by Micro chip Technology Incorporate d with re spect t o the accur acy or use of such infor mation, o r infrin gemen t of patents or other intellectua l
property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property righ ts. The Microchip lo go and name are registered tradema rks of Microchip Technology Inc. in the U.S.A. and other countries. All rights
reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21051H-page 20 2001 Microchip Technology Inc.
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