Datasheet 227f200 Datasheet

Am29F200B

2 Megabit (256 K x 8-Bit/128 K x 16-Bit)
CMOS 5.0 Volt-only, Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ 5.0 V ± 10% for read and write operations

— Minimizes system level power requirements

■ Manufactured on 0.32 µm process technology

— Compatible with 0.5 µm Am29F200A device

■ High performance

— Access times as fast as 45 ns

■ Low power consumption

— 20 mA typical active read current (byte mode)
— 28 mA typical active read current for

(word mode)
— 30 mA typical program/erase current
—1 µA typical standby current

■ Sector erase architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte , and

three 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and

three 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:

A hardware method of locking a sector to

prevent any program or erase operations within

that sector

Sectors can be loc ked vi a progr amming equipm ent

T emporary Sector Unprotect feat ure allows code

changes in previously locked sectors

■ T op or bot tom boot bloc k configura tions av ailabl e

■ Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any
combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

■ Minimum 1,000,000 write/erase cycles guaranteed

■ 20-year data retention at 125°C

— Reliable operation for the life of the system

■ Package options

— 44-pin SO
— 48-pin TSOP
— Known Good Die (KGD)

(see publication number 21257)

■ Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply flash

— Superior inadvertent write protection

■ Data# Polling and Toggle Bit

— Detects program or erase cycle completion

■ Ready/Busy# output (RY/BY#)

— Hardware method for detection of program or

erase cycle completion

■ Erase Suspend/Erase Resume

— Supports reading data from a sector not

being erased

■ Hardware RESET# pin

— Resets internal state machine to the reading

array data

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication# 21526 Rev: B Amendment/+2
Issue Date: July 2, 1999

GENERAL DESCRIPTION

The Am29F200B is a 2 Mbit, 5.0 Volt-only Flash
memory organized as 262,144 bytes or 131,072 words .

The 8 bits of data appear on DQ0–DQ7; the 16 bits on
DQ0–DQ15. The Am29F200B is offered in 44-pin SO
and 48-pin TSOP packages. The device is also avail­able in Known Good Die (KGD) form. For more
information, refer to publication number 21257. This
device is designed to be programmed in-system with
the standard system 5.0 volt V

is not required for program or erase operations.

V

PP

The device can also be reprogrammed in standard
EPROM programmers.

This device is manufactured using AMD’s 0.32 µm
process technology, and offers all the features and
benefits of the Am29F200A, which was manufactured
using 0.5 µm process technology.

The standard device offers access times of 45, 50, 55,
70, 90, and 120 ns, allowing op eration of high-speed
microprocessors without wait states. To eliminate bus
contention the device has separate chip enable (CE#),
write enable (WE#) and output enable (OE#) controls.

The device requires only a single 5.0 volt power
supply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.

The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com­mands are written to the command regis ter using
standard micropr ocessor wri te timings. Register co n­tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto­matically times the program pulse widths and verifies
proper cell margin.

supply. A 12.0 volt

CC

Device erasure occurs by executing the erase
command sequence. This initiates the Embedded
Erase algorithm—an internal algorithm that automati­cally preprograms the array (if it is not already
programmed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.

The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6/
DQ2 (toggle) status bits. After a program or e rase
cycle has been completed, the device is ready to read
array data or accept another command.

The sector erase archite cture allo ws m emory sect ors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically in hibits write opera-

V

CC

tions during power transitions. The hardware sector
protection feature disables both program and erase

operations in an y combi nati on of t he sec tors o f memory.
This can be achieved via programming equipment.

The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True bac kg round er ase can thus be achieved.

The hardware RESET# pi n terminates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The system can place the device into the standby
mode. Po wer consumpt ion is grea tly reduc ed in this mode .

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective­ness. The device electrically erases all bi ts within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.

2 Am29F200B

PRODUCT SELECTOR GUIDE

Family Part Number Am29F200B

= 5.0 V ± 5% -45 -50

V

Speed Option

Max access time, ns (t
Max CE# access time, ns (t
Max OE# access time, ns (t

CC

= 5.0 V ± 10% -55 -70 -90 -120

V

CC

) 4550557090120

ACC

) 4550557090120

CE

) 303030303550

OE

BLOCK DIAGRAM

DQ0–DQ15

V

CC

V

SS

WE#

BYTE#

RESET#

CE#
OE#

A0–A16

A-1

RY/BY#

Buffer

State

Control

Command

Register

V

Detector

CC

RY/BY#

PGM Voltage

Generator

Timer

Erase Voltage

Generator

STB

Chip Enable

Output Enable

Logic

Y-Decoder

Address Latch

STB

Input/Output

Buffers

Data

Latch

Y-Gating

Cell MatrixX-Decoder

21526B-1

Am29F200B 3

CONNECTION DIAGRAMS

This device is also available in Known Good Die (KGD) form. Refer to publication number 21257 for
more information.

NC

RY/BY#

NC

A7
A6
A5
A4
A3
A2
A1
A0

CE#

V
OE#
DQ0
DQ8
DQ1
DQ9
DQ2

DQ10

DQ3

DQ11

SS

10
11
12
13
14
15
16
17
18
19
20
21
22

1
2
3
4
5
6
7
8
9

SO

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

21526B-2

4 Am29F200B

CONNECTION DIAGRAMS

This device is also available in Known Good Die (KGD) form. Refer to publication number 21257 for
more information.

A15
A14
A13
A12
A11
A10

A9

A8
NC
NC

WE#

RESET#

NC
NC

RY/BY#

NC
NC

A7

A6

A5

A4

A3

A2

A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

23
24

Standard TSOP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A16
BYTE#

V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4

V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#

V

SS
CE#
A0

21526B-3

A16

BYTE#

V

SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V

CC

DQ11

DQ3

DQ10

DQ2
DQ9
DQ1
DQ8
DQ0
OE#

V

SS

CE#

A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

23
24

Reverse TSOP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
NC
A7
A6
A5
A4
A3
A2
A1

21526B-4

Am29F200B 5

PIN CONFIGURATION

A0–A16 = 17 addresses
DQ0–DQ14 = 15 data inputs/outputs
DQ15/A-1 = DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

LOGIC SYMBOL

17

A0–A16

16 or 8

DQ0–DQ15

(A-1)

BYTE# = Selects 8-bit or 16-bit mode
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy output

= +5.0 V single power supply

V

CC

(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)

V

SS

= Device ground

NC = Pin not connected internally

CE#
OE#

WE#
RESET#
BYTE# RY/BY#

21526B-5

6 Am29F200B

ORDERING INFORMATION
Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:

Am29F200B T -45 E C

OPTIONAL PROCESSING

Blank = Standard Processing
B=Burn-In
(Contact an AMD representative for more information)

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)
I = Industrial (–40

E = Extended (–55

PACKAGE TY PE

E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044
This device is also available in Known Good Die (KGD) form. See publication number

21257 for more information.

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top sector
B = Bottom sector

°C to +85°C)

°C to +125°C)

)

AM29F200BT-45,
AM29F200BB-45

AM29F200BT-50,
AM29F200BB-50

AM29F200BT-55,
AM29F200BB-55

AM29F200BT-70,
AM29F200BB-70

AM29F200BT-90,
AM29F200BB-90

AM29F200BT-120,
AM29F200BB-120

DEVICE NUMBER/DESCRIPTION

Am29F200B
2 Megabit (256 K x 8-Bit128 K x 16-Bit) CMOS Flash Memory

5.0 Volt-only Program and Erase

Valid Combinations

EC, EI, FC, FI, SC, SI

EC, EI, EE,

FC, FI, FE,
SC, SI, SE

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

Valid Combinations

Am29F200B 7

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory loca­tion. The register is composed of l atches that store the
commands, along with the address and data informa­tion needed to execute the command. The contents of

Table 1. Am29F200B Device Bus Operations

the register serve as inputs to the i nternal state
machine. The state machine outputs dictate the func­tion of the device. The appropriate device bus
operations table lists the inputs and control levels
required, and the resulting output. The following sub­sections describe each of these operations in furthe r
detail.

DQ8–DQ15

OUT

D

D

BYTE#

= V

IH

High-Z
High-Z

IN

IN

X

BYTE#

Operation CE# OE# WE# RESET# A0–A16 DQ0–DQ7

Read L L H H A
Write L H L H A
CMOS Standby V

TTL Standby H X X H X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Hardware Reset X X X L X High-Z High-Z High-Z
Temporary Sector Unprotect

(See Note)

Legend:

L = Logic Low = V

Note: See the sections Sector Group Protection and Temporary Sector Unprotect for more information.

, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, D

IL

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the by te or word configur a­tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con­trolled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–D Q7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at V
BYTE# pin deter mines whether the device outputs
array data in words or bytes.

The internal state machine is set for reading arr ay data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the mem ory

. On x16 (word-wide) devices, the

IH

± 0.5 V X X VCC ± 0.5 V X High-Z High-Z High-Z

CC

XXX V

ID

content occurs during the power transition. No
command is neces sary in this mode to obtain ar ray
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.

See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica­tions and to the Read Operations Timings diagram for
the timing waveforms. I
table represents the active current specification for
reading array data.

Writing Commands/Command Sequences

. CE# is the power

IL

To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

, and OE# to VIH.

IL

On x16 (word-wide) devices, for program operations,
the BYTE# pin determines whether the de vice accepts
program data in bytes or wor ds. Refer to “Word/Byte
Configuration” for more information.

IN

IN

A

IN

D

OUT

D

IN

D

IN

= Data Out, AIN = Address In

OUT

in the DC Characteristics

CC1

= V

D

IL

8 Am29F200B

An erase operation can erase one sect or, multiple sec­tors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.

A “sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini­tions” section for details on erasing a sector or the
entire chip, or suspending/resuming the erase
operation.

After the system writes the autoselect command
sequence, the devi ce enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Sta ndard read cycle timings apply
in this mode. Refer to the “Autoselect Mode” and
“Autoselect Command Sequence” sections for more
information.

in the DC Characteristics table represents the

I

CC2

active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I

CC

read specifications apply. Refer to “Write Operation
Status” for more information, and to each AC Charac­teristics section in the appropriate data sheet f or t iming
diagrams.

Standby Mode

When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is great ly reduc ed, and the
outputs are placed in the high impedance state, inde­pendent of the OE# input.

The device enters the CMOS standb y mode when CE#
and RESET# pins are both held at V
that this is a more restrict ed voltage range than V
The device enters the TTL standby mode when CE#
and RESET# pins are both held at V
requires standard access time (t
when the device is in either of these s tandby modes,
before it is ready to read data.

The device also enters the standby mode wh en the
RESET# pin is driven low. Refer to the next section,
“RESET#: Hardware Reset Pin”.

± 0.5 V. (Note

CC

. The device

IH

) for read access

CE

IH

If the device is deselected during erasure or program­ming, the device draws active current until the
operation is completed.

In the DC Characteristics tables, I

represents the

CC3

standby current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardw are method of reset­ting the device to readin g arr ay data. When the system
drives the RESET# pin low for at least a period of t
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration o f the RESET#
pulse. The device also resets the internal state
machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to
ensure data integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V

, the device enters

IL

the TTL standby mode; if RESET# is held at V

0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm­ware from the Flash memory.

If RESET# is asserted during a program or erase oper­ation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t

(not during Embe dded Algo-

READY

rithms). The system can read data t
RESET# pin returns to V

Refer to the AC Characteristics tables for RESET#

.)

parameters and timing diagram.

.

IH

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high imped­ance state.

after the

RH

SS

RP

,

±

Am29F200B 9

Table 2. Am29F200T Top Boo t Block Sector Address Table

Sector Size

(Kbytes/

Sector A16 A15 A14 A13 A12

SA0 0 0 X X X 64/32 00000h–0FFFFh 00000h–07FFFh
SA1 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh
SA2 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh
SA3 1 1 0 X X 32/16 30000h–37FFFh 18000h–1BFFFh
SA4 1 1 1 0 0 8/4 38000h–39FFFh 1C000h–1CFFFh
SA5 1 1 1 0 1 8/4 3A000h–3BFFFh 1D000h–1DFFFh
SA6 1 1 1 1 X 16/8 3C000h–3FFFFh 1E000h–1FFFFh

Kwords)

Address Range (in hexadecim al )

(x8)

Address Range

Address Range

(x16)

Table 3. Am29F200B Bottom Boot Block Sector Address Table

Sector Size

(Kbytes/

Sector A16 A15 A14 A13 A12

SA0 0 0 0 0 X 16/8 00000h–03FFFh 00000h–01FFFh
SA1 0 0 0 1 0 8/4 04000h–05FFFh 02000h–02FFFh
SA2 0 0 0 1 1 8/4 06000h–07FFFh 03000h–03FFFh
SA3 0 0 1 X X 32/16 08000h–0FFFFh 04000h–07FFFh

Kwords)

Address Range (in hexadecim al )

(x8)

Address Range

Address Range

(x16)

SA4 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh
SA5 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh
SA6 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh

Note for Tables 2 and 3: Address range is A16:A-1 in byte mode and A16:A0 in word mode. See the “Word/Byte Configuration”
sectionfor more information.

Autoselect Mode

The autoselect mode provides manufacturer and
device identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.

When using programming equipment, the autoselect
mode requires V

(11.5 V to 12.5 V) on address pin

ID

A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In addi­tion, when verifying sector protection, the sector

address must appear on the appropriate highest order
address bits. Refer to the corresponding Sector
Address Tables. The Command D efinitions table
shows the remaining address bits that are don’t care.
When all necessary bits have been set as required, the
programming equipment may then read the corre­sponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Defini­tions table. This method does not require V

. See

ID

“Autoselect Command Sequence” for details on using
the autoselect mode.

10 Am29F200B

Table 4. Am29F200B Autoselect Codes (High Voltage Method)

Description Mode CE# OE# WE#

A16

to

A12

A11

to

A10 A9

A8

to

A7 A6

A5

to

A2 A1 A0

DQ8

to

DQ15

DQ7

to

DQ0

Manufacturer ID: AMD L L H X X V
Device ID:

Am29F200B
(Top Boot Block)

Device ID:
Am29F200B
(Bottom Boot Block)

Sector Protection Verification L L H SA X V

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Word L L H

XXVIDXLXLH

Byte L L H X 51h

Word L L H

XXVIDXLXLH

Byte L L H X 57h

XLXLL X 01h

ID

XLXHL

ID

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sect or. The hard­ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.

Sector protection/unprotection must be implemented
using programming equipment. The procedure
requires a high voltage (V
control pins. Details on this method are provided in a
supplement, publication number 20551. Contact an
AMD representative to obtain a cop y of the appropriate
document.

) on address pin A9 and the

ID

22h 51h

22h 57h

X

X

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

ID

IH

01h

(protected)

00h

(unprotected)

The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.

It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.

Temporary Sector Unprotect

This feature allows temporary unpr otection of previ­ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the
RESET# pin to V
tected sectors can be programmed or erased by
selecting the sector addresses. Once V
from the RESET# pin, all the previously protected
sectors are protected again. Figure 1 shows the algo­rithm, and the Temporary Se ctor Unprotect diagram
(Figure 18) shows the timing waveforms, for this
feature.

. During this mode, former ly pro-

ID

is removed

ID

Am29F200B 11

Temporary Sector

Unprotect

Completed (Note 2)

21526B-6

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once
again.

Figure 1. Temporary Sector Unprotect Operati on

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi­nitions table). In addition, the following hardware data
protection measures pre vent a ccidental eras ure or pro-

gramming, which might otherwise be caused by
spurious system level signals during V

power-up and

CC

power-down transitions, or from system noise.

Low V

When V
accept any write cycles. This protects data during V

Write Inhibit

CC

is less than V

CC

, the device does not

LKO

CC

power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V

. The system must provide the

LKO

CC

proper signals to the control pins to prevent uninten­tional writes when V

is greater than V

CC

LKO

.

COMMAND DEFINITIONS

Writing specific address and data commands or
sequences into the command register initiates device
operations. The Command Definitions tab le defines the
valid register command sequences. Writing incorrect

address and data values or writing them in the
improper sequence resets the device t o reading array

data.
All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after comp leting an Embedded Program o r
Embedded Erase algorithm.

After the device accepts an Er ase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor­mation on this mode.

must

The system
enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.

See also “Requirements for Reading Arr a y Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-

issue the reset command to re-

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

, CE# = VIH or WE# = VIH. To initiate a write cycle,

V

IL

CE# and WE# must be a logical zero while OE# is a
logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during power up , the

IL

device does not accept commands on the rising edge
of WE#. The internal state mac hine is automatically
reset to reading array data on power-up.

ters, and Read Operation Timings diagram shows the
timing diagram.

Reset Command

Writing the reset co mmand to the device resets the
device to reading array data. Address bits are don’t
care for this command.

The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins . This resets the device t o reading
array data. Once erasure begins, however, the device
ignores reset commands until the operation is
complete.

The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.

The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, t he reset c ommand

must

be written to return to reading array data (also applies
to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to
reading array data (also applies during Erase
Suspend).

Autoselect Command Sequence

The autoselect c ommand sequenc e allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an a lternative to
that shown in the Autoselect Codes (High Voltage

12 Am29F200B

Method) table, which is intended for PROM program­mers and requires V

on address bit A9.

ID

The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.

A read cycle at address XX00h retrieves the manufac­turer code. A read cycle at address XX01h in word
mode (or 02h in byte mode) returns the device code. A
read cycle containing a sector address (SA) and the
address 02h in word mod e (or 04h in byte mode)
returns 01h if that s ector is protected, or 00h if it is
unprotected. Refer to the Sector Address tables for
valid sector addresses.

The system must write the reset command to exit the
autoselect mode and return to reading array data.

Embedded

Program

algorithm

in progress

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

Yes

No

Word/Byte Program Command Sequence

The system may program the device by byte or word,
on depending on the state of the BYTE# pin. Progr am­ming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock
write cycles, follo wed by t he program set-up command.
The program address and data are written next, which
in turn initiate the Embedded Program algorithm. The

not

system is
ings. The device automatically provides internally
generated program pulses and verify the programmed
cell margin. The Command Definitions take shows the
address and data requirements for the byte program
command sequence.

When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using

DQ7, DQ6, or RY/BY#. See “Write Ope ration Status”
for information on these status bits.

Any commands written to the device during the
Embedded Program Algorithm are ignored. Not e that a
hardware reset immediately terminates the program­ming operation. The program command sequence
should be reinitiated once the device has reset to
reading array data, to ensure data integrity.

Programming is allowed in any sequence an d across
sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the op eration was suc­cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.

required to provide further controls or tim-

Increment Address

Note: See the appropriate Command Definitions table for
program command sequence.

No

Last Address?

Yes

Programming

Completed

21526B-6

Figure 2. Program Operation

Chip Erase Command Sequence

Chip erase is a six-bu s-cycle oper ation. The chip er ase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase

not

algorithm. The device does
preprogram prior to erase. The Embedded Erase algo­rithm automatically preprograms and verifies the entire
memory for an all zero data patter n prior to electr ical
erase. The system is not required to provide any con­trols or timings during these operations. The Command
Definitions table shows the address and data require­ments for the chip erase command sequence.

Any commands written to the chip during the
Embedded Erase algorithm are ignored. Note that a
hardware reset during the chip eras e operat ion imme­diately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure
data integrity.

require the system to

Am29F200B 13

The system can determine the status of the erase oper-

ation by using DQ7, DQ6, DQ2, or RY/BY#. See “Write
Operation Status” for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading arra y data and addresses are
no longer latched.

Figure 3 illustrates the algorithm for the erase opera­tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters , and to the Chip/Sector
Erase Operation Timings for timing waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the
sector erase command sequence.

not

The device does
the memory prior to erase. The Embedded Erase algo­rithm automatically programs and verifies the sector f or
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.

After the command sequence is written, a sector erase
time-out of 50 µs begi ns. During the time-out per iod,
additional sector addresses and sector erase com­mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of
sectors may be from one sector to all sectors . The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recom­mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the las t Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not m onitor DQ3. Any

command other than Sector Erase or E rase
Suspend during the time-out period resets the
device to reading array data. The system must

rewrite the command sequence and any additiona l
sector addresses and commands.

The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sec tor Erase
Timer” section.) The time-out be gins from the rising
edge of the final WE# pulse in the command sequence .

Once the sector erase operation has begun, onl y the
Erase Suspend command is valid. All other commands
are ignored. Note th at a hardware reset during the
sector erase operation immedia tely terminates the
operation. The Sec tor Erase command sequence

require the system to preprogram

should be reinitiated onc e the device has returned to
reading array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the
device returns to reading arra y data and addr esses are
no longer latched. The system can determi ne the
status of the erase operation b y using DQ7, DQ6, DQ2,
or RY/BY#. Refer to “Write Operation Status” for infor­mation on these status bits.

Figure 3 illustrates the algorithm for the erase opera­tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
the Sector Erase Operations Timing diagr am for timing
waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase c ommand sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo­rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation.
Addresses are “don’t-cares” wh en writing the Erase
Suspend command.

When the Erase Suspend command is written during a
sector erase operation, the de vice requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter­minates the time-out period and suspends the erase
operation.

After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasu re. (The de vice “er ase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended
sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to
determine if a sector is actively erasing or is eras e-sus­pended. See “Write Operation Status” for information
on these status bits.

After an erase-suspended program operation is com­plete, the system c an once again r ead arra y d ata within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper­ation. See “Write Operation Status” for more
information.

The system may also write the autoselect command
sequence when the device is in the Erase Suspend

14 Am29F200B

mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command Sequence”
for more information.

The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operat ion. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the
device has resumed erasing.

START

Write Erase

Command Sequence

Data Poll

from System

No

Data = FFh?

Erasure Completed

Embedded
Erase
algorithm
in progress

Yes

21526B-7

Notes:

1. See the appropriate Command Definitions table for erase
command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 3. Erase Operation

Am29F200B 15

Table 5. Am29F200B Command Definitions

Command

Sequence

(Note 1)

Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0

Manufacturer ID

Device ID,
Top Boot Block

Device ID,
Bottom Boot Block

Autoselect (Note 8)

Sector Protect Verify
(Note 9)

Program

Chip Erase

Sector Erase
Erase Suspend (Note 10) 1 XXX B0

Erase Resume (Note 11) 1 XXX 30

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA AAA 555 AAA

Word

Byte AAA 555 AAA AAA 555

First Second Third Fourth Fifth Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Cycles

555

4

4

4

4

4

6

6

555

555

555

555

555

555

AA

AA

AA

AA

AA

AA

AA

2AA

2AA

2AA

2AA

2AA

2AA

2AA

55

55

55

55

55

55

55

Bus Cycles (Notes 2–5)

555

555

555

555

555

555

555

90 X00 01

X01 2251

90

X02

X01 2257

90

X02

(SA)

X02

90

(SA)

X04

A0 PA PD

555

80

555

80

51

57
XX00
XX01

00

01

AA

AA

2AA

2AA

555

55

55 SA 30

10

Legend:

X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles
are write operations.

4. Data bits DQ15–DQ8 are don’t cares for unlock and
command cycles.

5. Address bits A16–A11 are don’t cares for unlock and
command cycles, unless SA or PA required.

6. No unlock or command cycles required when reading array
data.

7. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status da ta).

PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A16–A12 uniquely select any sector.

8. The fourth cycle of the autoselect command sequence is a
read cycle.

9. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.

10. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.

11. The Erase Resume command is valid only during the Erase
Suspend mode.

16 Am29F200B

WRITE OPERATION STATUS

The device provides several bits to determine the
status of a write operation: DQ2, DQ3, DQ5, DQ6,
DQ7, and RY/BY#. Table 1 and the following subsec­tions describe the func tions of these bits. DQ7, RY/
BY#, and DQ6 each offer a method for determining
whether a program or erase oper ation is c omplete or in
progress. These three bits are discussed first.

Table 1 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.

START

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in progress
or completed, or wh ether the device is in Erase Sus­pend. Data# Polling is valid after the rising edge of the
final WE# pulse in the program or erase command
sequence.

During the Em bedded Program algor ithm, the device
outputs on DQ7 the complement of the datum pro­grammed to DQ7. Thi s DQ7 status also appl ies to
programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address f alls within a
protected sector, Data# Polling on DQ7 is active for
approximately 2 µs, then the device returns to reading
array data.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” o r
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status
information on DQ7.

No

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

No

FAIL

Yes

Yes

PASS

After an erase command sequence is written, if all
sectors selected for erasing are protected, Data#
Polling on DQ7 is active for approximately 100 µs, then
the device returns to reading array data. If not all
selected sectors are protected, the Embedd ed Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected.

When the system detects DQ7 has changed from the
complement to true data, it can read va lid data at DQ7–
DQ0 on the

following

read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is assert ed low. The Data#
Polling Timings (During Embedded Algorithms) figure
in the “AC Characteristics” section illustrates this.

Am29F200B 17

Notes:

1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

21526B-8

Figure 4. Data# Polling Algorithm

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied together in parallel
with a pull-up resistor to V

If the output is low (Busy ), the de vice is activ ely er asing
or programming. (T his includes programming in the
Erase Suspend mode.) If th e output is high (Ready) ,
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.

Table 1 shows the outputs for RY/BY#. The timing dia­grams for read, reset, program, and erase shows the
relationship of RY/BY# to other signals.

CC

.

DQ6: Toggle Bit I

Toggle Bi t I on DQ6 indicates w hether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase
operation), and during the sector erase time-out.

The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences
between DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi­cates whether a par ticular sect or is actively erasing
(that is, the Embedded Erase algo rithm is in pro gress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of t he final WE# pulse in
the command sequence.

DQ2 toggles w hen the system reads at addresses
within those sector s that have been selected for era­sure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus­pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era­sure. Thus, both status bits are required for sector and
mode information. Refer to Table 1 to compare output s
for DQ2 and DQ6.

During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle. (The system may us e either OE#
or CE# to control the read cycles.) When the operation
is complete, DQ6 stops toggling.

After an erase command sequence is written, if all
sectors selected for er asing are protected, DQ6 toggles
for appro ximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.

The system can use DQ6 and DQ2 together to deter­mine whether a sector is actively erasing or is erase­suspended. When the device is activ ely erasing (that is ,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a pro tected sector,

DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.

DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.

Figure 5 shows the toggle bit algorithm in flowchar t
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows t he dif­ferences between DQ2 and DQ6 in graphical f orm.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 5 for the following discussion. Whe n­ever the system initially begins readin g toggle bit
status, it must read DQ7–DQ0 at least t wice in a row to
determine whether a toggle bit is toggling. Typically, a
system would note and store the value of the t oggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has com­pleted the program or eras e operation. The system can
read array data on DQ7–DQ0 o n the following read
cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggli ng, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog­gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully comp leted the
program or erase operation. If it is still toggling, the
device did not complete the oper ation successfully, and

18 Am29F200B

the system must write the reset command to return to
reading array data.

The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The system may contin ue to monitor the
toggle bit and DQ5 through successive read cy cles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 5).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure
condition that indicates the prog ram or er ase cycle was
not successfully completed.

of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been
accepted. Table 1 shows the outputs for DQ3.

START

Read DQ7–DQ0

Read DQ7–DQ0

(Note 1)

The DQ5 failure condition may appear if the system
tries to program a “1” to a location that i s previously pro­grammed to “0.” Only an era se operation can change

a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, t he system must issue the

reset command to return the device to reading array
data.

DQ3: Sector Erase Timer

After writing a sector erase comm and sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi­tional sectors are selected for erasure, the entire time­out also applies after each additional sector erase com­mand. When the time-out is com plete, DQ3 switches
from “0” to “1.” The system may ignore DQ3 if the
system can guarantee that the ti me between add itional
sector erase commands will always be less than 50 µs.
See also the “Sector Erase Command Sequence”
section.

After the sector erase command sequence is written,
the system should read the status on DQ7 (Data#
Polling) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.
If DQ3 is “1”, the internally controlled erase cycle has
begun; all further commands (other than Erase Sus­pend) are ignored until the er ase operation is complete .
If DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the comm and has been
accepted, the system software should ch eck the s tatus

Toggle Bit

= Toggle?

Yes

No

Notes:

1. Read toggle bit twice to determine whether or not it is
toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

No

(Notes
1, 2)

No

Program/Erase

Operation Complete

21526B-9

Figure 5. Toggle Bit Algorithm

Am29F200B 19

Table 1. Write Operation Status

DQ7

Standard
Mode

Erase
Suspend
Mode

Operation

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Reading within Erase

Suspended Sector
Reading within Non-Erase

Suspended Sector
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

(Note 1) DQ6

1 No toggle 0 N/A Toggle 1

Data Data Data Data Data 1

Notes:

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

DQ5

(Note 2) DQ3

DQ2

(Note 1) RY/BY#

20 Am29F200B

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground

(Note 1) . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

V

CC

A9, OE#, and

RESET# (Note 2). . . . . . . . . . . .–2.0 V to +12.5 V

All other pins (Note 1) . . . . . . . . .–0.5 V to +7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, i nput or I/O pins may overshoot V
to –2.0 V for periods of up to 20 ns. See Figure 6.
Maximum DC voltage on input or I/O pin s is V
During voltage transitions, input or I/O pins may overshoot
to V

+2.0 V for periods up to 20 ns. See Figure 7.

CC

2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may overshoot V
to 20 ns. See Figure 6. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to +13.5 V for periods
up to 20 ns.

3. No more than on e output may be shor te d to ground at a
time. Duration of the short circuit should not be greater
than one second.

Note: Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the op­erational sections of this data sheet is not implied. Exposure
of the device to absolute maximum rating conditions for ex­tended periods may affect device reliability.

to –2.0 V for periods of up

SS

CC

SS

+0.5 V.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T

Industrial (I) Devices

Ambient Temperature (T

Extended (E) Devices

Ambient Temperature (T

VCC Supply Voltages

for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V

V

CC

for± 10% devices. . . . . . . . . . . . +4.5 V to +5.5 V

V

CC

Note: Operating ranges define those limits between which
the functionality of the device is guaranteed.

) . . . . . . . . . . .0°C to +70°C

A

) . . . . . . . . .–40°C to +85°C

A

) . . . . . . . .–55°C to +125°C

A

20 ns

+0.8 V

–0.5 V
–2.0 V

20 ns

20 ns

Figure 6. Maximum Negative Overshoot

Waveform

20 ns

V

CC

+2.0 V

V

CC

+0.5 V

2.0 V
20 ns

21526B-10

20 ns

Figure 7. Maximum Posi tive Overshoot

Waveform

Am29F200B 21

21526B-11

DC CHARACTERISTICS
TTL/NMOS Compatible

Parameter

Symbol Parameter Descri ptio n Test Conditions Min M ax Unit

V

I

I

I

CC1

I

CC2

I

CC3

V
V

V

V

V

I

LI

LIT

LO

IL

IH

ID

OL

OH

LKO

Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA

A9, OE#, RESET# Input Load
Current

Output Leakage Current V

VCC = VCC Max,
A9, OE

OUT

VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = V

VCC Active Program/Erase Current
(Notes 2, 3, 4)

CE

# = V

VCC Standby Current (Note 2) VCC = VCC Max, CE# = VIH, OE# = V
Input Low Voltage –0.5 0.8 V
Input High Voltage 2.0 VCC + 0.5 V
V oltage for Autoselect and Temporary

Sector Unprotect

V

CC

Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V
Output High Voltage IOH = –2.5 mA, VCC = VCC Min 2.4 V
Low VCC Lock-Out Voltage 3.2 4.2 V

Notes:

1. The I

2. Maximum I

3. I

current is typically less than 2 mA/MHz, with OE# at VIH.

CC

specifications are tested with VCC = V

CC

active while Embedded Program or Erase Algorithm is in progress.

CC

CCmax

4. Not 100% tested.

#, RESET# = 12.5 V

50 µA

= VSS to VCC, VCC = VCC Max ±1.0 µA

Byte 40

mA

, OE# = V

IL

IH

IH

Word 50

60 mA

IH

1.0 mA

= 5.0 V 11.5 12.5 V

.

22 Am29F200B

DC CHARACTERISTICS (Continued)
CMOS Compatible

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

I

LI

I

LIT

I

LO

I

CC1

I

CC2

I

CC3

V

IL

V

IH

V

ID

V

OL

V

OH1

V

OH2

V

LKO

Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA

A9, OE#, RESET# Input
Load Current

Output Leakage Current V
VCC Active Read Current

(Notes 1, 2)
VCC Active Program/Erase

Current (Notes 2, 3, 4)
VCC Standby Current

Note (Note 5)

VCC = VCC Max;
A9, OE

#, RESET# = 12.5 V

= VSS to VCC, VCC = VCC Max ±1.0 µA

OUT

CE# = VIL, OE# = V

CE

# = V

, OE# = V

IL

CE# = VCC ± 0.5 V, OE# = V

Input Low Voltage –0.5 0.8 V
Input High Voltage 0.7 x V
Voltage for Autoselect and

Temporary Sector Unprotect

V

= 5.0 V 11.5 12.5 V

CC

Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V

IOH = –2.5 mA, VCC = VCC Min 0.85 V

Output Low Voltage

IOH = –100 µA, VCC = VCC Min VCC – 0.4 V

Low VCC Lock-Out Voltage 3.2 4.2 V

Notes:

1. The I

2. Maximum I

3. I

current listed is typically less than 2 mA/MHz, with OE# at VIH.

CC

specifications are tested with VCC = V

CC

active while Embedded Program or Erase Algorithm is in progress.

CC

CCmax

4. Not 100% tested.

5. I

for extended temperature is 20 µA max (>+85

CC3

°

C).

50 µA

Byte 20 40

IH

Word 28 50

IH

IH

CC

CC

30 50 mA

15µA

VCC + 0.3 V

mA

V

.

Am29F200B 23

TEST CONDITIONS

Device

Under

Test

C

L

6.2 kΩ

5.0

2.7 kΩ

Table 6. Test Specifications

-45, -50,

Test Condition

Output Load 1 TTL gate
Output Load Capacitance, C

(including jig capacitance)
Input Rise and Fall Times 5 20 ns
Input Pulse Levels 0.0–3.0 0.45–2.4 V

-55

L

30 100 pF

All

others Unit

Note:

Diodes are IN3064 or equivalents.

Figure 8. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

21526B-12

Input timing measurement
reference levels

Output timing measurement
reference levels

Steady

Changing from H to L

Changing from L to H

1.5 0.8, 2.0 V

1.5 0.8, 2.0 V

24 Am29F200B

KS000010-PAL

AC CHARACTERISTICS
Read Operations

Parameter

JEDEC Std Test Setup -45 -50 -55 -70 -90 -120 Unit

t

AVAV

t

AVQVtACC

t

ELQVtCE

t

GLQVtOE

t

EHQZtDF

t

GHQZtDF

Description

t

Read Cycle Time (Note 1) Min 45 50 55 70 90 120 ns

RC

Address to Output Delay

Chip Enable to Output Delay OE# = V
Output Enable to Output Delay

(Note 1)
Chip Enable to Output High Z

(Note 1)
Output Enable to Output High Z

(Note 1)
Output Enable

Hold Time

t

OEH

(Note 1)

Read Min 0 ns
Toggle and

Data# Polling

CE# = V
OE# = V

IL

Max4550557090120ns

IL

Max4550557090120ns

IL

Max303030303550ns

Max202020202030ns

Max202020202030ns

Min 10 ns

Speed Options

Output Hold Time From

t

AXQXtOH

Addresses, CE# or OE#,

Min 0 ns

Whichever Occurs First (Note 1)

Notes:

1. Not 100% tested.

2. See Figure 8 and Table 6 for test specifications

Addresses

CE#

OE#

WE#

Outputs

RESET#

RY/BY#

0 V

t

RC

Addresses Stable

t

ACC

t

OE

t

OEH

t

CE

HIGH Z

Output Valid

Figure 9. Read Operations Timings

t

OH

t

DF

HIGH Z

Am29F200B 25

AC CHARACTERISTICS
Hardware Reset (RESET#)

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

READY

READY

t

RP

t

RH

t

RB

RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)

RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)

RESET# Pulse Width Min 500 ns
RESET# High Time Before Read (See Note) Min 50 ns
RY/BY# Recovery Time Min 0 ns

t

t

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

Max 20 µs

Max 500 ns

t

RH

t

RP

t

Ready

Reset Timings NOT during Embedded Algorithms

RY/BY#

CE#, OE#

RESET#

Reset Timings during Embedded Algorithms

t

Ready

t

RP

Figure 10. RESET# Timings

t

RB

21526B-13

26 Am29F200B

AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)

Parameter Speed Options

JEDEC Std Description -45 -50 -55 -70 -90 -120 Unit

t

ELFL/tELFH

t

FLQZ

t

FHQV

CE# to BYTE# Switching Low or High Max 5 ns
BYTE# Switching Low to Output HIGH Z Max 20 20 20 20 20 30 ns
BYTE# Switching High to Output Active Max 45 50 55 70 90 120 ns

CE#

OE#

BYTE#

BYTE#

Switching

DQ0–DQ14

ELFL

Data Output

(DQ0–DQ14)

Data Output

(DQ0–DQ7)

t

from word

to byte

mode

DQ15/A-1

t

ELFH

t

FLQZ

DQ15

Output

Address

Input

BYTE#

BYTE#

Switching

from byte

DQ0–DQ14

to word

mode

DQ15/A-1

Figure 11. BYTE# Timings for Read Operations

CE#

WE#

BYTE#

Note:

Refer to the Erase/Program Operations table for t

Figure 12. BYTE# Timings for Write Operations

Data Output
(DQ0–DQ7)

The falling edge of the last WE# signal

t

SET

(tAS)

and tAH specifications.

AS

Address

Input

t

FHQV

t

HOLD

Data Output

(DQ0–DQ14)

DQ15

Output

21526B-14

(tAH)

21526B-15

Am29F200B 27

AC CHARACTERISTICS
Erase/Program Operations

Parameter Speed Options

JEDEC Std Description -45 -50 -55 -70 -90 -120 Unit

t

AVAV

t

AVWL

t

WLAX

t

DVWH

t

WHDX

t

GHWL

t

ELWL

t

WHEH

t

WLWH

t

WHWL

t

WHWH1tWHWH1

t

WHWH2tWHWH2

t

WC

t

AS

t

AH

t

DS

t

DH

t

OES

t

GHWL

t

CS

t

CH

t

WP

t

WPH

t

VCS

t

RB

t

BUSY

Write Cycle Time (Note 1) Min 45 50 55 70 90 120 ns
Address Setup Time Min 0 ns
Address Hold Time Min 45 45 45 45 45 50 ns
Data Setup Time Min 25 25 25 30 45 50 ns
Data Hold Time Min 0 ns
Output Enable Setup Time Min 0 n s
Read Recovery Time Before Write

(OE# High to WE# Low)

Min 0 ns

CE# Setup Time Min 0 ns
CE# Hold Time Min 0 ns
Write Pulse Width Min 30 30 30 35 45 50 ns
Write Pulse Width High Min 20 ns

Programming Operation
(Note 2)

Byte Typ 7

µs

Word Typ 12
Sector Erase Operation (Note 2) Typ 1 sec
VCC Setup Time (Note 1) Min 50 µs
Recovery Time from RY/BY# Min 0 ns
Program/Erase Valid to RY/BY# Delay Min 30 30 30 30 35 50 ns

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

28 Am29F200B

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

t

WC

Addresses

555h

CE#

t

GHWL

OE#

t

WP

WE#

t

CS

t

DS

t

DH

Data

A0h

RY/BY#

t

VCS

V

CC

Notes:

1. PA = program address, PD = program data, D

2. Illustration shows device in word mode.

Figure 13. Program Operation Timing s

t

AS

PA PA

t

AH

t

CH

t

WPH

PD

t

BUSY

is the true data at the program address.

OUT

Read Status Data (last two cycles)

PA

t

WHWH1

Status

D

OUT

t

RB

21526B-16

Am29F200B 29

AC CHARACTERISTICS

Erase Command Sequence (last two cycles) Read Status Data

t

AS

555h for chip erase

VA

t

AH

VA

Addresses

t

WC

2AAh SA

CE#

t

GHWL

t

t

WP

t

DS

55h

t

CH

DH

t

WPH

30h

10 for Chip Erase

t

BUSY

t

WHWH2

In

Progress

Complete

t

RB

OE#

WE#

Data

t

CS

RY/BY#

t

VCS

V

CC

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (”see “Write Operation Status”).

2. Illustration shows device in word mode.

Figure 14. Chip/Sector Erase Operation Timings

21526B-17

30 Am29F200B

AC CHARACTERISTICS

Addresses

CE#

t

CH

OE#

t

WE#

DQ7

OEH

t

ACC

t

CE

t

VA

t

RC

OE

t

t

OH

Complement

DF

VA VA

Complement

True

Valid Data

High Z

DQ0–DQ6

t

BUSY

Status Data

Status Data

True

Valid Data

High Z

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.

21526B-18

Figure 15. Data# Polling Timings (During Embedded Algorithms)

t

RC

Addresses

CE#

OE#

WE#

DQ6/DQ2

RY/BY#

t

CH

t

BUSY

t

OEH

High Z

t

ACC

t

CE

VA

t

OE

t

DF

t

OH

(first read) (second read) (stops toggling)

VA VA

Valid Status

VA

Valid DataValid StatusValid Status

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle

21526B-19

Figure 16. Toggle Bit Timings (During Embedded Algorithms)

Am29F200B 31

AC CHARACTERISTICS

-

Enter

Embedded

Erasing

WE#

DQ6

DQ2

Erase

Erase

Suspend

Erase Suspend

Suspend Program

Read

Enter Erase

Erase

Suspend

Program

Erase Suspend

Read

Erase

Resume

Erase

Erase

Complete

Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the erase-sus
pended sector.

21526B-20

Figure 17. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

All Speed OptionsJEDEC Std Description Unit

t

t

VID Rise and Fall Time (See Note) Min 500 ns

VIDR

RESET# Setup Time for Temporary Sector

RSP

Unprotect

Min 4 µs

Note: Not 100% tested.

RESET#

CE#

WE#

RY/BY#

12 V

0 or 5 V

t

VIDR

Program or Erase Command Sequence

t

RSP

Figure 18. Tem pora ry Sector Unprotect Timi ng Diagram

t

VIDR

0 or 5 V

21526B-21

32 Am29F200B

AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations

Parameter Speed Options

JEDEC S td Descript ion -45 -50 -55 -70 -90 -120 Unit

t

t

AVAV

t

AVEL

t

ELAX

t

DVEH

t

EHDX

t

GHEL

t

WLEL

t

EHWH

t

ELEH

t

EHEL

t

WHWH1tWHWH1

t

Write Cycle Time (Note 1) Min 45 50 55 70 90 120 ns

WC

t

Address Setup Time Min 0 ns

AS

t

Address Hold Time Min 45 45 45 45 45 50 ns

AH

t

Data Setup Time M in 2 5 25 25 30 45 50 ns

DS

t

Data Hold Time Min 0 ns

DH

Output Enable Setup Time Min 0 ns

t

OES

Read Recovery Time Before Write

GHEL

(OE# High to WE# Low)

t

WE# Setup Time Min 0 ns

WS

t

WE# Hold Time Min 0 ns

WH

t

CE# Pulse Width Min 30 30 30 35 45 50 ns

CP

t

CE# Pulse Width High Min 20 ns

CPH

Programming Operation
(Note 2)

Byte Typ 7

Word Typ 12

Min 0 ns

µs

t

WHWH2tWHWH2

Sector Erase Operation (Note 2) Typ 1 sec

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Am29F200B 33

AC CHARACTERISTICS

Addresses

WE#

OE#

CE#

Data

RESET#

555 for program
2AA for erase

t

WC

t

WH

t

WS

t

RH

PA for program
SA for sector erase
555 for chip erase

t

AS

t

GHEL

t

CP

t

CPH

t

DS

t

DH

A0 for program
55 for erase

t

AH

t

PD for program
30 for sector erase
10 for chip erase

BUSY

Data# Polling

t

WHWH1 or 2

PA

DQ7# D

OUT

RY/BY#

Notes:

1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D

2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.

Figure 19. Alternate CE# Controlled Write Operation Timings

= Array Data.

OUT

21526B-22

34 Am29F200B

ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter

Sector Erase Time 1 8 sec
Chip Erase Time 5 sec
Byte Programming Time 7 300 µs

Word Programming Time 12 500 µs
Chip Programming Time (Note 3) 1.8 5.4 sec

Excludes 00h programming prior to
erasure (Note 4)

Excludes system-level overhead
(Note 5)

CommentsTyp (Note 1) Max (Note 2) Unit

Notes:

1. Typical program and erase times assume the following conditions: 25×C, 5.0 V V

, 1,000,000 cycles. Additionally,

CC

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 4.5 V (VCC = 4.75 V for ±5% devices), 1,000,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 1
for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Parameter Description Min Max

Input Voltage with respect to V

Current –100 mA +100 mA

V

CC

on all I/O pins –1.0 V VCC + 1.0 V

SS

Note: Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

Input Capacitance VIN = 0 6 7.5 pF
Output Capacitance V
Control Pin Capacitance VIN = 0 8 10 pF

= 0 8.5 12 pF

OUT

C

C

C

OUT

IN2

IN

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C 10 Years
125°C 20 Years

Am29F200B 35

PHYSICAL DIMENSIONS

SO 044—44-Pin Small Outline Package (measured in millimeters)

2.17

2.45

44

23

13.10

13.50

1

1.27 NOM.

TOP VIEW

28.00

28.40

0.35

0.50

SIDE VIEW

22

0.10

0.35

2.80

MAX.

15.70

16.30

SEATING
PLANE

0°
8°

0.10

0.21

0.60

1.00

END VIEW

16-038-SO44-2
SO 044
DF83
8-8-96 lv

36 Am29F200B

PHYSICAL DIMENSIONS

TS 048—48-Pin Standard Thin Small Outline Package (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

24

18.30

18.50

19.80

20.20

48

11.90

12.10

25

0.50 BSC

0.05

0.15

1.20

MAX

0.25MM (0.0098") BSC

0.08

0.20

0.10

0°

0.21

16-038-TS48-2
TS 048
DT95
8-8-96 lv

5°

0.50

0.70

Am29F200B 37

PHYSICAL DIMENSIONS

TSR048—48-Pin Reverse Thin Small Outline Package (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

24

18.30

18.50

19.80

20.20

1.20

MAX

0.25MM (0.0098") BSC

48

11.90

12.10

25

SEATING PLANE

16-038-TS48

0.08

0.20

TSR048
DT95
8-8-96 lv

0.10

0°

0.21

5°

0.50 BSC

0.05

0.15

0.50

0.70

38 Am29F200B

REVISION SUMMARY
Revision A

Global: Made formatting and layout consistent with other

data sheets. Used updated common tables and diagrams

Revision B

Distinctive Characteristics

Added bullet for 20-year data retention at 125°C

Ordering Information

Optional Processing

DC Characteristics—TTL/NMOS Compatible

I

, I

CC2

, I

CC3

CC1

cations are tested with V

DC Characteristics—CMOS Compatible

I

, I

CC2

, I

CC3

CC1

cations are tested with V

: Deleted “B = Burn-in”.

: Added Note 2 “Maximum ICC specifi-

CC

= V

CCmax

”.

: Added Note 2 “Maximum ICC specifi-

CC

= V

CCmax

”.

AC Characteristics

Figure 15. Data# Polling Timings (During Embedded
Algorithms)

: Added text to note.

Figure 16. Toggle Bit Timings (During Embedded Algo­rithms)

: Added text to note .

Revision B+1 (April 12, 1999)

Product Selector Guide

The 55 ns option now has a VCC operating range of
±10%.

Revision B+2 (July 2, 1999)

Global

Added referenc es to availability of device in K nown
Good Die (KGD) form.

Trademarks

Copyright © 1999 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am29F200B 39