Datasheet 1GbDDR2 Datasheet

Download

Page 1

DDR2 SDRAM

MT47H256M4 – 32 Meg x 4 x 8 banks MT47H128M8 – 16 Meg x 8 x 8 banks MT47H64M16 – 8 Meg x 16 x 8 banks

1Gb: x4, x8, x16 DDR2 SDRAM

Features

•RoHS compliant

•V

DD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V

• JEDEC standard 1.8V I/O (SSTL_18-compatible)

• Differential data strobe (DQS, DQS#) option

• 4-bit prefetch architecture

• Duplicate output strobe (RDQS) option for x8

• DLL to align DQ and DQS transitions with CK

• 8 internal banks for concurrent operation

• Programmable CAS latency (CL)

• Posted CAS additive latency (AL)

• WRITE latency = READ latency – 1

• Programmable burst lengths: 4 or 8

• Adjustable data-output drive strength

• 64ms, 8,192-cycle refresh

• On-die termination (ODT)

• Industrial temperature (IT) option

• Supports JEDEC clock jitter specification

Options Marking

• Configuration 256 Meg x 4 (32 Meg x 4 x 8 banks ) 256M4 128 Meg x 8 (16 Meg x 8 x 8 banks) 128M8 64 Meg x 16 (8 Meg x 16 x 8 banks) 64M16

• FBGA package (Pb-free) 92-ball FBGA (11mm x 19mm) (:A) BT 60-ball FBGA (8mm x 11.5mm) (:E) HQ 84-ball FBGA (8mm x 12.5mm) (:E) HR

• Timing – cycle time

5.0ns @ CL = 3 (DDR2-400) -5E

3.75ns @ CL = 4 (DDR2-533) -37E

3.0ns @ CL = 5 (DDR2-667) -3

3.0ns @ CL = 4 (DDR2-667) -3E

2.5ns @ CL = 6 (DDR2-800) -25

2.5ns @ CL = 5 (DDR2-800) -25E

• Self refresh Standard None Low-power L

• Operating temperature Commercial Industrial

• Revision :A/:E

(0°C ≤ TC ≤ 85°C)

(–40°C ≤ TC ≤ 95°C; –40°C ≤ TA ≤ 85°C)

None

Table 1: Configuration Addressing

Architecture 256 Meg x 4 128 Meg x 8 64 Meg x 16

Configuration

Refresh Count Row Addr. Bank Addr. Column Addr.

PDF: 09005aef821ae8bf/Source: 09005aef821aed36 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1GbbDDR2_1.fm - Rev. K 10/06 EN

32 Meg x 4 x

8 banks

8K 8K 8K

16K (A0–A13) 16K (A0–A13) 8K (A0–A12)

8 (BA0–BA2) 8 (BA0–BA2) 8 (BA0–BA2)

2K (A0–A9,

A11)

Products and specifications discussed herein are subject to change by Micron without notice.

16 Meg x 8 x

8 banks

1K (A0–A9) 1K (A0–A9)

8 Meg x 16 x

8 banks

Table 2: Key Timing Parameters

Speed Grade

-5E 400 400n/an/a151555

-37E 400 533 n/a n/a 15 15 55

-3 400533667n/a151555

-3E n/a667667n/a121254

-25 n/a n/a 667 800 15 15 55

-25E n/a 533 800 n/a 12.5 12.5 55

Note: CL = CAS latency.

Data Rate (MHz)

RCD

(ns)

(ns)CL = 3 CL = 4 CL = 5 CL = 6

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1Gb: x4, x8, x16 DDR2 SDRAM

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

FBGA Part Marking Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Industrial Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Mode Register (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

DLL RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Write Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Extended Mode Register (EMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

DLL Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Output Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

DQS# Enable/Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

RDQS Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

On-Die Termination (ODT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Off-Chip Driver (OCD) Impedance Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Posted CAS Additive Latency (AL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Extended Mode Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Extended Mode Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Command Truth Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

DESELECT, NOP, and LM Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

LOAD MODE (LM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Bank/Row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

ACTIVE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

ACTIVE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

READ Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

READ Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

WRITE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

WRITE Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

PRECHARGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

SELF REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Precharge Power-Down Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

RESET Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

(CKE LOW Anytime) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

ODT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MRS Command to ODT Update Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

PDF: 09005aef821ae8bf/Source: 09005aef821aed36 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1GbDDR2TOC.fm - Rev. K 10/06 EN

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Table of Contents

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

AC and DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Input Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Input Slew Rate Derating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Power and Ground Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

AC Overshoot/Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Output Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Full Strength Pull-Down Driver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Full Strength Pull-Up Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Reduced Strength Pull-Down Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Reduced Strength Pull-Up Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

FBGA Package Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

DD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

DD7 Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

AC Operating Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

PDF: 09005aef821ae8bf/Source: 09005aef821aed36 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1GbDDR2TOC.fm - Rev. K 10/06 EN

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List of Figures

Figure 1: 1Gb DDR2 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 2: 60-Ball FBGA Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 3: 84-Ball FBGA Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 4: 92-Ball FBGA Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 5: Functional Block Diagram – 64 Meg x 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 6: Functional Block Diagram – 128 Meg x 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 7: Functional Block Diagram – 256 Meg x 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 8: Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 9: DDR2 Power-up and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 10: Mode Register (MR) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 11: CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 12: Extended Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 13: READ Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 14: WRITE Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 15: Extended Mode Register 2 (EMR2) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 16: Extended Mode Register 3 (EMR3) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 17: ACTIVE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Figure 18: 8-Bank Activate Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Figure 19: READ Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Figure 20: Example: Meeting

Figure 21: READ Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Figure 22: Consecutive READ Bursts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 23: Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Figure 24: READ Interrupted by READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Figure 25: READ-to-PRECHARGE – BL = 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 26: READ-to-PRECHARGE – BL = 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 27: READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 28: Bank Read – without Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Figure 29: Bank Read – with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Figure 30: x4, x8 Data Output Timing – Figure 31: x16 Data Output Timing – Figure 32: Data Output Timing –

Figure 33: WRITE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 34: WRITE Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 35: Consecutive WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 36: Nonconsecutive WRITE-to-WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 37: Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 38: WRITE Interrupted by WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 39: WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 40: WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Figure 41: Bank Write – without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 42: Bank Write – with Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 43: WRITE – DM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 44: Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 45: PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 46: Self Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 47: Refresh Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 48: Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Figure 49: READ to Power-Down or Self Refresh Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Figure 50: READ with Auto Precharge to Power-Down or Self Refresh Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Figure 51: WRITE to Power-Down or Self-Refresh Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Figure 52: WRITE with Auto Precharge to Power-Down or Self Refresh Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Figure 53: REFRESH Command to Power-Down Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 54: ACTIVE Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 55: PRECHARGE Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Figure 56: LOAD MODE Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

RRD (MIN) and tRCD (MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

DQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

DQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

AC and tDQSCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

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List of Figures

Figure 57: Input Clock Frequency Change During Precharge Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . .76

Figure 58: RESET Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Figure 59: ODT Timing for Entering and Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Figure 60: Timing for MRS Command to ODT Update Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Figure 61: ODT Timing for Active or Fast-Exit Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Figure 62: ODT Timing for Slow-Exit or Precharge Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Figure 63: ODT Turn-off Timings When Entering Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Figure 64: ODT Turn-On Timing When Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Figure 65: ODT Turn-Off Timing When Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Figure 66: ODT Turn-On Timing When Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Figure 67: Example Temperature Test Point Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Figure 68: Single-Ended Input Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Figure 69: Differential Input Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Figure 70: Nominal Slew Rate for Figure 71: Tangent Line for Figure 72: Nominal Slew Rate for Figure 73: Tangent Line for Figure 74: Nominal Slew Rate for Figure 75: Tangent Line for Figure 76: Nominal Slew Rate for Figure 77: Tangent Line for

Figure 78: AC Input Test Signal Waveform Command/Address Balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 79: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential). . . . . . . . . . . . . . . . . . . . . . 107

Figure 80: AC Input Test Signal Waveform for Data with DQS (single-ended) . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 81: AC Input Test Signal Waveform (differential). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 82: Input Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 83: Overshoot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 84: Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 85: Differential Output Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 86: Output Slew Rate Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 87: Full Strength Pull-Down Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 88: Full Strength Pull-Up Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 89: Reduced Strength Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 90: Reduced Strength Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 91: 92-Ball FBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 92: 60-Ball FBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 93: 84-Ball FBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

IS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

IS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

IH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

IH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

DS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

DS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

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List of Tables

Table 1: Configuration Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 2: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 3: FBGA 60/84-Ball Descriptions – 256 Meg x 4, 128 Meg x 8, 64 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . .13

Table 4: 92-Ball Descriptions – 256 Meg x 4, 128 Meg x 8, 64 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 5: Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 6: Truth Table – DDR2 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 7: Truth Table – Current State Bank n – Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 8: Truth Table – Current State Bank n – Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 9: Minimum Delay with Auto Precharge Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 10: READ Using Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 11: WRITE Using Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 12: CKE Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 13: DDR2-400/533 ODT Timing for Active and Fast-Exit Power-Down Modes . . . . . . . . . . . . . . . . . . . . .81

Table 14: DDR2-400/533 ODT Timing for Slow-Exit and Precharge Power-Down Modes . . . . . . . . . . . . . . . . .82

Table 15: DDR2-400/533 ODT Turn-off Timings When Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . .83

Table 16: DDR2-400/533 ODT Turn-On Timing When Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . .84

Table 17: DDR2-400/533 ODT Turn-Off Timing When Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . .85

Table 18: DDR2-400/533 ODT Turn-On Timing When Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . .86

Table 19: Absolute Maximum DC Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Table 20: Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Table 21: Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Table 22: Recommended DC Operating Conditions (SSTL_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Table 23: ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Table 24: Input DC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Table 25: Input AC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Table 26: Differential Input Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Table 27: AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Table 28: DDR2-400/533 Setup and Hold Time Derating Values ( Table 29: DDR2-667 Setup and Hold Time Derating Values ( Table 30: DDR2-400/533 Table 31: DDR2-667

DS, tDH Derating Values with Differential Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

DS, tDH Derating Values with Differential Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 32: Single-Ended DQS Slew Rate Derating Values Using Table 33: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V

Table 36: Input Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 37: Address and Control Balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 38: Clock, Data, Strobe, and Mask Balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 39: Differential AC Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 40: Output DC Current Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 41: Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 42: Full Strength Pull-Down Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 43: Full Strength Pull-Up Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 44: Reduced Strength Pull-Down Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 45: Reduced Strength Pull-Up Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 46: Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 47: DDR2 I Table 48: DDR2 I Table 49: General I Table 50: I

DD Specifications and Conditions (die revision A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

DD Specifications and Conditions (die revision E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

DD Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

DD7 Timing Patterns (8-bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 51: AC Operating Conditions for -3E, -3, -37E and -5E Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

IS and tIH) . . . . . . . . . . . . . . . . . . . . . . . . . . .94

IS and tIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

DSb and tDHb . . . . . . . . . . . . . . . . . . . . . . . . . 101

REF) at DDR2-667 . . . . . . . . . . . . . . . . . 101

REF) at DDR2-533 . . . . . . . . . . . . . . . . . 102

REF) at DDR2-400 . . . . . . . . . . . . . . . . . 102

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Page 7

1Gb: x4, x8, x16 DDR2 SDRAM

List of Tables

Table 52: AC Operating Conditions for -25E and -25 Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

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Page 8

Part Numbers

Figure 1: 1Gb DDR2 Part Numbers

Example Part Number: MT47H128M8BT-37E

MT47H Package Speed

Configuration

256 Meg x 4 128 Meg x 8 64 Meg x 16

Package

92-Ball 11 x 19 FBGA 60-Ball 8 x 11.5 FBGA 84-Ball 8 x 12.5 FBGA

Notes: 1. Not all speeds and configurations are available. Contact Micron sales for current revision.

Configuration

256M4 128M8 64M16

BT HQ HR

1Gb: x4, x8, x16 DDR2 SDRAM

Part Numbers

Revision

{

:A/:E

Revision

Low-Power

Industrial Temperature Speed Grade

CK = 5ns, CL = 3

-5E t

CK = 3.75ns, CL = 4

-37E t

CK = 3ns, CL = 5

-3

-3E

-25

-25E

t t t

CK = 3ns, CL = 4 CK = 2.5ns, CL = 6 CK = 2.5ns, CL = 5

FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Micron’s FBGA Part Marking Decoder is available at www.micron.com/decoder.

General Description

The 1Gb DDR2 SDRAM is a high-speed CMOS, dynamic random access memory containing 1,073,741,824 bits. It is internally configured as an 8-bank DRAM. The functional block diagrams of the all device configurations are sho wn starting on page19. Ball assignments and signal descriptions are shown in “Ball Assignments and Descriptions” on page 10.

The 1Gb DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architec tur e is essentia lly a 4n- pr efe tch ar c hitec tur e, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the 1Gb DDR2 SDRAM effectively consists of a single 4n-bit- wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls.

A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#).

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Page 9

1Gb: x4, x8, x16 DDR2 SDRAM

General Description

The 1Gb DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS as well as to both edges of CK.

Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locat ions in a programme d sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coinci dent with the READ or WR ITE command are us ed to select the bank and the starting column location for the burst access.

The DDR2 SDRAM provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read or a burst write of eight with another write. An au to precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.

As with standard DDR SDRAMs, the pipeline d, multibank ar chitectur e of DDR2 SDRAMs allows for concurrent operation, thereby pro v iding high, effective bandwidth by hiding row precharge and activation time.

A self refresh mode is provided, along with a power-saving, powe r-down mode. All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength

outputs are SSTL_18-compatible.

Industrial Temperature

The industrial temperature (IT) device has two simultaneous requirements: ambient temperature surrounding the device cannot exceed –40°C or +85°C, and the case temperature cannot exceed –40°C or 95°C. JEDEC specifications require the refresh rate to double when T refresh option. Additionally, ODT resistance and the input/output impedance must be derated when the T

General Notes

• The functionality and the timing specifications discussed in this data sheet are for the DLL-enabled mode of operation.

• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x16 is divided into 2 bytes, the lower byte and upper byte. For the lower byte (DQ0–DQ7), DM refers to LDM and DQS refers to LDQS. For the upper byte (DQ8–DQ15), DM refers to UDM and DQS refers to UDQS.

• Complete functionality is described throughout the document, and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements.

• Any specific requirement takes precedence over a general statement.

exceeds 85°C; this also requires use of the high-temperature self

is < 0°C or > 85°C.

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Page 10

Ball Assignments and Descriptions

Figure 2: 60-Ball FBGA Assignment

Die rev E, HQ marking, top view (8mm x 11.5mm, x4/x8)

1234 6 7895

1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

NF,DQ6

NF,DQ4

BA2

NC,RDQS#/NU

VSSQ

DQ1

REF

CKE

BA0

A10

A12

DM,DM/RDQS

VDDQ

DQ3

WE#

BA1

RFU

DQS

DQ2

RAS#

CAS#

A11

RFU

DQS#/NU

DQ0

CK#

CS#

A13

NF,DQ7

NF,DQ5

ODT

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Page 11

Figure 3: 84-Ball FBGA Assignment

Die rev E, HR marking, top view, 8mm x 12.5mm, x16

1234 6 7895

VDD

DQ14

DDQ

DQ12

DQ6

SSQ

DQ9

SSQ

VSS

UDM

DDQ

DQ11

LDM

1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

VSSQ

UDQS

DDQ

DQ10

SSQ

LDQS

UDQS#/NU

SSQ

DQ8

SSQ

LDQS#/NU

SSQ

VDDQ

DQ15

DDQ

DQ13

DDQ

DQ7

DDQ

DQ4

DDL

BA2

VDD

DQ1

SSQ

REF

CKE

BA0

A10

A12

DDQ

DQ3

WE#

BA1

RFU

DDQ

DQ2

SSDL

RAS#

CAS#

A11

RFU

DQ0

SSQ

CK#

CS#

A13

DQ5

ODT

VSS

DDQ

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Page 12

Figure 4: 92-Ball FBGA Assignment

Die rev A, BT marking, top view, 11mm x 19mm, x4/x8/x16

1234 6 7895

1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

NF, DQ6

NF,DQ 4

BA2

NF, RDQS#/NU

VSSQ

DM/RDQS

DQ1

REF

CKE

BA0

A10

A12

DQ3

WE#

BA1

RFU

DQS

A11

RFU

DQS#/NU

DQ0

CK#

CS#

A13

NF, DQ7

NF, DQ5

VDD

ODT

DQ2

RAS#

CAS#

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Page 13

1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

Table 3: FBGA 60/84-Ball Descriptions – 256 Meg x 4, 128 Meg x 8, 64 Meg x 16

x16 Ball Number

x4, x8 Ball

Number Symbol Type Description

K9 F9 ODT Input

J8, K8 E8, F8 CK, CK# Input

K2 F2 CKE Input

L8 G8 CS# Input

K7, L7,

F3, B3

F7, G7,

RAS#, CAS#,

Input

WE#

LDM, UDM DMInput

L2, L3,

G2, G3,

BA0, BA1

BA2

Input

On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ0–DQ15, LDM, UDM, LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ0–DQ7, DQS, DQS#, RDQS, RDQS#, and DM for the x8; DQ0–DQ3, DQS, DQS#, and DM for the x4. The ODT input will be ignored if disabled via the LOAD MODE command.

Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.

Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides precharge power-down and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is synchronous for power-down entry, power-down exit, output disable, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during POWERDOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_18 input but will detect a LVCMOS LOW level once V

DD is applied during first power-up. After VREF

has become stable during the power-on and initialization sequence, it must be maintain e d for proper operation of the CKE receiver. For proper SELF-REFRESH operation, V

REF must be

maintained. Chip select: CS# enables (registered LOW) and di sables

(registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple ranks. CS# is considered part of the command code.

Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered.

Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. LDM is DM for lower byte DQ0–DQ7 and UDM is DM for upper byte DQ8– DQ15.

Bank address inputs: BA0–BA2 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0–BA2 define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.

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Page 14

1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

Table 3: FBGA 60/84-Ball Descriptions – 256 Meg x 4, 128 Meg x 8, 64 Meg x 16

x16 Ball Number

M8, M3, M7,

x4, x8 Ball

Number Symbol Type Description

– A0, A1, A2,

N2, N8, N3,

N7, P2, P8,

P3, M2,

P7, R2,

– H8, H3, H7,

J2, J8, J3,

J7, K2, K8,

K3, H2,

K7, L2,

G8, G2, H7,

– DQ0–DQ2,

H3, H1, H9,

F1, F9, C8, C2, D7, D3, D1, D9, B1,

–C8, C2, D7,

D3, D1, D9,

B1, B9

A3, A4, A5, A6, A7, A8,

A9, A10

A11, A12

A13

A0, A1, A2, A3, A4, A5, A6, A7, A8,

A9, A10

A11, A12,

A13

DQ3–DQ5, DQ6–DQ8,

DQ9–DQ11,

DQ12–DQ14,

DQ15

DQ0–DQ2, DQ3–DQ5,

DQ6–DQ7

Input

I/O

Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA2–BA0) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command.

Data input/output: Bidirectional data bus for 64 Meg x 16.

Data input/output: Bidirectional data bus for 128 Meg x 8.

– C8, C2, D7,

DQ0–DQ2,

DQ3

B7, A8 – UDQS, UDQS# I/O

F7, E8 – LDQS, LDQS# I/O

– B7, A8 DQS, DQS# I/O

– B3, A2 RDQS, RDQS# Output

A1, E1, M9, R1, J9A1, E9, L1, H9 V

DD Supply

I/O

Data input/output: Bidirectional data bus for 256 Meg x 4.

Data strobe for upper byte: Output with read data, input

with write data for source synchronous operation. Edge-aligned with read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE command.

Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center-aligned with write data. LDQS# is only used when differential data strobe mode is enabled via the LOAD MODE command.

Data strobe: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command.

Redundant data strobe for 128 Meg x 8 only. RDQS is enabled/disabled via the load mode command to the extended mode register (EMR). When RDQS is enabled, RDQS is output with read data only and is ignored during write data. When RDQS is disabled, pin B3 becomes data mask (s ee DM pin). RDQS# is only used when RDQS is enabled and differential data strobe mode is enabled.

Power supply: 1.8V ±0.1V.

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Page 15

1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

Table 3: FBGA 60/84-Ball Descriptions – 256 Meg x 4, 128 Meg x 8, 64 Meg x 16

x16 Ball Number

x4, x8 Ball

Number Symbol Type Description

J1 E1 VDDL Supply

A9, C1, C3, C7,

C9, G3, E9, G1,

A9, C1, C3, C7,

DDQ Supply

G7, G9,

J2 E2 V

A3, E3, J3, N1, P9A3, E3, J1, K9 V

J7 E7 V

A7, B2, B8, D2,

D8, E7, F2, F8,

A7, B2, B8, D2,

REF Supply

SS Supply

SSDL Supply

VSSQ Supply

H2, H8

A2, E2 NC –

– B1, B9, D1, D9 NF –

A8, E8 A2, A8 NU –

R3, R7 L3, L7 RFU –

DLL power supply: 1.8V ±0.1V. DQ power supply: 1.8V ±0.1V. Isolated on the device for

improved noise immunity.

SSTL_18 reference voltage. Ground.

DLL ground: Isolated on the device from V

SS and VSSQ.

DQ ground: Isolated on the device for improved noise immunity.

No connect: These pins should be left unconnected. No function: These pins are used as DQ4–DQ7 on the 128 Meg

x 8 , but are NF (no function) on the 256 Meg x 4 configuration. Not used:

If EMR[E10] = 0, For 64 Meg x 16, A8 = UDQS# and E8 = LDQS# For 128 Meg x 8, A2 = RDQS# and A8 = DQS# For 256 Meg x 4, A2 = NU and A8 = NU

If EMR[E10] = 1, For 64 Meg x 16, A8 = NU and E8 = NU For 128 Meg x 8, A2 = NU and A8 = NU For 256 Meg x 4, A2 = NU and A8 = NU

Reserved for future use: Row address bits A14 and A15.

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Page 16

1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

Table 4: 92-Ball Descriptions – 256 Meg x 4, 128 Meg x 8, 64 Meg x 16

x16 Ball Number

x4, x8 Ball

Number Symbol Type Description

N9 N9 ODT Input

M8, N8 M8, N8 CK, CK# Input

N2 N2 CKE Input

P8 P8 CS# Input

N7, P7,

RAS#, CAS#,

WE#

J3, E3 J3 LDM, UDM,

(DM)

P2, P3, P1 P2, P3, P1 BA0–BA2 Input

R8, R3, R7,

T2, T8, T3, T7,

U2, U8, U3,

R2, U7, V2

–A0–A2,

A3–A6, A7–A9,

A10–A12

Input

On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following balls: DQ0–DQ15, LDM, UDM, LDQS, LDQS#, UDQS, and UD QS# for the x16; DQ0–DQ7, DQS, DQS#, RDQS, RDQS#, and DM for the x8; DQ0–DQ3, DQS, DQS#, and DM for the x4. The ODT input will be ignored if disabled via the LOAD MODE command.

Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/ DQS#) is referenced to the crossings of CK and CK#.

Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operat ing mode. CKE LOW provides precharge power-down mode and SELF REFRESH operation (all banks idle), or active power-down (row active in any bank). CKE is synchronous for power-down entry, power-down exit, output disable, and self refresh entry . CKE is asynchronous for SELF REFRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during self refresh. CKE is an SSTL_18 input but will detect a LVCMOS LOW level once V

DD is applied during first

power-up. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper SELF REFRESH operation,

REF must be maintained.

V Chip select: CS# enables (registered LOW) and disables (registered

HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external ba nk selection on systems with multiple ranks. CS# is considered part of the command code.

Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered.

Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled HIGH during a WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM loading is designed to match that of DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM for upper byte DQ8–DQ15.

Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/ WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA2–BA0) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command.

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Page 17

1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

Table 4: 92-Ball Descriptions – 256 Meg x 4, 128 Meg x 8, 64 Meg x 16

x16 Ball Number

– R8, R3, R7, T2,

K8, K2, L7, L3,

L1, L9, J1, J9,

F8, F2, G7,

G3, G1, G9,

E1, E9

– K8, K2, L7, L3,

x4, x8 Ball

Number Symbol Type Description

A0–A3,

T8, T3, T7, U2,

U8, U3, R2, U7, V2, V8

A4–A7, A8–A10, A11–A13

– DQ0–DQ3,

DQ4–DQ7,

DQ8–DQ10,

DQ11–DQ13,

DQ14–DQ15

DQ0–DQ3,

L1, L9, J1, J9

DQ4–DQ7

– K8, K2, L7, L3 DQ0–DQ3 I/O

E7, D8

J7, H8

– UDQS,

UDQS#

– LDQS,

LDQS#

– J7, H8 DQS, DQS# I/O

– J3, H2 RDQS, RDQS# Output

D1, H1, M9,

R9, V1

D1, H1, M9,

R9, V1

M1 M1 V

D9, F1, F3, F7,

F9, H9, K1,

D9, H9, K1,

K3, K7, K9

DD Supply

DDL Supply

DDQ Supply

K3, K7, K9

M2 M2 V

D3, H3, M3,

T1, U9

D3, H3, M3,

T1, U9

M7 M7 V

D7, E2, E8,

G2, G8, H7,

D7, H7,J 2,

J8, L2, L8

REF Supply

SS Supply

SSDL Supply

SSQ Supply

J2, J8, L2, L8

Input

I/O

Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/ WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA2–BA0) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command.

Data input/output: Bidirectional data bus for 64 Meg x 16.

Data input/output: Bidirectional data bus for 128 Meg x 8.

Data input/output: Bidirectional data bus for 256 Meg x 4. Data strobe for upper byte: Output with read data, input with

write data for source synchronous operation. Edge-aligned with read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE command.

Data strobe: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center-aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command.

Redundant data strobe: For 128 Meg x 8 only. RDQS is enabled/ disabled via the LOAD MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS is output with read data only and is ignored during write data. When RDQS is disabled, ball J3 becomes data mask (see DM ball). RDQS# is only used when RDQS is enabled and differential data strobe mode is enabled.

Power supply: 1.8V ±0.1V.

DLL power supply: 1.8V ±0.1V. DQ power supply: 1.8V ±0.1V. Isolated on the device for

improved noise immunity.

SSTL_18 reference voltage. Ground.

DLL ground: Isolated on the device from VSS and VSSQ. DQ ground: Isolated on the device for improved noise immunity.

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Page 18

1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

Table 4: 92-Ball Descriptions – 256 Meg x 4, 128 Meg x 8, 64 Meg x 16

x16 Ball Number

A1, A2, A8,

A9 D2, H2,

AA1, AA2, AA8, AA9

x4, x8 Ball

Number Symbol Type Description

A1, A2, A8,

NC –

A9, D2, D8,

E1–E3, E7–E9,

F1–F3, F7–F9,

G1–G3,

G7–G9, AA1,

AA2, AA8,

AA9

– J1, J9, L1, L9,

NF –

H2,

D8, H8 – NU –

– H2, H8 NU –

V3, V7, V8 V3, V7 RFU –

No connect: These balls should be left unconnected.

No function: These balls are used as D Q4–DQ7 o n the 12 8 Meg x8

, but are NF (no function) on the 256 Meg x 4 configuration. Not used: Not used only on x16. If EMR[E10] = 0, D8 and H8 are

UDQS# and LDQS#. If EMR[E10] = 1, then D8 and H8 are not used.

Not used: Not used only on x8. If EMR[E10] = 0, H2 and H8 are RDQS# and DQS#. If EMR[E10] = 1, then H2 and H8 are not used.

Reserved for future use: Row address bits A13 (V8), A14(V3), and A15(V7) are reserved.

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Page 19

Functional Description

The 1Gb DDR2 SDRAM is a high-speed CMOS dynamic random access memory containing 1,073,741,824 bits. The 1Gb DDR2 SDRAM is internally configured as an 8bank DRAM.

The 1Gb DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The DDR2 architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the 1Gb DDR2 SDRAM consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit- wide, one-half-clockcycle data transfers at the I/O balls.

Prior to normal operation, the DDR2 SDRAM must be i n itialized. The following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation.

Figure8 on page 21 shows a simplified state diagram to pro vide the basic command flow. It is not comprehensive and does not identify all timing requirements or possible command restrictions.

Figure 5: Functional Block Diagram – 64 Meg x 16

1Gb: x4, x8, x16 DDR2 SDRAM

Functional Description

ODT

CKE

CK#

CS# RAS# CAS#

WE#

A0–A12,

A0–BA2

BANK 3

BANK 2

BANK 1

BANK 0

ROW-

LATCH

BANK 7

BANK 6

BANK 5

BANK 4

8,192

8 2

MEMORY

(8,192 x 256 x 64)

SENSE AMPLIFIERS

16,384

I/O GATING

DM MASK LOGIC

COLUMN DECODER

CONTROL

DECODE

COMMAND

MODE

REGISTERS

ADDRESS REGISTER

LOGIC

REFRESH

COUNTER

ROW-

ADDRESS

MUX

ADDRESS

DECODER

BANK

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

BANK 2

BANK 1

BANK 0

ARRAY

256

(x64)

BANK 6

BANK 5

BANK 4

BANK 3

BANK 7

CK,CK#

COL0,COL1

ODT CONTROL

sw1

R1 R1

sw1

R1 R1

sw1

R1 R1

UDQS, UDQS# LDQS, LDQS#

2 2 2

2 16 16 16 16

CK,CK#

DLL

DRVRS

RCVRS

COL0,COL1

READ

LATCH

WRITE

FIFO

DRIVERS

CK OUT

CK IN

16 16

MUX

MASK

DATA

DQS

GENERATOR

INPUT

REGISTERS

2 2

2 2 16 16 16 16

sw2

R2 R2

sw2

R2 R2

sw2

R2 R2

VssQ

sw3

R3 R3

sw3

R3 R3

sw3

R3 R3

VDDQ

DQ0–DQ15

UDQS, UDQS# LDQS, LDQS#

UDM, LDM

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Page 20

Figure 6: Functional Block Diagram – 128 Meg x 8

1Gb: x4, x8, x16 DDR2 SDRAM

Functional Description

ODT

CKE

CK#

CS# RAS# CAS#

WE#

A0-A13,

BA0-BA2

BANK 2

BANK 1

ROW-

LATCH

BANK 5

BANK 4

BANK 3

16,384

8 2

BANK 7

BANK 6

(16,384 x 256 x 32)

SENSE AMPLIFIERS

I/O GATING

DM MASK LOGIC

COLUMN

DECODER

CONTROL

DECODE

COMMAND

MODE

REGISTERS

ADDRESS REGISTER

LOGIC

REFRESH

COUNTER

ROW-

ADDRESS

MUX

ADDRESS

DECODER

BANK

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

BANK 0

BANK 3

BANK 2

BANK 1

BANK 0

MEMORY

ARRAY

8,192

256

(x32)

BANK 7

BANK 6

BANK 5

BANK 4

COL0,COL1

Figure 7: Functional Block Diagram – 256 Meg x 4

CK,CK#

ODT CONTROL

sw1

R1 R1

sw1

R1 R1

sw1

R1 R1

DATA

UDQS, UDQS# LDQS, LDQS#

CK,CK#

DLL

DRVRS

2 2

RCVRS

8 8

COL0,COL1

READ

LATCH

WRITE

FIFO

DRIVERS

CK OUT

CK IN

8 8

MUX

DQS

GENERATOR

INPUT

REGISTERS

2 2

MASK

DATA

2 8 8 8 8

sw2

R2 R2

sw2

R2 R2

sw2

R2 R2

VssQ

sw3

VDDQ

R3 R3

DQ0–DQ7

DQS, DQS#

RDQS#

RDQS

ODT

CKE

CK#

CS#

RAS#

CAS#

WE#

A0-A13,

BA0-BA2

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CONTROL

DECODE

COMMAND

MODE

REGISTERS

ADDRESS REGISTER

LOGIC

REFRESH

COUNTER

ROW-

ADDRESS

MUX

ADDRESS

DECODER

BANK

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

BANK 3

BANK 2

BANK 1

BANK 0

ROW-

LATCH

BANK 7

BANK 6

BANK 5

BANK 4

16,384

9 2

MEMORY

(16,384 x 512 x 16)

SENSE AMPLIFIERS

I/O GATING

DM MASK LOGIC

COLUMN

DECODER

BANK 2

BANK 1

BANK 0

ARRAY

8,192

512

(x16)

BANK 7

BANK 6

BANK 5

BANK 4

BANK 3

CK,CK#

COL0,COL1

READ

LATCH

WRITE

FIFO

DRIVERS

CK OUT

CK IN

COL0,COL1

4 4 4

MUX

GENERATOR

MASK

DATA

DQS

INPUT

REGISTERS

1 1 1 4 4 4 4

DQS, DQS#

1 1 1 1 4 4 4 4

CK,CK#

DLL

DRVRS

RCVRS

ODT CONTROL

sw1

R1 R1

sw1

R1 R1

sw1

R1 R1

sw2

R2 R2

sw2

R2 R2

sw2

R2 R2

VssQ

sw3

VDDQ

R3 R3

DQ0–DQ3

DQS, DQS#

Page 21

State Diagram

Figure8 shows a simplified state diagram to provide the basic command flow. It is not comprehensive and does not identify all timing requirements or possible command restrictions.

Figure 8: Simplified State Diagram

1Gb: x4, x8, x16 DDR2 SDRAM

State Diagram

OCD

calibration

Setting

MRS

EMRS

WRITE

(E)MRS

Automatic Sequence

Command Sequence

CKE_L

Active

Power-

Down

Writing

WRITE

CKE_L

PRE

CKE_H

WR_A

Initialization

Sequence

Idle

All banks

Precharged

ACT

Activating

Bank

Active

WR_A

CKE_H

RD_

CKE_L

Self

Refreshing

CKE_H

REFRESH

CKE_L

Precharge

Power-

Down

ACT = Activate

CKE_H = CKE HIGH, exit power-down or self refresh CKE_L = CKE LOW, enter power-down

(E)MRS = (Extended) mode register set PRE = PRECHARGE PRE_A = PRECHARGE ALL READ = READ RD_A = READ with auto precharge REFRESH = REFRESH SR = SELF REFRESH WRITE = WRITE WR_A = WRITE with auto precharge

READ

CKE_L

READ

Reading

Refreshing

RD_A

WR_A

Writing

with

Auto

Precharge

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PRE, PRE_A

Precharging

WR_A

RD_A

Reading

with

PRE , PRE_A

Auto

Precharge

Page 22

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1GbDDR2_2.fm - Rev. K 10/06 EN

Initialization

VDD

VDDL

VDDQ

VTT VREF

CK#

CKE

Notes appear on page 23

VTD

LVCMOS LOW LEVEL

SSTL_18

LOW LEVEL

DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Figure 9 illustrates the sequence required for power-up and initialization.

Figure 9: DDR2 Power-up and Initialization

Ta0

Tb0

Tc0Td0

Te0 Tf0

Tg0 Th0 Ti0 Tj0

Tk0 Tl0 Tm0

ODT

COMMAND

ADDRESS

NOP

PRE

A10 = 1

CODE

CODE CODE

PRE

REF

A10 = 1

CODE

VALID

1Gb: x4, x8, x16 DDR2 SDRAM

High-Z

DQS

High-Z

T = 200µs (MIN)

Power-up:

and stable

V clock (CK, CK#)

T = 400ns

(MIN)

RPA

EMR(2)

MRD

EMR(3)

MRD

EMR

MRD

MR with

DLL RESET

MRD

RPA

200 cycles of CK are required before a READ command can be issued.

RFC

See note 12

RFC

MR without

DLL RESET

MRD

EMR with

OCD Default

Indicates a break in time scale

MRD

EMR with

OCD Exit

MRD

Normal

Operation

DON’T CARE

Initialization

Page 23

1Gb: x4, x8, x16 DDR2 SDRAM

Initialization

Notes: 1.

10. Issue a LOAD MODE command with LOW to A8 to initialize device operation (i.e., to pro-

11. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, and

12. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and E9

Applying power; if CKE is maintained below 0.2 x VDDQ,

outputs remain disabled. To guarantee RTT (ODT resistance) is off, VREF must be valid and a low le vel must be applied to the ODT ball (all other inputs may be undefined, I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DDR2 SDRAM device latch-up). At least one of the following two sets of conditions (A or B) must be met to obtain a stable supply state (stable supply defined as V

DD, VDDL, VDDQ, VREF, and VTT are between their minimum and maximum val-

ues as stated in Table 22):

1a. (single power source) The VDD voltage ramp from 300mV to VDD (MIN) must take no

longer than 200ms; during the V

DD voltage ramp, |VDD - VDDQ| ≤ 0.3V. Once supply volt-

age ramping is complete (when VDDQ crosses VDD (MIN)), Table 22 specifications apply.

–V

DD, VDDL, and VDDQ are driven from a single power converter output

–V

TT is limited to 0.95V MAX

–V

REF tracks VDDQ/2; VREF must be within ±0.3V with respect to VDDQ/2 during supply

ramp time

–V

DDQ ≥ VREF at all times

1b. (multiple power sources) V

DD ≥ VDDL ≥ VDDQ must be maintained during supply voltage

ramping, for both AC and DC levels, until supply voltage ramping completes (VDDQ crosses VDD [MIN]). Once supply voltage ramping is complete, Table 22 specifications apply.

–Apply VDD and VDDL before or at the same time as VDDQ; VDD/VDDL voltage ramp time

must be ≤ 200ms from when VDD ramps from 300mV to VDD (MIN)

–Apply V

DDQ before or at the same time as VTT; the VDDQ voltage ramp time from when

VDD (MIN) is achieved to when VDDQ (MIN) is achieved must be ≤ 500ms; while VDD is ramping, current can be supplied from V

–V

REF must track VDDQ/2, VREF must be within ±0.3V with respect to VDDQ/2 during supply

DD through the device to VDDQ

ramp time; VDDQ ≥ VREF must be met at all times

–Apply V

TT; The VTT voltage ramp time from wh en VDDQ (MI N ) is achieved to when VTT

(MIN) is achieved must be no greater than 500ms

2. For a minimum of 200µs after stable power and clock (CK, CK#), apply NOP or DESELECT commands, then take CKE HIGH.

3. Wait a minimum of 400ns, then issue a PRECHARGE ALL command.

4. Issue an LOAD MODE command to the EMR(2). (To issue an EMR(2) command, provide LOW to BA0 and BA2, provide HIGH to BA1.)

5. Issue a LOAD MODE command to the EMR(3). (To issue an EMR(3) command, provide HIGH to BA0 and BA1, provide LOW to BA2.)

6. Issue an LOAD MODE command to the EMR to enable DLL. To issue a DLL ENABLE command, provide LOW to BA1, BA2, and A0, provide HIGH to BA0. Bits E7, E8, and E9 can be set to “0” or “1”; Micron recommends setting them to “0.”

7. Issue a LOAD MODE command for DLL RESET. 200 cycles of clock input is required to lock the DLL. (T o issue a DLL RESET, provide HIGH to A8 and provide LOW to BA2, BA1, and BA0.) CKE must be HIGH the entire time.

8. Issue PRECHARGE ALL command.

9. Issue two or more REFRESH commands.

gram operating parameters without resetting the DLL).

E9 to “1,” and then setting all other desired parameters.

to “0,” and then setting all other desired parameters.

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Page 24

Mode Register (MR)

The mode register is used to define the specific mode of oper atio n of the DDR2 SDRAM. This definition includes the selection of a burst length, burst type, CAS latency, operating mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 10 on page 25. Contents of the mode register can be altered by re-executing the LOAD MODE (LM) command. If the user chooses to modify only a subset of the MR variables, all variables (M0–M13 for x4 and x8 or M0–M12 for x16) must be programmed when the command is issued.

The MR is programmed via the LM command (bits BA2–BA0 = 0, 0, 0) and other bits (M13–M0 for x4 and x8, M12–M0 for x16) will retain the stored information until it is programmed again or the device loses power (except for bit M8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly.

The LM command can only be issued (or reissued) when all banks are in the precharged state (idle state) and no bursts are in progress. The control ler must wait the specified time Violating either of these requirements will result in unspecified operation.

Burst Length

1Gb: x4, x8, x16 DDR2 SDRAM

Mode Register (MR)

MRD before initiating any subsequent operations such as an ACTIVE command.

Burst length is defined by bits M0–M3, as shown in Figure 10 on page 25. Read and write accesses to the DDR2 SDRAM are burst-oriented, with the burst length being programmable to either four or eight. The burst length dete rmines the maximum number of column locations that can be accessed for a given READ or WRITE command.

When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL = 8 (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts.

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Page 25

Figure 10: Mode Register (MR) Definition

1Gb: x4, x8, x16 DDR2 SDRAM

Mode Register (MR)

BA2

M16

0 0 0

BA1

M15

0 1 1

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

A13

M12

PD mode

(Normal)

Slow Exit

(Low Power)

M11

0 0 0 0 1 1 1 1

M14

Extended Mode Register (EMR)

Extended Mode Register (EMR2)

Extended Mode Register (EMR3)

A10A12 A11BA0

9 765438 210

10111213

DLL TM

Fast Exit

0 1

WRITE RECOVERY

M10

Reserved

Mode Register Definition

Mode Register (MR)

0 1

DLL Reset

2 3 4 5 6

CAS#

Mode

Normal

Test

Yes

Latency

0 0 0 0 1 1 1 1

Burst Length

BTPD

0 1

Mode Register (Mx)

Burst Type

Sequential

Interleaved

CAS Latency (CL)

Reserved Reserved Reserved

Reserved

Address Bus

Burst Length

Reserved Reserved

8 Reserved Reserved Reserved Reserved

3 4 5 6

Notes: 1. M13 (A13) is reserved for future use and must be programmed to “0.” A13 is not used in

x16 configuration.

2. Not all listed CL options are supported in any individual speed grade.

Burst Type

Accesses within a given burst may be programme d to be either seque ntial or interl eaved. The burst type is selected via bit M3, as shown in Figure 10. The ordering of accesses within a burst is determined by th e burs t leng th, t he burs t t ype, and the starting column address, as sho wn in Table5 on page 26. DDR2 SDRAM supports 4-bit burst mode and 8bit burst mode only. For 8-bit burst mode, full, interleaved address ordering is supported; however, sequential address ordering is nibbl e-based.

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Page 26

Table 5: Burst Definition

1Gb: x4, x8, x16 DDR2 SDRAM

Mode Register (MR)

Operating Mode

Starting Column

Burst Length

4 0 0 0, 1, 2, 3 0, 1, 2, 3

8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7

Address

(A2, A1, A0)

0 1 1, 2, 3, 0 1, 0, 3, 2 1 0 2, 3, 0, 1 2, 3, 0, 1

1 1 3, 0, 1, 2 3, 2, 1, 0

0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0

Burst Type = Sequential Burst Type = Interleaved

Order of Accesses Within a Burst

The normal operating mode is selected by issuing a command with bit M7 set to “0,” and all other bits set to the desired values, as sh own in Figure 10 on page 25. When bit M7 is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1” places the DDR2 SDRAM into a test mode that is only used by the manufacturer and should not be used. No operation or functionality is guaranteed if M7 bit is “1.”

DLL RESET

Write Recovery

DLL RESET is defined by bit M8, as shown in Figure 10 on page 25. Programming bit M8 to “1” will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a value of “0” after the DLL RESET function has been issued.

Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of

the

AC or tDQSCK parameters.

Write recovery (WR) time is defined by bits M9–M11, as shown in Figure10 on page 25. The WR register is used by the DDR2 SDRAM during WRITE with auto precharge operation. During WRITE with auto precharge operation, the DDR2 SDRAM delays the internal auto precharge operation b y WR clocks (programmed in bits M9–M11) from the last data burst. An example of WRITE with auto precharge is shown in Figure 42 on page 62.

WR values of 2, 3, 4, 5, or 6 clocks may be used for programming bits M9–M11. The user is required to program the value of WR, which is calculated by dividing onds) by WR [cycles] =

CK (in nanoseconds) and rounding up a noninteger value to the next integer;

WR [ns] / tCK [ns]. Reserved states should not be used as unknown opera-

WR (in nanosec-

tion or incompatibility with future versions may result.

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Page 27

Power-Down Mode

1Gb: x4, x8, x16 DDR2 SDRAM

Mode Register (MR)

Active power-down (PD) mode is defined by bit M12, as shown in Figure10 on page 25. PD mode allows the user to determine the active power-down mode, which determines performance versus power savings. PD mode bit M12 does not apply to precharge PD mode.

When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled.

The

XARD parameter is used for fast-exit active PD exit timing. The DLL is expected to

be enabled and running during this mode.

CAS Latency (CL)

When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is enabled. The

XARDS parameter is used for slow-exit active PD exit timing. The DLL can be enabled but “frozen” during active PD mode since the exit-to-READ command timing is relaxed. The power difference expected between I

DD3P normal and IDD3P low-power

mode is defined in Table 47 on page 118.

The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 10 on page 25. CL is the delay , in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The CL can be set to 3, 4, 5, or 6 clocks, depending on the speed grade option being used.

DDR2 SDRAM does not support any half-clock latencie s. Reserved states should not be used as unknown operation or incompatibility with future versions may result.

DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This feature allows the READ command to be issued prior to

RCD (MIN) by delaying the internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in more detail in “Posted CAS Additive Latency (AL)” on page 31.

Examples of CL = 3 and CL = 4 are shown in Figure11 on page 28; both assume AL = 0. If a READ command is registered at clock edge n, and the CL is m clocks, the data will be available nominally coincident with clock edge n + m (this assumes AL = 0).

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Page 28

Figure 11: CAS Latency (CL)

1Gb: x4, x8, x16 DDR2 SDRAM

Extended Mode Register (EMR)

CK#

COMMAND

DQS, DQS#

CK#

COMMAND

DQS, DQS#

T0 T1 T2

READ

T0 T1 T2

READ

NOP NOP NOP

CL = 3 (AL = 0)

NOP NOP NOP

CL = 4 (AL = 0)

T3 T4 T5

NOP NOP

DOUT

T3 T4 T5

DOUT

n + 1

DOUT

n + 2

NOP NOP

DOUT

n + 3

DOUT

n + 1

DOUT

n + 2

NOP

DOUT n + 3

DON’T CARETRANSITIONING DATA

Notes: 1. BL = 4.

2. Posted CAS# additive latency (AL) = 0.

3. Shown with nominal tAC, tDQSCK, and tDQSQ.

Extended Mode Register (EMR)

The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, ondie termination (ODT) (R DQS# enable/disable, RDQS/RDQS# enable/disable, and output disable/ enable. These functions are controlled via the bits shown in Figure 12 on page 29. The EMR is programmed via the LM command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly.

The EMR must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specif ie d ti me tion. Violating either of these requiremen ts could result in unspecified operation.

TT), posted AL, off-chip driver impedance calibration (OCD),

MRD before initiating any subsequent opera-

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Page 29

Figure 12: Extended Mode Register Definition

1Gb: x4, x8, x16 DDR2 SDRAM

DLL Enable/Disable

BA2

MRS

E12

0 1

A13

Outputs Enabled Disabled

RDQS Enable

E11

0 1

E10

A10A12 A11BA0BA1

10111213

RDQS

DQS#

Yes

DQS# Enable

Enable

Disable

OCD Operation

OCD Not Supported

Reserved

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

9765438210

OCD Program

Rtt

Rtt (nominal)

Rtt Disabled

75 ohm 150 ohm Reserved

0 0 0 0 1 1 1 1

ODS

0 1

Posted CAS# Additive Latency (AL)

Address Bus

Extended Mode Register (Ex)

DLLPosted CAS# Rttout

DLL Enable

Enable (Normal)

Disable (Test/Debug)

Output Drive Strength

100%

60%

0 1 2 3

4 Reserved Reserved Reserved

E15

1 1

Notes: 1. During initialization, all three bits must be set to “1” for OCD default state, then must be

2. E13 (A13) is not used on the x16 configuration.

DLL Enable/Disable

The DLL may be enabled or disabled by programming bit E0 during the LM command, as shown in Figure12. The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL should always be followed by resetting the DLL using the LM command.

The DLL is automatically disabled when entering SELF REFRESH operation and is automatically re-enabled and reset upon exit of SELF REFRESH oper ation.

Anytime the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a READ command can be issued, to allow time for the internal clock to synchronize with the external clock. Failing to wait for synchronization to occur may result in a violation of the

E14

0 1

*E13 (A13) and E16 (BA2) are reserved for future use and must be programmed to '0'.

Mode Register Set

Mode Register Set (MRS)

Extended Mode Register (EMRS)

Extended Mode Register (EMRS2) Extended Mode Register (EMRS3)

set to “0” before initialization is finished, as detailed in the notes on page 23.

AC or tDQSCK parameters.

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Page 30

Output Drive Strength

The output drive strength is defined by bit E1, as shown in Figure 12 on page 29. The normal drive strength for all outputs are specified to be SSTL_18. Programming bit E1 = 0 selects normal (full strength) drive strength for all outputs. Selecting a reduced drive strength option (E1 = 1) will reduce all outputs to approximately 60 percen t of the SSTL_18 drive strength. This option is intended for the support of lighter load and/or point-to-point environments.

DQS# Enable/Disable

The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the complement of the differential data strobe pair DQS/DQS#. When disabled (E10 = 1), DQS is used in a single-ended mode and the DQS# ball is disabled. When disabled, DQS# should be left floating. This function is also used to enable/disable RDQS#. If RDQS is enabled (E11 =

1) and DQS# is enabled (E10 = 0), then both DQS# and RDQS# will be enabled.

RDQS Enable/Disable

The RDQS ball is enabled by bit E11, as shown in Figure 12 on page 29. This feature is only applicable to the x8 configuration. When enabled (E11 = 1), RDQS is identical in function and timing to data strobe DQS during a READ. During a WRITE operation, RDQS is ignored by the DDR2 SDRAM.

1Gb: x4, x8, x16 DDR2 SDRAM

Output Drive Strength

Output Enable/Disable

The OUTPUT ENABLE function is defined by bit E12, as shown in Figure12 on page 29. When enabled (E12 = 0), all outputs (DQs, DQS, DQS#, RDQS, RDQS#) function normally. When disabled (E12 = 1), all DDR2 SDRAM outputs (DQs, DQS, DQS#, RDQS, RDQS#) are disabled, thus removing output buffer current. The output disable featur e i s intended to be used during I

On-Die Termination (ODT)

ODT effective resistance, RTT (EFF), is defined by bits E2 and E6 of the EMR, as shown in Figure12 on page 29. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DDR2 SDRAM controller to independently turn on/off ODT for any or all devices. R selectable and apply to each DQ, DQS/DQS#, RDQS/RDQS#, UDQS/UDQS#, LDQS/ LDQS#, DM, and UDM/LDM signals. Bits (E6, E2) deter m ine wh at ODT resistance is enabled by turning on/off “sw1,” “sw2,” or “sw3.” The ODT effective resistance value is selected by enabling switch “sw1,” which enables all R1 values that are 150Ω each, enabling an effective resistance of 75Ω (R all R2 values that are 300Ω each, enable an effective ODT resistance of 150Ω (R = R2/2). Switch “sw3” enables R1 values of 100Ω, enabling effe c tive resistance of 50 Ω. Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

The ODT control ball is used to determine when R assuming ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and ODT input ball are only used during active, active power-down (both fast-exit and slowexit modes), and precharge power-down modes of operation.

DD characterization of read current.

TT effective resistance values of 50Ω, 75Ω, and 150Ω are

TT2 (EFF) = R2/2). Similarly, if “sw2” is enabled,

TT2 (EFF)

TT (EFF) is turned on and off,

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Page 31

Off-Chip Driver (OCD) Impedance Calibration

ODT must be turned off prior to entering self refresh. During power-up and initialization of the DDR2 SDRAM, ODT should be disabled until issuing the EMR command to enabl e the ODT feature, at which point the ODT ball will determine the R time the EMR enables the ODT function, ODT may not be driven HIGH until eight clocks after the EMR has been enabled. See “ODT Timing” on page 79 for ODT timing diagrams.

Off-Chip Driver (OCD) Impedance Calibration

The OFF-CHIP DRIVER function is no longer supported and must be set to the default state. See “Initialization” on page22 for proper setting of OCD defaults.

Posted CAS Additive Latency (AL)

Posted CAS additive latency (AL) is supported to make the command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. Bits E3–E5 define the value of AL, as shown in Figure12 on page 29. Bits E3–E5 allow the user to program the DDR2 SDRAM with an inverse AL of 0, 1, 2, 3, or 4 clocks. Reserved states should not be used as unknown operation or incompatibility with future versions may result.

1Gb: x4, x8, x16 DDR2 SDRAM

TT (EFF) value. Any

In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued prior to using this feature would set AL = held for the time of the AL before it is issued internally to the DDR2 SDRAM device. RL is controlled by the sum of AL and CL; RL = AL + CL. Write latency (WL) is equal to RL minus one clock; WL = AL + CL - 1 x example of a WL is shown in Figure14 on page 32.

Figure 13: READ Latency

T0 T1 T2

CK#

COMMAND

DQS, DQS#

ACTIVE n

READ n NOP NOP

Notes: 1. BL = 4.

2. Shown with nominal

3. CL = 3.

4. AL = 2.

5. RL = AL +CL = 5.

RCD (MIN)

RCD (MIN) with the requirement that AL ≤ tRCD (MIN). A typical application

T3 T4 T5

AL = 2

RL = 5

AC, tDQSCK, and tDQSQ.

RCD (MIN) - 1 x tCK. The READ or WRITE command is

CK. An example of RL is shown in Figure 13. An

NOP

CL = 3

NOP

DOUT

T7 T8

NOP NOP

DOUT

n + 2

n + 1

DOUT

n + 3

DON’T CARETRANSITIONING DATA

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Page 32

Figure 14: WRITE Latency

1Gb: x4, x8, x16 DDR2 SDRAM

Extended Mode Register 2

CK#

COMMAND

DQS, DQS#

T0 T1 T2

ACTIVE n

RCD (MIN)

AL = 2 CL - 1 = 2

Notes: 1. BL = 4.

2. CL = 3.

3. AL = 2.

4. WL = AL + CL - 1 = 4.

Extended Mode Register 2

The extended mode register 2 (EMR2) controls functions beyond those controlled by the mode register. Currently all bits in EMR2 are reserved, except for E7, which is for commercial or high-temperature operations, as shown in Figure15. The EMR2 is programmed via the LM command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly.

T3 T4 T5

NOP NOP

WL = AL + CL - 1 = 4

NOPWRITE n

NOP

n + 1

NOP

n + 2

n + 3

NOP

DON’T CARETRANSITIONING DATA

Bit E7 (A7) must be programmed as “1” to provide a faster refresh rate on IT devices if the T

CASE exceeds 85°C.

EMR2 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specif ie d ti me tion. Violating either of these requiremen ts could result in unspecified operation.

Figure 15: Extended Mode Register 2 (EMR2) Definition

BA2

M15

A13

MRS

M14

0 1

0* 0*

Mode Register Set

Mode Register Set (MRS)

Extended Mode Register (EMRS)

Extended Mode Register (EMRS2)

Extended Mode Register (EMRS3)

Notes: 1. E13 (A13)–E8 (A8) and E6 (A6)–E0 (A0) are reserved for future use and must all be pro-

grammed to “0.” A13 is not used in x16 configuration.

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

A10A12 A11BA0BA1

9765438210

10111213

0* 0*

* E16 and E13 (A13) - E0 (A0) are reserved for future

MRD before initiating any subsequent opera-

Address Bus

Extended Mode

0* 0*

use and must all be programmed to '0'.

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Page 33

Extended Mode Register 3

The extended mode register 3 (EMR3) controls functions beyond those controlled by the mode register. Currently all bits in EMR3 are reserved, as shown in Figure16 on page 33. The EMR3 is programmed via the LM command and will retain the stored information until it is programmed again or the device loses po wer. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly.

1Gb: x4, x8, x16 DDR2 SDRAM

Extended Mode Register 3

EMR3 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specif ie d ti me tion. Violating either of these requiremen ts could result in unspecified operation.

Figure 16: Extended Mode Register 3 (EMR3) Definition

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

BA2

M15

A13

1415

MRS

M14

0 1

Mode Register Set (MRS)

Extended Mode Register (EMRS)

Extended Mode Register (EMRS2)

Extended Mode Register (EMRS3)

Notes: 1. E13 (A13)–E0 (A0) are reserved for future use and must all be programmed to “0.” A13 is

not used in x16 configuration.

A10A12 A11BA0BA1

9765438210

10111213

0* 0*

Mode Register Set

0* 0*

* E16 and E13 (A13) - E0 (A0) are reserved for future

MRD before initiating any subsequent opera-

Address Bus

Extended Mode

0* 0*

use and must all be programmed to '0'.

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Page 34

Command Truth Tables

The following tables provide a quick reference of DDR2 SDRAM available commands, including CKE power-down modes and bank-to-bank commands.

Table 6: Truth Table – DDR2 Commands

Notes: 1, 5, and 6 apply to all

1Gb: x4, x8, x16 DDR2 SDRAM

Command Truth Tables

Function

LOAD MODE REFRESH SELF REFRESH entry SELF REFRESH exit

Single bank PRECHARGE

All banks PRECHARGE

Bank activate WRITE

WRITE with auto precharge

READ

READ with auto precharge

NO OPERATION Device DESELECT Power-down entry

Power-down exit

CKE

Cycle

H H L L L L BA OP Code 2 HHLLLHXXXX HLLLLHXXXX

LHHXXXXXXX7

HHLLHLBAXLX2

HHLLHLXXHX

H H L L H H BA Row Address H H L H L L BA Column

H H L H L L BA Column

H H L H L H BA Column

HXLHHHXXXX HXHXXXXXXX HLHXXXXXXX 4

LHHXXXXXXX4

Current

Cycle

CS# RAS# CAS# WE#

LHHH

BA2 BA1 BA0

A13, A12,

A11 A10 A9–A0 Notes

L Column

Address

H Column

Address

L Column

Address

H Column

Address

2, 3

Notes: 1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the

rising edge of the clock.

2. Bank addresses (BA) BA0–BA2 determine whic h bank is to be operated upon. BA during a LM command selects which mode register is programmed.

3. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See Figure 24 on page 45 and Figure 38 on page 58 for other restrictions and details.

4. The power-down mode does not perform any REFRESH operations. The duration of powerdown is limited by the refresh requirements outlined in the AC parametric section.

5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. See “ODT Timing” on page79 for details.

6. “X” means “H or L” (but a defined logic level).

7. SELF REFRESH exit is asynchronous.

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Page 35

1Gb: x4, x8, x16 DDR2 SDRAM

Command Truth Tables

Table 7: Truth Table – Current State Bank n – Command to Bank n

Notes: 1–6; notes appear below and on next page

Current State CS# RAS# CAS# WE# Command/Action Notes

Any

Idle

Row active

Read (autoprecharge Disabled

Write (autoprecharge disabled)

HXXX

LHHH

DESELECT (NOP/continue previous operation) NO OPERA T IO N (NOP/c on tinue previous

operation) LLHH LLLH LLLL LHLH LHLL LLHL LHLH LHLL LLHL LHLH LHLL LLHL

ACTIVE (select and activate row)

REFRESH

LOAD MODE

READ (select column and start READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE (deactivate row in bank or banks)

READ (select column and start new READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE (start PRECHARGE)

READ (select column and start READ burst)

WRITE (select column and start new WRITE burst)

PRECHARGE (start PRECHARGE)

7 7 9 9 8 9

9, 10

8 9 9 8

Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSNR has been met

(if the previous state was self refresh).

2. This table is bank-specific, except where noted (the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state). Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged,

complete.

Row active: A row in the bank has been activated, and

RP has been met, and any READ burst is

RCD has been met. No data bursts/

accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not

yet terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not

yet terminated.

4. The following states must not be interrupted by a command issued to the same bank. Issue DESELECT or NOP commands, or allowable commands to the other bank, on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and this table, and according to Table 8 on page 37.

Precharging: Starts with registration of a PRECHARGE command and ends when

is met. Once

Read with auto precharge enabled:

Starts with registration of a READ command with auto precharge enabled and ends when will be in the idle state.

Row activating: Starts with registration of an ACTIVE command and ends when

RP is met, the bank will be in the idle state.

RP has been met. Once tRP is met, the bank

RCD is

met. Once tRCD is met, the bank will be in the “row active” state.

Write with auto precharge enabled:

Starts with registration of a WRITE command with auto precharge enabled and ends when

RP has been met. Once tRP is met, the bank

will be in the idle state.

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Page 36

1Gb: x4, x8, x16 DDR2 SDRAM

Command Truth Tables

5. The following states must not be interrupted by any executable command (DESELECT or NOP commands must be applied on each positive clock edge during these states):

Refreshing: Starts with registration of a REFRESH command and ends when

met. Once

Accessing mode register:

Starts with registration of the LM command and ends when tMRD has been met. Once

RFC is met, the DDR2 SDRAM will be in the all banks idle state.

MRD is met, the DDR2 SDRAM will be in the all banks idle

state.

Precharging all: Starts with registration of a PRECHARGE ALL command and ends when

RP is met. Once tRP is met, all banks will be in the idle state.

6. All states and sequenc es not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle and bursts are not in progress.

8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.

9. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.

10. A WRITE command may be applied after the completion of the READ burst.

RFC is

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Page 37

1Gb: x4, x8, x16 DDR2 SDRAM

Command Truth Tables

Table 8: Truth Table – Current State Bank n – Command to Bank m

Notes: 1–6; notes appear below and on next page

Current State CS# RAS# CAS# WE# Command/Action Notes

Any

Idle Row Activating,

Active, or Precharging

Read (auto precharge disabled

Write (auto precharge disabled.)

Read (with autoprecharge)

Write (with autoprecharge)

HXXX

LHHH

XXXX

LLHH LHLH LHLL LLHL LLHH LHLH LHLL LLHL LLHH LHLH LHLL LLHL LLHH LHLH LHLL LLHL LLHH LHLH LHLL LLHL

DESELECT (NOP/continue previous operation) NO OPERA T IO N (NOP/c ontinue previous operation) Any command otherwise allowed to bank m ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE

7 7

7, 9

7, 8

7, 3

7, 9, 3

7, 3 7, 3

Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSNR has been met

(if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged,

complete.

Row active: A row in the bank has been activated and

RP has been met, and any READ burst is

RCD has been met. No data bursts/

accesses and no register accesses are in progress.

Read: A READ burst has been initiated with auto precharge disabled, and has not yet

terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet

terminated.

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Page 38

1Gb: x4, x8, x16 DDR2 SDRAM

Command Truth Tables

READ with auto precharge enabled/ WRITE with auto precharge enabled:

The READ with auto precharge enabled or WRITE with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. For READ with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For WRITE with auto precharge, the precharge period begins when

WR ends, with tWR measured as if auto precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or

RP) begins. This device supports concurrent auto precharge such that when a READ with auto precharge is enabled or a WRITE with auto precharge is enabled, any command to other banks is allowed, as long as that command does not interrupt the read or write data transfer already in process. In either case, all other related limitations apply (contention between read data and write data must be avoided).

– The minimum delay from a READ or WRITE command with auto precharge

enabled to a command to a different bank is summarized in Table 9:

Table 9: Minimum Delay with Auto Precharge Enabled

From Command

(Bank n) To Command (Bank m)

WRITE with auto

precharge

READ with auto

precharge

READ or READ with auto

precharge

WRITE or WRITE with auto

precharge

PRECHARGE or ACTIVE 1

READ or READ with auto

precharge

WRITE or WRITE with auto

precharge

PRECHARGE or ACTIVE 1

Minimum Delay

(with concurrent

auto precharge) Units

(CL - 1) + (BL / 2) +

WTR

(BL / 2)

(BL / 2) + 2

t t

CK CK

4. REFRESH and LM commands may only be issued when all banks are idle.

5. Not used.

6. All states and sequenc es not shown are illegal or reserved.

7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.

8. Requires appropriate DM.

9. A WRITE command may be applied after the completion of the READ burst.

10. The number of clock cycles required to meet

WTR is either 2 or tWTR/tCK, whichever is

greater.

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Page 39

DESELECT, NOP, and LM Commands

DESELECT

The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in progress are not affected. DESEL ECT is also referred to as COMMAND INHIBIT.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to perform a NOP (CS# is LOW; RAS#, CAS#, and WE are HIGH). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.

LOAD MODE (LM)

The mode registers are loaded via inputs BA2–BA0 and A13–A0 for x4 and x8, and A12–A0 for x16 configurations. BA2–BA0 determine which mode register will be programmed. See “Mode Register (MR)” on page 24. The LM command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until met.

1Gb: x4, x8, x16 DDR2 SDRAM

DESELECT, NOP, and LM Commands

MRD is

Bank/Row Activation

ACTIVE Command

The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA2–BA0 inputs selects the bank, and the address provided on inputs (A13–A0 for x4 and x8, and A12–A0 for x16) selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank.

ACTIVE Operation

Before any READ or WRITE commands can be issued to a bank within the DDR2 SDRAM, a row in that bank must be opened (activated), even when additive latency is used. This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated, as shown in Figure 17 on page 40.

After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row subject to the the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. The same procedure is used to convert other specification limits from time units to clock cycles. For example, a clock ( page 42, which covers any case where 5 < case for

RCD specification. tRCD (MIN) should be divided by

CK = 3.75ns) results in 5.3 clocks, rounded up to 6. This is reflected in Figure20 on

RRD where 2 < tRRD (MIN) / tCK ≤ 3.

RCD (MIN) specification of 20ns with a 266 MHz

RCD (MIN) / tCK ≤ 6. Figure 20 also shows the

A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by

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RC.

Page 40

A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results i n a reduction of total ro w-acces s o verhead. The mini mum time interval between successive ACTIVE commands to different banks is defined by

RRD.

Figure 17: ACTIVE Command

1Gb: x4, x8, x16 DDR2 SDRAM

Bank/Row Activation

CK#

CKE

CS#

RAS#

CAS#

WE#

ADDRESS

BANK ADDRESS

DON’T CARE

DDR2 SDRAM also supports the AL f eatur e, which allows a READ or WRITE command to be issued prior to command to the internal device by AL clock cycles.

No more than 4-bank ACTIVE commands may be issued in a given

RRD (MIN) restriction still applies. The tFAW (MIN) parameters apply to all 8-bank DDR2 devices, regardless of the number of banks already open or closed, as shown in Figure18 .

Figure 18: 8-Bank Activate Restriction

CK#

COMMAND

ADDRESS

BA0, BA1, BA2

Row

Bank a Bank b

T1T0 T2 T3 T4 T5 T6 T7

READACT ACT NOP

Col

Bank a

RRD (MIN)

Row

Col

Bank b

Row

Bank

RCD (MIN) by delaying the actual registration of the READ/WRITE

FAW (MIN) period.

T10

ACT

Row

Bank e

ACTREAD READ READACT NOP

Row

Bank c

FAW (MIN)

Col

Bank c

Row

Bank d

Col

Bank d

T8 T9

DON’T CARE

Notes: 1. 8-bank DDR2-533 (-37E, x4 or x8), tCK = 3.75ns, BL = 4, AL = 3, CL = 4, tRRD (MIN) = 7.5ns,

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FAW (MIN) = 37.5ns.

Page 41

READ Command

READ Operation

1Gb: x4, x8, x16 DDR2 SDRAM

READ Command

The READ command is used to initiate a burst re ad access to an active row. The value on the BA2–BA0 inputs selects the bank, and the address provided on inputs A 0–i (wher e i = A9 for x16, A9 for x8, or A9, A11 for x4) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be pr e char ged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses.

READ bursts are initiated with a READ command, as shown in Figure 19 on page 42. The starting column and bank addresses are provided with the READ com mand an d auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accesse d is automatically precharged at the completion of the burst. If auto precharge is disabled, the row will be left open after the completion of the burst.

During READ bursts, the valid data-out element from the starting column address will be available READ latency (RL) clocks later. RL is defined as the sum of AL and CL; RL = AL + CL. The value for AL and CL are programmable via the MR and EMR commands, respectively. Each subseque nt data-out element will be valid nominally at the next positive or negative clock edge (i.e., at the next crossing of CK and CK#). Figure21 on page 43 shows examples of RL based on different AL and CL settings.

DQS/DQS# is driven by the DDR2 SDRAM along with output data. The initial LOW state on DQS and HIGH state on DQS# is known as the read preamble ( on DQS and HIGH state on DQS# coincident with the last data-out element is known as the read postamble (

Upon completion of a burst, assuming no other commands have been initiated, the DQ will go High-Z. A detailed explanation of window hold), and the valid data window are depicted in Figure30 on page 51 and Figure31 on page 52. A detailed explanation of

AC (data-out transition skew to CK) is shown in Figure 32 on page 53.

RPST).

DQSQ (valid data-out skew), tQH (data-out

DQSCK (DQS transition skew to CK) and

RPRE). The LOW state

Data from any READ burst may be concatenated with data from a subsequent READ command to provide a continuous flow of data. The first data element from the new burst follows the last element of a completed burst. The new READ command should be issued x cycles after the first READ command, where x equals BL / 2 cycles. This is sho wn in Figure22 on page 44.

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Page 42

Figure 19: READ Command

1Gb: x4, x8, x16 DDR2 SDRAM

READ Command

CK#

CKE

CS#

RAS#

CAS#

WE#

AUTO PRECHARGE

BANK ADDRESS

Figure 20: Example: Meeting

CK#

COMMAND

ADDRESS

BA0, BA1, BA2

Row Row

Bank x Bank y

T1T0 T2 T3 T4 T5 T6 T7

NOPACT NOP NOPACT NOP NOP RD/WR

RRD

ADDRESS

Col

ENABLE

A10

DISABLE

Bank

DON’T CARE

RRD (MIN) and tRCD (MIN)

RCD

NOP

DON’T CARE

Col

Bank y

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Page 43

Figure 21: READ Latency

1Gb: x4, x8, x16 DDR2 SDRAM

READ Command

CK#

COMMAND

ADDRESS

DQS, DQS#

CK#

COMMAND

ADDRESS

DQS, DQS#

CK#

COMMAND

ADDRESS

DQS, DQS#

T0 T1 T2 T3 T3n T4nT4 T5

READ NOP NOP NOP NOP NOP

Bank a,

Col n

T0 T1 T2 T3 T4n T5nT4 T5

READ NOP NOP NOP NOP NOP

Bank a,

Col n

T0 T1 T2 T3 T3n T4nT4 T5

READ NOP NOP NOP NOP NOP

Bank a,

Col n

RL = 3 (AL = 0, CL = 3)

AL = 1

CL = 3

RL = 4 (AL = 1 + CL = 3)

RL = 4 (AL = 0, CL = 4)

DON’T CARE

TRANSITIONING DATA

Notes: 1. DO n = data-out from column n.

2. BL = 4.

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Shown with nominal

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AC, tDQSCK, and tDQSQ.

Page 44

Figure 22: Consecutive READ Bursts

1Gb: x4, x8, x16 DDR2 SDRAM

READ Command

CK#

COMMAND

ADDRESS

DQS, DQS#

CK#

COMMAND

ADDRESS

DQS, DQS#

T0 T1 T2 T3 T3n T4nT4 T5 T6

READ NOP READ NOP NOP NOP NOP Bank,

Col n

T0 T1 T2 T3T2n

READ NOP READ NOP NOP NOP Bank,

Col n

CCD

RL = 3

CCD

RL = 4

Bank, Col b

T3n T4nT4 T5 T6

DON’T CARE TRANSITIONING DATA

T5n T6n

NOP

Notes: 1. DO n (or b) = data-out from column n (or column b).

2. BL = 4.

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Three subsequent elements of data-out appear in the programmed order following DO b.

5. Shown with nominal

AC, tDQSCK, and tDQSQ.

6. Example applies only when READ commands are issued to same device.

Nonconsecutive read data is illustrated in Figure 23 on page 45. Full-speed random read accesses within a page (or pages) can be performed. DDR2 SDRAM supports the use of concurrent auto precharge timing, shown in Table 10 on page 46.

DDR2 SDRAM does not allow interrupting or truncating of any READ burst using BL = 4 operations. Once the BL = 4 READ command is registered, it must be allowed to complete the entire READ burst. However, a READ (with auto precharge disabled) using BL = 8 operation may be interrupted and truncated only by another READ burst as long as the interruption occurs on a 4-bit boundary due to the 4n prefetch architecture of DDR2 SDRAM. READ burst BL = 8 operations may not be interrupted or truncated with any command except another READ command, as shown in Figure24 on page 45.

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Page 45

Figure 23: Nonconsecutive READ Bursts

1Gb: x4, x8, x16 DDR2 SDRAM

READ Command

CK#

COMMAND

ADDRESS

DQS, DQS#

CK#

COMMAND

ADDRESS

DQS, DQS#

T0 T1 T2 T3 T3n T4 T5 T7 T8T6T4n T6n T7n

READ NOP NOP NOP NOP NOP NOP NOP

Bank, Col n

T0 T1 T2 T3 T4

READ NOP NOP NOP

Bank, Col n

CL = 3

CL = 4

READ

Bank, Col b

READ

Bank, Col b

DON’T CARE TRANSITIONING DATA

Notes: 1. DO n (or b) = data-out from column n (or column b).

2. BL = 4.

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Three subsequent elements of data-out appear in the programmed order following DO b.

5. Shown with nominal tAC, tDQSCK, and tDQSQ.

6. Example applies when READ commands are issued to different devices or nonconsecutive

READs.

T5 T7 T8T5n T6T4n T7n

NOP NOP NOP NOP

Figure 24: READ Interrupted by READ

CK#

COMMAND

ADDRESS

A10

DQS, DQS#

T0 T1 T2

READ

VALID

NOP

CL = 3 (AL = 0)

CCD

Notes: 1. BL = 8 required; auto precharge must be disabled (A10 = LOW).

2. READ command can be issued to any valid bank and row address (READ command at T0 and

3. Interrupting READ command must be issued exactly 2 x tCK from previous READ.

4. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the inter-

5. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command cannot be issued to

6. Example shown uses AL = 0; CL = 3, BL = 8, shown with nominal

READ

VALID

T2 can be either same bank or different bank).

rupting READ command.

banks used for READs at T0 and T2.

T3 T4 T5

NOP

CL = 3 (AL = 0)

VALID VALID

OUT

OUTDOUTDOUTDOUTDOUT

VALID

OUTDOUTDOUT

T7 T8 T9

VALID VALID VALID

OUTDOUTDOUT

AC, tDQSCK, and tDQSQ.

DON’T CARETRANSITIONING DATA

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Page 46

Table 10: READ Using Concurrent Auto Precharge

From

Command

(Bank n)

READ with

auto

precharge

READ or READ with auto precharge BL/2

WRITE or WRITE with auto precharge (BL/2) + 2

To Command

(Bank m)

PRECHARGE or ACTIVE 1

Data from any READ burst must be completed before a subsequent WRITE burst is allowed. An example of a READ burst followed by a WRITE burst is shown in Figure 27 on page 48. The

time. (

DQSS (MIN) case is shown; the tDQSS (MAX) case has a longer bus idle

DQSS [MIN] and tDQSS [MAX] are defined in Figure34 on page 56.)

A READ burst may be followed by a PRECHARGE command to the same bank, provided that auto precharge was not activated. The minimum READ-to-PRECHARGE command spacing to the same bank is AL + BL/2 clocks and must also satisfy a minimum analog time from the rising clock edge that initiates the last 4-bit prefetch of a READ-toPRECHARGE command. This READ-to-PRECHARGE time is called is the time from the actual READ (AL after the READ command) to PRECHARGE command. For BL = 8 this is the time from AL + 2CK after the READ-to-PRECHARGE command. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until

RP is met.

Note: Part of the row precharge time is hidden during the access of the last data elements.

1Gb: x4, x8, x16 DDR2 SDRAM

READ Command

Minimum Delay (with

Concurrent Auto Precharge)

Units

RTP. For BL = 4 this

Examples of READ-to-PRECHARGE are shown in Figure 25 on page 47 for BL = 4 and Figure26 on page 47 for BL = 8. The delay from READ-to-PRECHARGE command to the same bank is AL + BL/2 + MAX (

RTP/tCK or 2CK) - 2CK.

If A10 is HIGH when a READ command is issued, the READ with auto precharge function is engaged. The DDR2 SDRAM starts an auto precharge operation on the rising edge, which is AL + (BL/2) cycles later than the READ with auto precharge command if (MIN) and auto precharge operation will be delayed until

RTP are satisfie d. If tRAS (MIN) is not satisfied at the edge, the start point of

RAS (MIN) is satisfied. If tRTP (MIN) is

RAS

not satisfied at the edge, the start point of the auto precharge operation will be delayed

until

RTP (MIN) is satisfied. In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens (not at the next rising clock edge after this event). For BL = 4, the minimum time from READ with auto precharge to the next ACTIVATE command becomes AL + ( page 47; for BL = 8, the time from READ with auto precharge to the next ACTIVATE command is AL + 2 clocks + (

RTP + tRP)*, shown in Figure26 on page 47. The asterisk (*)

indicates each parameter term is divided by

RTP + tRP)*, shown in Figure 25 on

CK and rounded up to the next integer. In any event, internal precharge does not start earlier than two clocks after the last 4-bit prefetch.

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Page 47

Figure 25: READ-to-PRECHARGE – BL = 4

T0 T1 T2

CK#

COMMAND

ADDRESS

DQS, DQS#

READ

AL + BL/2 + MAX(tRTP/tCK or 2CK) - 2CK

Bank a

A10

AL = 1

4-bit prefetch

NOP

≥tRTP (MIN)

≥tRAS (MIN)

1Gb: x4, x8, x16 DDR2 SDRAM

T3 T4 T5 T6

PRECHG

Bank a

Valid

CL = 3

≥tRC (MIN)

NOP NOP

OUT

OUTDOUTDOUT

≥tRP (MIN)

READ Command

ACTIVE

Bank a

Valid

NOP

DON’T CARETRANSITIONING DATA

Notes: 1. RL = 4 (AL = 1, CL = 3); BL = 4.

RTP ≥ 2 clocks.

3. Shown with nominal

Figure 26: READ-to-PRECHARGE – BL = 8

first 4-bit

T0 T1 T2

CK#

COMMAND

ADDRESS

DQS, DQS#

READ

Bank a

A10

Notes: 1. RL = 4 (AL = 1, CL = 3); BL = 8.

RTP ≥ 2 clocks.

3. Shown with nominal

prefetch

NOP

AL = 1

AC, tDQSCK, and tDQSQ.

second 4-bit prefetch

T3 T4 T5 T6 T7 T8

NOP

AL + BL/2 + MAX(tRTP/tCK or 2CK) -2CK

CL = 3

≥tRAS (MIN)

AC, tDQSCK, and tDQSQ.

NOP

≥tRTP (MIN)

≥tRC (MIN)

NOP

PRECHG

Bank a

Valid

DOUT

DOUT DOUT DOUT DOUT DOUT DOUT DOUT

NOP

≥tRP (MIN)

NOP

ACTIVE

Bank a

Valid

DON’T CARETRANSITIONING DATA

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Page 48

Figure 27: READ-to-WRITE

1Gb: x4, x8, x16 DDR2 SDRAM

READ Command

CK#

COMMAND

DQS, DQS#

T0 T1 T2

ACTIVE n

READ n

RCD = 3

Notes: 1. BL = 4; CL = 3; AL = 2.

T3 T4 T5

NOP

AL = 2

NOP

NOP NOP

NOP WRITE n

RL = 5

2. Shown with nominal

WRITE

CL = 3

AC, tDQSCK, and tDQSQ.

NOP

OUT

T7 T8

NOP NOP NOP

WL = RL - 1 = 4

OUT

n + 2

OUT

n + 3

OUT

n + 1

T9 T10 T11

NOP NOP

n + 1

DON’T CARETRANSITIONING DATA

n + 2

n + 3

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Page 49

Figure 28: Bank Read – without Auto Precharge

1Gb: x4, x8, x16 DDR2 SDRAM

READ Command

CK#

CKE

COMMAND

ADDRESS

A10

BA0, BA1, BA2

Case 1: tAC (MIN)

DQS, DQS#

NOP

and tDQSCK (MIN)

ACT

RA Col n

Bank x

T2 T3 T4 T5 T7n T8nT6 T7 T8

CHtCL

RCD

RAS

NOP

READ

Bank x

CL = 3

NOP

RTP

LZ (MIN)

PRE

ALL BANKS

ONE BANK

RPRE

LZ (MIN)

NOP

DQSCK (MIN)

n t

AC (MIN)

NOP

HZ (MIN)

RPST

ACT

Bank xBank x

Case 2: tAC (MAX) and tDQSCK (MAX)

DQS, DQS#

LZ (MAX)

LZ (MIN)

DON’T CARE

RPRE

DQSCK (MAX)

AC (MAX)

RPST

HZ (MAX)

TRANSITIONING DATA

Notes: 1. DO n = data-out from column n; subsequent elements are applied in the programmed

order .

2. BL = 4 and AL = 0 in the case shown.

3. Disable auto precharge.

4. “Don’t Care” if A10 is HIGH at T5.

5. PRE = PRECHARGE, ACT = ACTIVE, RA = row address, BA = bank address.

6. NOP commands are shown for ease of illustration; other commands may be valid at these

times.

7. The PRECHARGE command can only be applied at T6 if

8. READ-to-PRECHARGE = AL + BL/2 + (

RTP - 2 clocks).

RAS (MIN) is met.

9. I/O balls, when entering or exiting HIGH-Z, are not referenced to a specific voltage level,

but to when the device begins to drive or no longer drives, respectively.

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Page 50

Figure 29: Bank Read – with Auto Precharge

1Gb: x4, x8, x16 DDR2 SDRAM

READ Command

CK#

CKE

COMMAND

ADDRESS

A10

BA0, BA1, BA2

Case 1: tAC (MIN)

DQS, DQS#

NOP

and tDQSCK (MIN)

ACT

Bank x

T2 T3 T4 T5 T7n T8nT6 T7 T8

RCD

RAS t

NOP

CHtCL

READ

Col n

Bank x

2,6

AL = 1

NOP

RTP

CL = 3

LZ (MIN)

NOP

RPRE

LZ (MIN)

NOP

DQSCK (MIN)

AC (MIN)

NOP

HZ (MIN)

ACT

Bank x

RPST

Case 2: tAC (MAX) and tDQSCK (MAX)

DQS, DQS#

LZ (MAX)

4-bit prefetch

Internal precharge

LZ (MAX)

RPRE

DON’T CARE

DQSCK (MAX)

AC (MAX)

RPST

HZ (MAX)

TRANSITIONING DATA

Notes: 1. DO n = data-out from column n; subsequent elements are applied in the programmed

order .

2. BL = 4, RL = 4 (AL = 1, CL = 3) in the case shown.

3. Enable auto precharge.

4. ACT = ACTIVE, RA = row address, BA = bank address.

5. NOP commands are shown for ease of illustration; other commands may be valid at these

times.

6. The DDR2 SDRAM internally delays auto precharge until both

RAS (MIN) and tRTP (MIN)

have been satisfied.

7. I/O balls, when entering or exiting HIGH-Z, are not referenced to a specific voltage level,

but to when the device begins to drive or no longer drives, respectively.

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Page 51

1Gb: x4, x8, x16 DDR2 SDRAM

Figure 30: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window

T1 T2 T3 T4T2n T3n

CK#

DQSQ

DQS#

DQS

DQSQ

READ Command

DQSQ

DQ (Last data valid)

DQ DQ DQ DQ DQ DQ

2 2 2 2 2 2

DQ (First data no longer valid)

T2n T2n

T2n

T3 T3

T3n

DQ (Last data valid)

DQ (First data no longer valid)

All DQs and DQS, collectively

Earliest signal transition

Latest signal transition

Data

Valid

Window

Data

Valid

Window

Data Valid

Window

Data

Valid

Window

Notes: 1. DQ transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at

T2n are “early DQS,” at T3 are “nominal DQS,” and at T3n are “late DQS.”

2. DQ0, DQ1, DQ2, DQ3 for x4 or DQ0–DQ7 for x8.

DQSQ is derived at each DQS clock edge, is not cumu lative over time, begins with DQS

transitions, and ends with the last valid transition of DQ.

QH is derived from tHP: tQH = tHP - tQHS.

HP is the lesser of tCL or tCH clock transitions collectively when a bank is active.

6. The data valid window is derived for each DQS transition and is defined as

QH - tDQSQ.

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Page 52

1Gb: x4, x8, x16 DDR2 SDRAM

Figure 31: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window

T1 T2 T3 T4T2n T3n

CK#

LDSQ# LDQS

DQSQ

READ Command

DQ (Last data valid)

DQ (First data no longer valid)

DQ (Last data valid)

DQ (First data no longer valid)

DQ0–DQ7 and LDQS, collectively

DQ (Last data valid)

DQ (First data no longer valid)

DQ (Last data valid)

DQ (First data no longer valid)

DQ8–DQ15 and UDQS, collectively

DQ DQ DQ DQ DQ DQ

UDQS# UDQS

DQ DQ DQ DQ DQ DQ

2 2 2 2 2 2 2

7 7 7 7 7 7 7

DQSQ

Data Valid

Window

T2n

Data Valid

Window

DQSQ

T2n

Data Valid

Window

DQSQ

Data Valid

Window

T3n

Lower Byte

Upper Byte

Data Valid

Window

Data Valid

Window

Data Valid

Window

Data Valid

Window

Notes: 1. DQ transitioning after DQS transitions define the tDQSQ window. LDQS defines the lower

byte, and UDQS defines the upper byte.

2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.

3.tDQSQ is derived at each DQS clock edge, is not cumu lative over time, begins with DQS

transitions, and ends with the last valid transition of DQ.

QH is derived from tHP: tQH = tHP - tQHS.

HP is the lesser of tCL or tCH clock transitions collectively when a bank is active.

6. The data valid window is derived for each DQS transition and is

QH - tDQSQ.

7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.

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Page 53

Figure 32: Data Output Timing – tAC and tDQSCK

CK#

T1 T2 T3 T3n T4 T4n T5 T5n T6 T6n

LZ (MIN)

DQSCK1 (MIN)

1Gb: x4, x8, x16 DDR2 SDRAM

READ Command

DQSCK1 (MAX)

HZ (MAX)

LDQS#/LDQS / UDQ#/UDQS

DQS#/DQS, or

DQ (Last data valid)

DQ (First data valid)

All DQs, collectively

Notes: 1.tDQSCK is the DQS output window relative to CK and is the “long-term” component of DQS

HZ (MAX)

RPST

T6n

RPRE

T3T3T3n T4n T5n T6n

T3n

LZ (MIN)

T3n

T3 T4 T5 T6

tAC4

(MIN)

T4n T4n

tAC4

(MAX)

T5n

skew.

2. DQ transitioning after DQS transitions define

3. All DQ must transition by

AC is the DQ output window relative to CK and is the “long term” component of DQ skew.

LZ (MIN) and tAC (MIN) are the first valid signal transitions.

HZ (MAX) and tAC (MAX) are the latest valid signal transitions.

DQSQ after DQS transitions, regardless of tAC.

DQSQ window.

7. READ command with CL = 3, AL = 0 issued at T0.

8. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level, but

to when the device begins to drive or no longer drives, respectively.

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Page 54

WRITE Command

The WRITE command is used to initiate a burst write access to an active row. The value on the BA2–BA0 inputs selects the bank, and the address provid ed on inputs A0–i (wher e i = A9 for x8 and x16; or A9, A11 for x4) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the ro w will remain open for subsequent accesses.

Figure 33: WRITE Command

CK#

CKE

CS#

RAS#

CAS#

1Gb: x4, x8, x16 DDR2 SDRAM

WRITE Command

HIGH

Notes: 1. CA = column address; BA = bank address; EN AP = enable auto precharge; and DIS AP = dis-

WRITE Operation

WE#

ADDRESS

A10

BANK ADDRESS

EN AP

DIS AP

DON’T CARE

able auto precharge.

Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal i s r egister ed L O W, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location (Figure43 on page 63).

WRITE bursts are initiated with a WRITE command, as shown in Figure33. DDR2 SDRAM uses WL equal to RL minus one clock cycle [WL = RL - 1CK = AL + (CL - 1CK)]. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that acc ess . If auto pr e charge is enab led, the row being accessed is precharged at the completion of the burst.

Note: For the generic WRITE commands used in the following il lustrations, auto precharge

is disabled.

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Page 55

1Gb: x4, x8, x16 DDR2 SDRAM

WRITE Command

During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and subsequent data elements will be registered on successive edges of DQS. The LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is known as the write postamble.

The time between the WRITE command and the first rising DQS edge is WL ± Subsequent DQS positive rising edg es are timed, relative to the associated clock edge , as

DQSS. tDQSS is specified with a relatively wide range (25 percent of one clock cycle).

All of the WRITE diagrams show the nominal case, and where the two extreme cases

(

DQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also been included.

Figure34 on page 56 shows the nominal case and the extr emes of

DQSS for BL = 4. Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain High-Z and any additional input data will be ignored.

Data for any WRITE burst may be concatenated with a subsequent WRITE command to provide continuous flow of input data. The first data element from the new burst is applied after the last element of a completed burst. The new WRITE command shou ld be issued x cycles after the first WRITE command, where x equals BL/2.

Figure35 on page 57 shows concatenated bursts of BL = 4. An example of nonconsecutive WRITEs is shown in Figure 36 on page 57. Full-speed random write accesses within a page or pages can be performed as shown in Figure 37 on page 58. DDR2 SDRAM supports concurrent auto precharge options, as shown in Table11.

DQSS.

DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4 operation. Once the BL = 4 WRITE command is registered, it must be allowed to complete the entire WRITE burst cycle. However, a WRITE BL = 8 operation (with auto precharge disabled) might be interrupted and trun cat ed ONLY by another WRITE burst as long as the interruption occurs on a 4-bit boundary, due to the 4n prefetch architecture of DDR2 SDRAM. WRITE burst BL = 8 operations may not be interrupted or truncated with any command except another WRITE command, as shown in Figure38 on page 58.

Data for any WRITE burst may be followed by a subsequent READ command. To follow a WRITE, cycles required to meet

WTR should be met, as shown in Figure 39 on page 59. The number of clock

WTR is either 2 or tWTR/tCK, whichever is greater. Data for any WRITE burst may be followed by a subsequent PRECHARGE command. met, as shown in Figure40 on page 60. of the data mask condition.

Table 11: WRITE Using Concurrent Auto Precharge

From Command

(Bank n)

WRITE with auto

precharge

To Command

(Bank m)

READ or READ with auto

precharge

WRITE or WRITE with

auto precharge

PRECHARGE or ACTIVE 1

WR starts at the end of the data burst, regardless

Minimum Delay

(with concurrent

auto precharge) Units

(CL - 1) + (BL/2) +

(BL/2)

WTR

WR must be

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Page 56

Figure 34: WRITE Burst

1Gb: x4, x8, x16 DDR2 SDRAM

WRITE Command

CK#

COMMAND

ADDRESS

DQSS (NOM)

DQS, DQS#

DQSS (MIN)

DQS, DQS#

DQSS (MAX)

DQS, DQS#

T0 T1 T2 T3T2n T4T3n

WRITE NOP NOP

Bank a,

Col b

WL ± tDQSS

WL - tDQSS

WL + tDQSS

NOP NOP

DQSS

Notes: 1. DI b = data-in for column b.

2. Three subsequent elements of data-in are applied in the programmed order following

DI b.

3. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.

4. A10 is LOW with the WRITE command (auto precharge is disabled).

5. Subsequent rising DQS signals must align to the clock within

DON’T CARE TRANSITIONING DATA

DQSS.

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Page 57

Figure 35: Consecutive WRITE-to-WRITE

1Gb: x4, x8, x16 DDR2 SDRAM

WRITE Command

CK#

COMMAND

ADDRESS

DQSS (NOM)

DQS, DQS#

T0 T1 T2 T3T2n T4 T5T4n T6T5nT3nT1n

WRITE NOP WRITE NOP NOP NOP

CCD

WL = 2

Bank,

Col b

WL ±

DQSS

Bank, Col n

Notes: 1. DI b, etc. = data-in for column b, etc.

2. Three subsequent elements of data-in are applied in the programmed order following

DI b.

3. Three subsequent elements of data-in are applied in the programmed order following

DI n.

4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.

5. Each WRITE command may be to any bank.

6. Subsequent rising DQS signals must align to the clock within

NOP

WL = 2

DQSS.

DON’T CARE TRANSITIONING DATA

Figure 36: Nonconsecutive WRITE-to-WRITE

CK#

COMMAND

ADDRESS

DQSS (NOM) WL ± tDQSS

DQS, DQS#

Notes: 1. DI b, etc. = data-in for column b, etc.

2. Three subsequent elements of data-in are applied in the programmed order following

DI b.

3. Three subsequent elements of data-in are applied in the programmed order following

DI n.

4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.

5. Each WRITE command may be to any bank.

6. Subsequent rising DQS signals must align to the clock within

T0 T1 T2 T3T2n T4 T5T4nT3n T5n T6 T6n

WRITE NOP NOP NOP NOP NOP

Bank,

Col b

WL = 2

WRITE

WL = 2

Bank,

Col n

DON’T CARE TRANSITIONING DATA

DQSS.

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Page 58

Figure 37: Random WRITE Cycles

1Gb: x4, x8, x16 DDR2 SDRAM

WRITE Command

CK#

T0 T1 T2 T3T2n T4 T5T4n T6T5nT3nT1n

COMMAND

WRITE NOP WRITE NOP NOP NOP

CCD

WL = 2

ADDRESS

DQSS (NOM)

Bank,

Col b

WL ±

DQSS

Bank, Col n

DQS, DQS#

Notes: 1. DI b, etc. = data-in for column b, etc.

2. Three subsequent elements of data-in are applied in the programmed order following

DI b.

3. Three subsequent elements of data-in are applied in the programmed order following

DI n.

4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.

5. Each WRITE command may be to any bank.

6. Subsequent rising DQS signals must align to the clock within

NOP

WL = 2

DON’T CARE TRANSITIONING DATA

DQSS.

Figure 38: WRITE Interrupted by WRITE

CK#

COMMAND

ADDRESS

A10

DQS, DQS#

T0 T1 T2

WRITE

VALID

NOP

WL = 3

Notes: 1. BL = 8 required and auto precharge must be disabled (A10 = LOW).

2. WRITE command can be issued to any valid bank and row address (WRITE command at T0

and T2 can be either same bank or different bank).

3. Interrupting WRITE command must be issued exactly 2 x tCK from previous WRITE.

4. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the inter-

rupting WRITE command.

5. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command cannot be issued to

banks used for WRITEs at T0 and T2.

6. Earliest WRITE-to-PRECHARGE timing for WRITE at T0 is WL + BL/2 +

with T7 and not T5 (since BL = 8 from MR and not the truncated length).

7. Example shown uses AL = 0; CL = 4, BL = 8.

8. Subsequent rising DQS signals must align to the clock within

WRITE

VALID

T3 T4 T5 T6

NOP

DIN

T7 T8 T9

NOP

VALID

8 8888

DIN

a + 1

DIN

a + 2

DIN

a + 3

DIN

b + 1

b + 2

b + 4

b + 5

b + 3

WL = 32 clock requirement

WR where tWR starts

DQSS.

b + 6

b + 7

DON’T CARETRANSITIONING DATA

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Page 59

Figure 39: WRITE-to-READ

1Gb: x4, x8, x16 DDR2 SDRAM

WRITE Command

CK#

COMMAND

ADDRESS

DQSS (NOM)

DQS, DQS#

DQSS (MIN)

DQS, DQS#

DQSS (MAX)

DQS, DQS#

T0 T1 T2 T3T2n T4 T5 T9nT3n

WRITE NOP NOP NOP NOP NOP NOP NOP

Bank a,

Col b

WL ± tDQSS

WL - tDQSS

WL + tDQSS

NOP

DON’T CARE TRANSITIONING DATA

WTR

T6 T7 T8 T9

READ

Bank a,

Col n

CL = 3

Notes: 1. DI b = data-in for column b; DOUT n = data-out from column n.

2. BL = 4, AL = 0, CL = 3; thus, WL = 2.

3. One subsequent element of data-in is applied in the programmed order following DI b.

WTR is referenced from the first positive CK edge after the last data-in pair.

5. A10 is LOW with the WRITE command (auto precharge is disabled).

6. The number of clock cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is

greater.

WTR is required for any READ following a WRITE to the same device, but it is not required

between module ranks.

8. Subsequent rising DQS signals must align to the clock within

DQSS.

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Page 60

Figure 40: WRITE-to-PRECHARGE

1Gb: x4, x8, x16 DDR2 SDRAM

WRITE Command

CK#

COMMAND

ADDRESS

DQSS (NOM)

DQS#

DQS

DQSS (MIN)

DQS#

DQS

DQSS (MAX)

DQS#

DQS

T0 T1 T2 T3T2n T4 T5T3n

WRITE NOP NOP NOP NOPNOP

Bank a,

Col b

WL + tDQSS

WL - tDQSS

WL + tDQSS

NOP

T6 T7

PRE

Bank,

(a or all)

Notes: 1. DI b = data-in for column b.

2. Three subsequent elements of data-in are applied in the programmed order following DI b.

3. BL = 4, CL = 3, AL = 0; thus, WL = 2.

WR is referenced from the first positive CK edge after the last data-in pair.

5. The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE

and WRITE commands may be to different banks, in which case PRECHARGE command could be applied earlier.

6. A10 is LOW with the WRITE command (auto precharge is disabled).

7. PRE = PRECHARGE command.

8. Subsequent rising DQS signals must align to the clock within

DON’T CARE TRANSITIONING DATA

WR is not required and the

DQSS.

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Page 61

Figure 41: Bank Write – without Auto Precharge

1Gb: x4, x8, x16 DDR2 SDRAM

WRITE Command

CK#

CKE

COMMAND

ADDRESS

A10

BA0, BA1, BA2

DQS, DQS#

NOP

ACT

RA Col n

Bank x

T2 T3 T5 T6 T6n T7 T8 T9T5n

RCD

RAS

NOP

CHtCL

WRITE

Bank x

NOP

WL = 2

WL ± tDQSS (NOM)

NOP

WPRE

NOP

DQSLtDQSHtWPST

DON’T CARE TRANSITIONING DATA

NOP

PRE

ALL BANKS

ONE BANK

Bank x

Notes: 1. DI n = data-in from column n; subsequent elements are applied in the programmed order.

2. BL = 4, AL = 0, and WL = 2 in the case shown.

3. Disable auto precharge.

4. “Don’t Care” if A10 is HIGH at T9.

5. PRE = PRECHARGE, ACT = ACTIVE, RA = row address, BA = bank address.

6. NOP commands are shown for ease of illustration; other commands may be valid at these

times.

7.tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.

DSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.

9. Subsequent rising DQS signals must align to the clock within

DQSS.

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Page 62

Figure 42: Bank Write – with Auto Precharge

1Gb: x4, x8, x16 DDR2 SDRAM

WRITE Command

CK#

CKE

COMMAND

ADDRESS

A10

BA0, BA1, BA2

DQS,DQS#

NOP

ACT

RA Col n

Bank x

T2 T3 T4 T5 T5n T6 T7 T8T6n

RCD

RAS

NOP

tCHt

WRITE

Bank x

NOP

WL = 2

WL ± tDQSS (NOM)

NOP

WPRE

NOP

DQSLtDQSHtWPST

TRANSITIONING DATA

NOP

DON’T CARE

NOP

Notes: 1. DI n = data-in from column n; subsequent elements are applied in the programmed order.

2. BL = 4, AL = 0, and WL = 2 in the case shown.

3. Enable auto precharge.

4. ACT = ACTIVE, RA = row address, BA = bank address.

5. NOP commands are shown for ease of illustration; other commands may be valid at these

times.

DSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.

DSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.

8. WR is programmed via MR[11, 10, 9] and is calculated by dividing

CK and rounding up to the next integer value.

9. Subsequent rising DQS signals must align to the clock within

WR (in nanoseconds) by

DQSS.

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Page 63

Figure 43: WRITE – DM Operation

1Gb: x4, x8, x16 DDR2 SDRAM

WRITE Command

CK#

CKE

COMMAND

ADDRESS

A10

BA0, BA1, BA2

DQS, DQS#

NOP

ACT

RA Col n

Bank x

T2 T3 T4 T5 T7nT6 T7 T8T6n

tCHt

NOP

WL = 2

WL ± tDQSS (NOM)

WPRE

NOP

RCD

RAS

NOP

WRITE

Bank x

AL = 1

NOP

DQSLtDQSHtWPST

NOP

T9 T10 T11

NOP

ALL BANKS

ONE BANK

DON’T CARETRANSITIONING DATA

PRE

Bank x

Notes: 1. DI n = data-in from column n; subsequent elements are applied in the programmed order.

2. Burst length = 4, AL = 1, and WL = 2 in the case shown.

3. Disable auto precharge.

4. “Don’t Care” if A10 is HIGH at T11.

5. PRE = PRECHARGE, ACT = ACTIVE, RA = row address, BA = bank address.

6. NOP commands are shown for ease of illustration; other commands may be valid at these

times.

DSH is applicable during tDQSS (MIN) and is referenced from CK T6 or T7.

DSS is applicable during tDQSS (MAX) and is referenced from CK T7 or T8.

WR starts at the end of the data burst regardless of the data mask condition.

10. Subsequent rising DQS signals must align to the clock within

DQSS.

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Page 64

Figure 44: Data Input Timing

1Gb: x4, x8, x16 DDR2 SDRAM

WRITE Command

CK#

WL - tDQSS (NOM)

DQS

DQS#

T1T0 T1n T2 T2n T3 T4T3n

DSH

WPRE

TRANSITIONING DATA

Notes: 1.tDSH (MIN) generally occurs during tDQSS (MIN).

DSS (MIN) generally occurs during tDQSS (MAX).

3. WRITE command issued at T0.

4. For x16, LDQS controls the lower byte and UDQS controls the upper byte.

5. WRITE command with WL = 2 (CL = 3, AL = 0) issued at T0.

6. Subsequent rising DQS signals must align to the clock within

DSS

DQSL

DSH

DQSH

DQSS.

DSS

WPST

DON’T CARE

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Page 65

PRECHARGE Command

The PRECHARGE command, illustrated in Figure 45, is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row activation a specified time ( issued, except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the precharge period will be determined by the last PRECHARGE command issued to the bank.

PRECHARGE Operation

Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA2–BA0 select the bank. Otherwis e BA2–BA0 are treated as “Don’t Car e.”

When all banks are to be precharged , inputs BA2–BA0 ar e tr eated as “Don’ t C ar e .” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. PRECHARGE (ALL) command is issued, regardless of the number of banks already open or closed. If a single-bank PRECHARGE command is issued, (MIN) applies to all 8-bank DDR2 devices.

1Gb: x4, x8, x16 DDR2 SDRAM

PRECHARGE Command

RP) after the PRECHARGE command is

RPA timing applies when the

RP timing applies. tRPA

Figure 45: PRECHARGE Command

CK#

CKE

CS#

RAS#

CAS#

WE#

ADDRESS

A10

BA2, BA0, BA1

Notes: 1. BA = bank address (if A10 is LOW; otherwise “Don’t Care”).

HIGH

ALL BANKS

ONE BANK

DON’T CARE

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Page 66

SELF REFRESH Command

The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR2 SDRAM retains data without external clocking. All power supply inputs (including V must be maintained at valid levels upon entry/exit and during SELF REFRESH operation.

The SELF REFRESH command is initiated like a REFRESH command exc ept CKE is L O W. The DLL is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh (200 clock cycles must then occur before a READ command can be issued). The differential clock should remain stable and meet specifications at least 1 x input signals except CKE are “Don’t Care” during self refresh.

1Gb: x4, x8, x16 DDR2 SDRAM

SELF REFRESH Command

REF)

CK after entering self refr esh mode. All command and address

CKE

The procedure for exiting self refresh requires a sequence of commands. F irst, the differential clock must be stable and meet going back HIGH. Once CKE is HIGH (

CK specifications at least 1 x tCK prior to CKE

CKE [MIN] has been satisfied with four clock

registrations), the DDR2 SDRAM must have NOP or DESELECT commands issued for

XSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOP or DESELECT commands for 200 clock cycles before applying any other command.

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Page 67

1Gb: x4, x8, x16 DDR2 SDRAM

SELF REFRESH Command

Figure 46: Self Refresh

CK# CK

CKE

COMMAND

ODT

ADDRESS

DQS#,

DQS

T0 T1 Ta2Ta1

CHtCL

NOP REF

AOFD / tAOFPD

Enter self refresh mode (synchronous)

XSRD

VALID

4,6

Tc0Tb0

VALID

CKE (MIN)

Ta0

tCK1

ISXR

NOP

Exit self refresh mode (asynchronous)

CKE

XSNR

NOP

3, 6, 11

DON’T CARE

tCK1

Td0

VALID

Indicates a break in time scale

Notes: 1. Clock must be stable and meeting tCK specifications at least 1 x tCK after entering self

refresh mode and at least 1 x tCK prior to exiting self refresh mode.

2. Device must be in the all banks idle state prior to entering self refresh mode.

3.tXSNR is required before any non-READ command can be applied.

XSRD (200 cycles of CK) is required before a READ command can be applied at state Td0.

5. REF = REFRESH command.

6. Self refresh exit is asynchronous; however,

XSNR and tXSRD timing starts at the first rising

clock edge where CKE HIGH satisfies tISXR.

7. NOP or DESELECT commands are required prior to exiting self refresh until state Tc0, which

allows any non-READ command.

8. ODT must be disabled and R

TT off (

AOFD and tAOFPD have been satisfied) prior to entering

SELF REFRESH at state T1.

9. Once self refresh has been entered,

10. CKE must stay HIGH until

XSRD is met; however , if self refresh is being re-entered, CKE may

CKE (MIN) must be satisfied prior to exiting self refresh.

go back LOW after tXSNR is satisfied.

11. Once exiting SELF REFRESH, ODT must remain LOW until

XSRD is satisfied.

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Page 68

REFRESH Command

REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to CAS#-Before-RAS# (CBR) REFRESH. This command is nonpersistent, so it must be issued each time a refr esh is r equired. The addr essing is gener ated by the internal r efre sh controller. This makes the address bits a “Don’t Care” during an REFRESH command. The 1Gb DDR2 SDRAM requires REFRESH cycles at an average interval of 7.8125µs (MAX). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight REFRESH commands can be posted (to defer issuing REFRESH commands) to any given DDR2 SDRAM, meaning that the maximum absolute interval between any REFRESH command and the next REFRESH command is 9 × 7.8125µs (70.3µs; 3.9µs for hightemperature operation). The refresh period begins when the REFRESH command is registered and ends

Figure 47: Refresh Mode

RFC (MIN) later.

1Gb: x4, x8, x16 DDR2 SDRAM

REFRESH Command

CK#

CKE

COMMAND

ADDRESS

A10

BANK

DQS, DQS#

NOP

PRE

ALL BANKS

ONE BANK

Bank(s)

T2 T3

tCHt

NOP

REF NOP

Ta0

RFC(MIN)

Ta1

REF

Tb0

NOP

RFC

Indicates a break in time scale

Tb1 Tb2

NOP

DON’T CARE

ACT

Notes: 1. PRE = PRECHARGE, ACT = ACTIVE, AR = REFRESH, RA = row address, BA = bank address.

2. NOP commands are shown for ease of illustration; other valid commands may be possible at

these times. CKE must be active during clock positive transitions.

3. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active

(i.e., must precharge all active banks).

4. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.

5. The second REFRESH is not required and is only shown as an example of two back-to-back

REFRESH commands.

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Page 69

Power-Down Mode

DDR2 SDRAMs support multiple power-down modes that allow significant power savings over normal operating modes. CKE is used to enter and exit different powerdown modes. Power-down entry and exit timings are shown in Figure48 on page 70. Detailed power-down entry conditions are shown in Figures49 through 56. The CKE Truth Table, Table12, is shown on page 71.

DDR2 SDRAMs requir e CKE to be registered HIGH (active) at all times that an access is in progress—from the issuing of a READ or WRITE command until completion of the burst. Thus, a clock suspend is not supported. For READs, a burst completion is defined when the read postamble is satisfied; for WRITEs, a burst completion is defined when the write postamble and page 73. The number of clock cycles required to meet whichever is greater.

Power-down mode (see Figure48 on page 70) is entered when CKE is registered LOW coincident with a NOP or DESELECT command. CKE is not allowed to go LOW during a mode register or extended mode register command time, or while a READ or WRITE operation is in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power -down. If po wer -down occurs when there is a ro w active in any bank, this mode is referred to as active power-down. Enter i n g power-down deactivates the input and output buffers, excluding CK, CK#, ODT, and CKE. For maximum power savings, the DLL is frozen during precharge power-down. Exiting active powerdown requires the device to be at the same voltage and frequency as when it entered power-down. Exiting precharge pow er-down requires the device to be at the same voltage as when it entered power-down; however, the clock frequency is allowed to change. See “Precharge Power-Down Clock Frequency Change” on page 76.

1Gb: x4, x8, x16 DDR2 SDRAM

Power-Down Mode

WR or tWTR are satisfied, as shown in Figures51 and 52 on

WTR is either two or tWTR/tCK,

The maximum duration for either active or precharge power-down is limited by the refresh requirements of the device entry and exit is limited by the

RFC (MAX). The minimum duration for po wer-down

CKE (MIN) parameter. While in power-down mode, CKE LOW, a stable clock signal, and stable power supply signals must be maintained at the inputs of the DDR2 SDRAM, while all other input signals are “Don’t Care” except ODT. Detailed ODT timing diagrams for differ ent power-down modes are shown in Figures 59 through 66.

The power-down state is synchronously exited when CKE is registered HIGH (in conjunction with an NOP or DESELECT command), as shown in Figure48 on page 70.

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Page 70

Figure 48: Power-Down

T1 T2 T3 T4 T5 T6 T7 T8

CK#

CHtCL

1Gb: x4, x8, x16 DDR2 SDRAM

Power-Down Mode

COMMAND

CKE

ADDRESS

DQS, DQS#

VALID

NOP NOP NOP

Enter

power-down

mode

CKE (MIN)

Exit

power-down

mode

tXP4

, tXARD

XARDS

VALID

CKE (MIN)

VALID VALID

DON’T CARE

Notes: 1. If this command is a PRECHARGE (or if the device is already in the idle state), then the

power-down mode shown is precharge power-down. If this command is an ACTIVE (or if at least one row is already active), then the power-down mode shown is active power-down.

2. No column accesses are allowed to be in progress at the time power-down is entered. If the

DLL was not in a locked state when CKE went LOW, the DLL must be reset after exiting power-down mode for proper READ operation.

CKE (MIN) of three clocks means CKE must be registered on three consecutive positive clock

edges. CKE must remain at the valid input level the entire time it takes to achieve the three clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of

IH window.

XP timing is used for exit precharge power-down and active power-down to any non-READ

IS + 2 x tCK + tIH. CKE must not transition during its tIS and

command.

XARD timing is used for exit active power-down to READ command if fast exit is selected

via MR (bit 12 = 0).

XARDS timing is used for exit active power-down to READ command if slow exit is selected

via MR (bit 12 = 1).

VALIDVALID

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Page 71

Table 12: CKE Truth Table

Notes 1–3, 12

Power-down L L X Maintain power-down 13, 14

Self refresh L L X Maintain self refresh 14

Bank(s) active H L DESELECT or NOP Active power-down

All banks idle H L DESELECT or NOP Precharge power-down

Notes: 1. CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) was the state of CKE at the previ-

2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge n.

3. Command (n) is the command registered at clock edge n, and action (n) is a result of com-

4. All states and sequences not shown are illegal or reserved unless explicitly described else-

5. On self refresh exit, DESELECT or NOP commands must be issued on every clock edge occur-

6. Self refresh mode can only be entered from the all banks idle state.

7. Must be a legal command, as defined in Table 6 on page 34.

8. Valid commands for power-down entry and exit are NOP and DESELECT only.

9. Valid commands for self refresh exit are NOP and DESELECT only.

10. Power-down and self refresh can not be entered while READ or WRITE operations, LOAD

11. Minimum CKE HIGH time is

12. The state of ODT does not affect the states described in this table. The ODT function is not

13. Power-down modes do not perform any REFRESH operations. The duration of power-down

14. “X” means “Don’t Care” (including floating around V

1Gb: x4, x8, x16 DDR2 SDRAM

Power-Down Mode

CKE

Current

State

Cycle

(n-1)

Current

Cycle (n)

L H DESELECT or NOP Power-down exit 4, 8

L H DESELECT or NOP Self refresh exit 4, 5, 9

H L REFRESH Self refresh entry 6, 9, 11 H H Shown in Table6 on page 34 7

ous clock edge.

mand (n).

where in this document.

ring during the

XSNR period. READ commands may be issued only after tXSRD (200 clocks)

is satisfied.

MODE operations, or PRECHARGE operations are in progress. See “Power-Down Mode” on page 69 and See “SELF REFRESH Command” on page 66 for a list of detailed restrictions.

CKE = 3 x tCK. Minimum CKE LOW time is tCKE = 3 x tCK. This

requires a minimum of 3 clock cycles of registration.

available during self refresh. See “ODT Timing” on page 79 for more details and specific restrictions.

mode is therefore limited by the refresh requirements.

However, ODT must be driven HIGH or LOW in power-down if the ODT function is enabled via EMR(1).

Command (n)

CS#, RAS#, CAS#, WE#

Action (n) Notes

4, 8, 10, 11

entry

4, 8, 10

entry

REF) in self refresh and power-down.

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Page 72

Figure 49: READ to Power-Down or Self Refresh Entry

1Gb: x4, x8, x16 DDR2 SDRAM

Power-Down Mode

CK#

COMMAND

CKE

ADDRESS

A10

DQS, DQS#

T0 T1 T2

READ

VALID

NOP NOP

RL = 3

NOP

T3 T4 T5

VALID

DOUT

VALID

OUTDOUT DOUT

Power-down or self refresh

Notes: 1. Power-down or self refresh entry may occur after the READ burst completes.

2. In the example shown, READ burst completes at T5; earliest power-down or self refresh

entry is at T6.

Figure 50: READ with Auto Precharge to Power-Down or Self Refresh Entry

CK#

COMMAND

CKE

T0 T1 T2

READ

NOP NOP

NOP

T3 T4 T5

VALID VALID

T6 T7

NOP

entry

T6 T7

NOP

CKE (MIN)

DON’T CARE TRANSITIONING DATA

CKE (MIN)

VALID

RL = 3

DOUT DOUTDOUT DOUT

TRANSITIONING DATA

Power-down

or self refresh

entry

DON’T CARE

ADDRESS

A10

DQS, DQS#

Notes: 1. Power-down or self refresh entry may occur after the READ burst completes.

2. In the example shown, READ burst completes at T5; earliest power-down or self refresh

entry is at T6.

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Page 73

Figure 51: WRITE to Power-Down or Self-Refresh Entry

1Gb: x4, x8, x16 DDR2 SDRAM

Power-Down Mode

CK#

COMMAND

CKE

ADDRESS

A10

DQS, DQS#

T0 T1 T2

WRITE

VALID

NOP NOP

WL = 3

NOP

T3 T4 T5

VALID VALID

DOUT

DOUT DOUT DOUT

VALID

WTR

or self refresh

Notes: 1. Power-down or self refresh entry may occur after the WRITE burst completes.

Figure 52: WRITE with Auto Precharge to Power-Down or Self Refresh Entry

CK#

COMMAND

CKE

T0 T1 T2

WRITE

NOP NOP

NOP

T3 T4 T5

VALID VALID

Ta0

VALID

T7 T8

NOP

Power-down

entry

Ta1 Ta2

NOP

CKE (MIN)

DON’T CARETRANSITIONING DATA

CKE (MIN)

ADDRESS

A10

DQS, DQS#

VALID

TRANSITIONING DATA

Notes: 1. WR is programmed through MR[9, 10, 11] and represents (tWR [MIN] ns / tCK) rounded up

OUT

WL = 3

DON’T CARE

to next integer

2. Internal PRECHARGE occurs at Ta0 when WR has completed; power-down entry may occur

CK later at Ta1, prior to tRP being satisfied.

1 x

OUTDOUTDOUT

Indicates a break in time scale

CK.

Power-down

or self refresh

entry

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Page 74

Figure 53: REFRESH Command to Power-Down Entry

1Gb: x4, x8, x16 DDR2 SDRAM

Power-Down Mode

CK#

T0 T1

COMMAND

VALID

REFRESH

CKE

Notes: 1. The earliest precharge power-down entry may occur is at T2 which is 1 x tCK after the

REFRESH command. Precharge power down entry occurs prior to

Figure 54: ACTIVE Command to Power-Down Entry

CK#

COMMAND

ADDRESS

T0 T1

VALID

ACTIVE

VALID

1 x tCK

T2 T3

NOP

Power-down

entry

NOP

CKE (MIN)

DON’T CARE

RFC (MIN) being satisfied.

CKE (MIN)

CKE

1 tCK

Power-down

DON’T CARE

entry

Notes: 1. The earliest active power-down entry may occur is at T2, which is 1 x tCK after the ACTIVE

command. Active power-down entry occurs prior to tRCD (MIN) being satisfied.

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Page 75

Figure 55: PRECHARGE Command to Power-Down Entry

1Gb: x4, x8, x16 DDR2 SDRAM

Power-Down Mode

CK#

T0 T1

COMMAND

ADDRESS

A10

VALID

PRECHARGE

VALID

ALL BANKS

SINGLE BANK

CKE

1 x tCK

Power-down entry

Notes: 1. The earliest precharge power-down entry may occur is at T2, which is 1 x tCK after the PRE-

CHARGE command. Precharge power-down entry occurs prio r to tRP (MIN) being satisfied.

Figure 56: LOAD MODE Command to Power-Down Entry

CK#

COMMAND

T0 T1

VALID LM

NOP

CKE (MIN)

DON’T CARE

T3 T4

NOP

ADDRESS

CKE

tRP2

VALID

MRD

Power-down

entry

CKE (MIN)

DON’T CARE

Notes: 1. The earliest precharge power-down entry is at T3, which is after tMRD is satisfied.

2. All banks must be in the precharged state and

RP met prior to issuing LM command.

3. Valid address for LM command includes MR, EMR, EMR(2), and EMR(3) registers.

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Page 76

1Gb: x4, x8, x16 DDR2 SDRAM

Precharge Power-Down Clock Frequency Change

When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off and CKE must be at a logic LOW level. A minimum of two differential clock cycles must pass after CKE goes LOW before clock frequency may change. The device input clock frequency is allowed to change only within minimum and maximum operating frequencies specified for the particular speed grade. During input clock frequency change, ODT and CKE must be held at stable LOW levels. Once the input clock frequency is changed, new stable clocks must be provided to the device before precharge power-down may be exited, and DLL must be reset via EMR after precharge power-down exit. Depending on the new clock frequency , an additional LM command might be r equired to appropriately set the WR MR[11, 10, 9]. During the DLL relock period of 200 cycles, ODT must remain off. After the DLL lock time, the DRAM is ready to operate with a new clock frequency.

Figure 57: Input Clock Frequency Change During Precharge Power-Down Mode

PREVIOUS CLOCK FREQUENCY NEW CLOCK FREQUENCY

CK#

T0 T1 T3 Ta0T2

CHtCL

x t

CK (MIN)

tCHt

1 x tCK (MIN)

Ta1 Ta2 Tb0Ta3

Ta4

CKE

COMMAND

ADDR

ODT

DQS, DQS#

VALID

High-Z

NOP

Enter precharge

power-down mode

CKE (MIN)

Frequency

change

NOP

Exit precharge

power-down mode

NOP

CKE (MIN)

DLL RESET

Indicates a break in time scale

200 x tCK

Notes: 1. If this command is a PRECHARGE (or if the device is already in the idle state), then the

power-down mode shown is precharge power-down, which is required prior to the clock frequency change.

2. A minimum of 2 x tCK is required after entering precharge power-down prior to changing

clock frequencies.

3. Once the new clock frequency has changed and is stable, a minimum of 1 x

prior to exiting precharge power-down.

4. Minimum CKE HIGH time is

CKE = 3 x tCK. Minimum CKE LOW time is tCKE = 3 x tCK. This

requires a minimum of three clock cycles of registration.

NOP

CK is required

VALID

DON’T CARE

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Page 77

RESET Function

(CKE LOW Anytime)

1Gb: x4, x8, x16 DDR2 SDRAM

RESET Function

DDR2 SDRAM applications may go into a reset state anytime during normal operation. If an application enters a reset condition, CKE is used to ensure the DDR2 SDRAM device resumes normal operation after re-initializing. All data will be lost during a reset condition; however, the DDR2 SDRAM device will continue to operate properly if the following conditions outlined in this section are satisfied.

The reset condition defined here assumes all supply voltages (V V

REF) are stable and meet all DC specifications prior to, during, and after the RESET

DD, VDDQ, VDDL, and

operation. All other input pins of the DDR2 SDRAM device are a “Don’t Care” during RESET with the exception of CKE.

If CKE asynchronously drops LOW during any valid operation (including a READ or WRITE burst), the memory controller must satisfy the timing parameter

DELAY before turning off the clocks. Stable cl ocks must exist at the CK, CK# inputs of the DRAM before CKE is raised HIGH, at which time the normal initialization sequence must occur. See “Initialization” on page 22. The DDR2 SDRAM device is now ready for normal operation after the initialization sequence. Figure58 on page 78 shows the proper sequence for a RESET operation.

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Page 78

Figure 58: RESET Function

1Gb: x4, x8, x16 DDR2 SDRAM

RESET Function

CK#

CKE

ODT

COMMAND

ADDRESS

A10

BA0, BA1, BA2

DQS

RTT

T0 T1 T2

READ

Col n

Bank a

High-Z

NOP

READ

Col n

Bank b

T3 T4 T5

NOP

DOUTDOUT

OUT

DELAY

Ta0

High-Z

NOP

Tb0

CKE (MIN)

PRE

ALL BANKS

High-Z

System

RESET

Indicates a break in time scale

Unknown RTT ON

Notes: 1. Either NOP or DESELECT command may be applied.

2. PRE = PRECHARGE command.

3. DM represents DM for x4/x8 configuration and UDM, LDM for x16 configuration. DQS rep-

resents DQS, DQS#, UDQS, UDQS #, LDQS, LDQS#, RDQS, RDQS# for the appropriate configuration (x4, x8, x16).

4. Initialization timing is shown in Figure 9 on page 22.

5. In certain cases where a READ cycle is interrupted, CKE going HIGH may result in the com-

pletion of the burst.

6. V

DD, VDDL, VDDQ, VTT, and VREF must be valid at all times.

T = 400ns (MIN)

Start of normal

initialization

sequence

DON’T CARE TRANSITIONING DATA

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Page 79

ODT Timing

1Gb: x4, x8, x16 DDR2 SDRAM

ODT Timing

Once a 12ns delay (tMOD) has been satisfied, and after the ODT function has been enabled via the EMR LOAD MODE command, ODT can be accessed under two timing categories. ODT will operate in either synchronous mode or asynchronous mode, depending on the state of CKE. ODT can switch anytime except during self refr esh mode and a few clocks after being enabled via EMR, as shown in Figure59 on page 80.

There are two timing categories for ODT—turn-on and turn-off. During active mode (CKE HIGH) and fast-exit power-down mode (any row of any bank open, CKE LOW, MR[12 = 0]), Figure61 on page 81 and Table 13 on page 81.

During slow-exit power-down mode (any row of any bank open, CKE LOW, MR[12] = 1) and precharge power-down mode (all banks/rows precharged and idle, CKE LOW),

AONPD and tAOFPD timing paramete rs are applied, as shown in Figure62 on page 82

and Table 14 on page 82.

AOND, tAON, tAOFD, and tAOF timing parameters are applied, as shown in

ODT turn-off timing, prior to entering any power-down mode, is determined by the parameter signal satisfies (MIN) is satisfied, shows the example where until state T3. When

ANPD (MIN), as shown in Figure 63 on page 83. At state T2, the ODT HIGH

ANPD (MIN) prior to entering power-down mode at T5. When tANPD

AOFD and tAOF timing parameters apply. Figure63 on page 83 also

ANPD (MIN) is not satisfied since ODT HIGH does not occur

ANPD (MIN) is not satisfied, tAOFPD timing parameters apply.

ODT turn-on timing prior to entering any power-down mode is determined by the parameter satisfies satisfied, where

ANPD (MIN) is not satisfied, tAONPD timing parameters apply.

ANPD, as shown in Figure 64 on page 84. At state T2, the ODT HIGH signal

ANPD (MIN) prior to entering power-down mode at T5. When tANPD (MIN) is

AOND and tAON timing parameters apply. Figure 64 also shows the example

ANPD (MIN) is not satisfied since ODT HIGH does not occur until state T3. When

ODT turn-off timing after exiting any power-down mode is d etermined b y the par ameter

AXPD (MIN), as shown in Figure 65 on page 85. At state Ta1, the ODT LOW signal satis-

fies

AXPD (MIN) after exiting power-do wn mode at state T1. When tAXPD (MIN) is satis-

fied,

AOFD and tAOF timing parameters apply. Figure65 also shows the example where

AXPD (MIN) is not satisfied since ODT LOW occurs at state Ta0. When tAXPD (MIN) is

not satisfied, ODT turn-on timing after exiting either slow-exit power-down mode or precharge

power-down mode is determined by the parameter on page 86. At state Ta1, the ODT HIGH signal satisfies down mode at state T1. When eters apply. Figure 66 also shows the example where ODT HIGH occurs at state Ta0. When

AOFPD timing parameters apply.

AXPD (MIN) is satisfied, tAOND and tAON timing param-

AXPD (MIN) is not satisfied, tAONPD timing

AXPD (MIN), as shown in Figure 66

AXPD (MIN) after exiting power-

AXPD (MIN) is not satisfied since

parameters apply.

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Page 80

1Gb: x4, x8, x16 DDR2 SDRAM

Figure 59: ODT Timing for Entering and Exiting Power-Down Mode

ODT Timing

Synchronous

ANPD (3 tCKs)

CKE latched LOW

CKE

Any mode except self refresh mode

Applicable modes

AOND/tAOFD

Applicable timing parameters

Active power-down fast (synchronous)

Active power-down slow (asynchronous)

Precharge power-down (asynchronous)

AOND/tAOFD (synchronous)

AONPD/tAOFPD (asynchronous)

MRS Command to ODT Update Delay

During normal operation, the value of the effective termination resistance can be changed with an EMRS set command.

Asynchronous

SynchronousSynchronous or

AXPD (8 tCKs)

CKE latched HIGH

Any mode except self refresh mode

AOND/tAOFD

MOD (MAX) updates the RTT setting.

Figure 60: Timing for MRS Command to ODT Update Delay

CMD

EMRS

CK#

ODT

AOFD

0ns

Internal

TT Setting

Old Setting Undefined New Setting

Notes: 1. LM command directed to mode register, which updates the information in EMR(1)[A6, A2],

TT (nominal).

i.e., R

2. To prevent any impedance glitch on the channel, the following conditions must be met:

AOFD must be met before issuing the LM command; ODT must remain LOW for the entire

duration of the

MOD window, until tMOD is met.

NOP NOPNOP NOP NOP

MOD

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Page 81

Figure 61: ODT Timing for Active or Fast-Exit Power-Down Mode

CK#

T1T0 T2 T3 T4 T5 T6

1Gb: x4, x8, x16 DDR2 SDRAM

ODT Timing

CMD

ADDR

CKE

ODT

VALIDVALID VALID VALIDVALID VALID

VALIDVALID VALID VALIDVALID VALID VALID

AOND

AOFD

AON (MIN)

AON (MAX)

RTT Unknown

AOF (MAX)

AOF (MIN)

Table 13: DDR2-400/533 ODT Timing for Active and Fast-Exit Power-Down Modes

Parameter Symbol Min Max Units

ODT turn-on delay ODT turn-on ODT turn-off delay ODT turn-off

AOND 2 2

AON

AOFD 2.5 2.5

AOF

AC (MIN)

AC (MAX) + 1,000 ps

AC (MAX) + 600 ps

VALID

DON’T CARE

Notes: 1. The half-clock of tAOFD’s 2.5 tCK assumes a 50/50 clock duty cycle. This half-clock value must

be derated by the amount of half-clock duty cycle error. For example, if the clock duty cycle was 47/53, tAOFD would actually be 2.5 - 0.03, or 2.47, for tAOF (MIN) and 2.5 + 0.03, or

2.53, for

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AOF (MAX).

Page 82

1Gb: x4, x8, x16 DDR2 SDRAM

Figure 62: ODT Timing for Slow-Exit or Precharge Power-Down Modes

ODT Timing

CK#

CMD

ADDR

CKE

ODT

AONPD (MIN)

Transitioning R

T1T0 T2 T3 T4 T5 T6

VALIDVALID VALID VALIDVALID VALID

VALIDVALID VALID VALIDVALID VALID VALID

AONPD (MAX)

AOFPD (MIN)

RTT Unknown

RTT On

AOFPD (MAX)

VALID

DON’T CARE

VALID

Table 14: DDR2-400/533 ODT Timing for Slow-Exit and Precharge Power-Down Modes

Parameter Symbol Min Max Units

ODT turn-on (power-down mode)

ODT turn-off (power-down mode)

AONPD

AOFPD

AC (MIN) + 2,000 2 x tCK +tAC (MAX) +

1,000

AC (MIN) + 2,000 2.5 x tCK + tAC (MAX) +

1,000

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Page 83

1Gb: x4, x8, x16 DDR2 SDRAM

Figure 63: ODT Turn-off Timings When Entering Power-Down Mode

CK#

T1T0 T2 T3 T4 T5 T6

ODT Timing

CKE

ODT

RTT

ODT

RTT

NOPNOP NOP NOPNOP NOP

ANPD (MIN)

AOFD

AOF (MIN)

AOFPD (MAX)

AOFPD (MIN)

AOF (MAX)

NOP

Transitioning RTT

RTT Unknown RTT On

DON’T CARE

Table 15: DDR2-400/533 ODT Turn-off Timings When Entering Power-Down Mode

Parameter Symbol Min Max Units

ODT turn-off delay ODT turn-off ODT turn-off

(power-down mode) ODT to power-down entry latency

Notes: 1. The half-clock of tAOFD’s 2.5 tCK assumes a 50/50 clock duty cycle. This half-clock value must

be derated by the amount of half-clock duty cycle error. For example, if the clock duty cycle was 47/53,

2.53, for

AOFD would actually be 2.5 - 0.03, or 2.47, for tAOF (MIN) and 2.5 + 0.03, or

AOF (MAX).

AOFD 2.5 2.5

AOF

AOFPD

ANPD 3

AC (MIN)

AC (MIN) +

2,000

AC (MAX) + 600 ps

2.5 x tCK + tAC (MAX) + 1,000

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Page 84

1Gb: x4, x8, x16 DDR2 SDRAM

Figure 64: ODT Turn-On Timing When Entering Power-Down Mode

CK#

T1T0 T2 T3 T4 T5 T6

ODT Timing

CKE

ODT

NOPNOP NOP NOPNOP NOP

ANPD (MIN)

AOND

AON (MAX)

AON (MIN)

AONPD (MAX)

AONPD (MIN)

NOP

Transitioning R

Unknown

Table 16: DDR2-400/533 ODT Turn-On Timing When Entering Power-Down Mode

Parameter Symbol Min Max Units

ODT turn-on delay ODT turn-on ODT turn-on

(power-down mode) ODT to power-down entry latency

AOND 2 2

AON

AONPD

ANPD 3

AC (MIN)

AC (MIN) +

2,000

AC (MAX) + 1,000 ps

(MAX) + 1,000

DON’T CARE

2 x tCK + tAC

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Page 85

Figure 65: ODT Turn-Off Timing When Exiting Power-Down Mode

CK#

COMMAND

T1T0 T2 T3 T4 Ta0 Ta1

NOPNOP NOP NOPNOP NOP NOP

AXPD (MIN)

1Gb: x4, x8, x16 DDR2 SDRAM

ODT Timing

Ta2 Ta3 Ta4 Ta5

NOPNOP NOP

NOP

CKE

ODT

RTT

ODT

RTT

Transitioning RTT

CKE (MIN)

RTT Unknown

TT On

AOFPD (MAX)

AOFPD (MIN)

DON’T CARE

AOFD

AOF (MIN)

Indicates a break in time scale

Table 17: DDR2-400/533 ODT Turn-Off Timing When Exiting Power-Down Mode

Parameter Symbol Min Max Units

ODT turn-off delay ODT turn-off ODT turn-off

(power-down mode) ODT to power-down exit latency

AOFD 2.5 2.5

AOF

AOFPD

AXPD 8

AC (MIN)

AC (MIN) +

2,000

AC (MAX) + 600 ps

2.5 x tCK + tAC (MAX) + 1,000

AOF (MAX)

Notes: 1. The half-clock of tAOFD’s 2.5 tCK assumes a 50/50 clock duty cycle. This half-clock value must

be derated by the amount of half-clock duty cycle error. For example, if the clock duty cycle was 47/53,

2.53, for

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AOFD would actually be 2.5 - 0.03, or 2.47, for tAOF (MIN) and 2.5 + 0.03, or

AOF (MAX).

Page 86

Figure 66: ODT Turn-On Timing When Exiting Power-Down Mode

CK#

COMMAND

T1T0 T2 T3 T4 Ta0 Ta1

NOPNOP NOP NOPNOP NOP

AXPD (MIN)

NOP

1Gb: x4, x8, x16 DDR2 SDRAM

ODT Timing

Ta2 Ta3 Ta4 Ta5

NOPNOP NOP

NOP

CKE

ODT

RTT

ODT

RTT

Transitioning RTT RTT Unknown RTT On

CKE (MIN)

AONPD (MAX)

AONPD (MIN)

DON’T CARE

AOND

AON (MIN)

Indicates a break in time scale

Table 18: DDR2-400/533 ODT Turn-On Timing When Exiting Power-Down Mode

Parameter Symbol Min Max Units

ODT turn-on delay ODT turn-on ODT turn-on

(power-down mode) ODT to power-down exit latency

AOND 2 2

AON

AONPD

AXPD 8

AC (MIN)

AC (MIN) +

2,000

AC (MAX) + 1,000 ps

(MAX) + 1,000

AON (MAX)

2 x tCK + tAC

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Page 87

1Gb: x4, x8, x16 DDR2 SDRAM

Absolute Maximum Ratings

Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not impli e d. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Table 19: Absolute Maximum DC Ratings

Parameter Symbol Min Max Units Notes

DD supply voltage relative to VSS

DDQ supply voltage relative to VSSQ

DDL supply voltage relative to VSSL

V Voltage on any ball relative to V Input leakage current; any input 0V ≤ V

not under test = 0V) Output leakage current; 0V ≤ V

disabled V

REF leakage current; VREF = Valid VREF level

Notes: 1. VDD, VDDQ, and VDDL must be within 300mV of each other at all times.

OUT ≤ VDDQ; DQ and ODT

REF ≤ 0.6 x VDDQ; however, VREF may be ≥ VDDQ provided that VREF ≤ 300mV.

2. V

3. Voltage on any I/O may not exceed voltage on V

IN ≤ VDD; all other balls

VDD –1.0 2.3 V 1

VDDQ –0.5 2.3 V 1, 2

VDDL–0.5 2.3 V 1

VIN, V OUT –0.5 2.3 V 3

VREF

–5 5 µA

–2 2 µA

DDQ.

Temperature and Thermal Impedance

It is imperative that the DDR2 SDRAM device’s temperature specifi ca tions, shown in Table 20 on page 88, be maintained in order to ensure the junction temperature is in the proper operating range to meet data sheet s peci fi cations. An important step in maintaining the proper junction temperature is using the device’s thermal impedances correctly. The thermal impedances are listed in Table21 on page 88 for the applicable and available die revision and packages.

Incorrectly using thermal impedances can produce significant errors. Read Micron technical note TN-00-08, “Thermal Applications,” prior to using the thermal impedances listed below. For designs that are expected to last several years and require the flexibility to use several designs, consider using final target theta values, rather than existing values, to account for larger thermal impedances.

The DDR2 SDRAM device’s safe junction temperature range can be maintained when the T temperature is too high, use of forced air and/or heat sinks may be required in order to satisfy the case temperature specifications.

(TC) specification is not exceeded. In applications where the device’s ambient

CASE

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Page 88

1Gb: x4, x8, x16 DDR2 SDRAM

Temperature and Thermal Impedance

Table 20: Temperature Limits

Parameter Symbol Min Max Units Notes

Storage temperature Operating temperature – commercial Operating temperature – industrial

Notes: 1. MAX storage case temperature; T

Figure 67. This case temperature limit is allowed to be exceeded briefly during package reflow, as noted in Micron technical note TN-00-15, “Recommended Soldering Parameters.”

2. MAX operating case temperature; T Figure 67.

3. Device functionality is not guaranteed if the device exceeds maximum T

4. Both temperature specifications must be satisfied.

5. Operating ambient temperature surrounding the package.

Table 21: Thermal Impedance

STG

AMB

–55 100 °C 1

085°C2, 3 –40 95 °C 2, 3, 4 –40 85 °C 4, 5

is measured in the center of the package, as shown in

STG

is measured in the center of the package, as shown in

during operation.

Die Rev Package Substrate

92-ball 2-layer 38.3 25.3 21.3 11.8 1.7

θ JA (°C/W)

Airflow =

0m/s

θ JA (°C/W)

Airflow =

4-layer 24.7 18.1 16.0 10.8

68-ball 2-layer 46.6 33.5 28.7 18.3 2.5

4-layer 32.8 26.1 23.3 18.0

84-ball 2-layer 46.6 33.5 28.7 18.3 2.5

4-layer 32.8 26.1 23.3 18.0

Last shrink

target

68-ball 2-layer 60.0 48.0 45.0 22.0 6.0

4-layer 39.0 34.0 32.0 22.0

84-ball 2-layer 55.0 42.0 37.0 22.0 6.0

4-layer 38.0 32.0 30.0 21.0

Notes: 1. Thermal resistance data is based on a number of samples from multiple lots and should be

viewed as a typical number.

2. This is an estimate; simulated number and actual results could vary.

Figure 67: Example Temperature Test Point Location

Test Point

19.0

1m/s

θ JA (°C/W)

Airflow =

2m/s θ JB (°C/W) θ JC (°C/W)

Test Point

16.50

9.5

5.5

11mm x 19mm “BT” FGBA

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11.00

10mm x 16.5 mm “B7” FBGA

10.00

6.75

5.00

Page 89

1Gb: x4, x8, x16 DDR2 SDRAM

AC and DC Operating Conditions

Table 22: Recommended DC Operating Conditions (SSTL_18)

All voltages referenced to VSS

Parameter Symbol Min Nom Max Units Notes

Supply voltage V

DDL supply voltage

I/O supply voltage I/O reference voltage I/O termination voltage (system)

Notes: 1. VDD and VDDQ must track each other. VDDQ must be ≤ VDD.

2. V

3. V

4. V

5. V

REF is expected to equal VDDQ/2 of the transmitting device and to track variations in the

DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±1 percent of the DC value. VREF(DC). This measurement is to be taken at the nearest VREF bypass capacitor.

TT is not applied directly to the device. VTT is a system supply for signal termination resis-

tors, is expected to be set equal to V

DDQ tracks with VDD; VDDL tracks with VDD. SSQ = VSSL = VSS.

DD 1.7 1.8 1.9 V 1, 5

DDL 1.7 1.8 1.9 V 4, 5

DDQ 1.7 1.8 1.9 V 4, 5

Vref(

DC) 0.49 x VDDQ 0.50 x VDDQ 0.51 X VDDQV 2

TT VREF(DC) - 40 Vref(DC)VREF(DC) + 40 mV 3

Peak-to-peak AC noise on VREF may not exceed ±2 percent of

REF, and must track variations in the DC level of VREF.

Table 23: ODT DC Electrical Characteristics

All voltages referenced to VSS

Parameter Symbol Min Nom Max Units Notes

TT effective impedance value for 75Ω setting

RTT1(EFF)60 75 90 Ω 1, 3

EMR (A6, A2) = 0, 1

TT effective impedance value for 150Ω setting

RTT2(EFF) 120 150 180 Ω 1, 3

EMR (A6, A2) = 1, 0

TT effective impedance value for 50Ω setting

TT3(EFF)40 50 60 Ω 1, 3

EMR (A6, A2) = 1, 1 Deviation of VM with respect to V

Notes: 1. R

DDQ/2

TT1(EFF) and RTT2(EFF) are determined by separately applying VIH(AC) and VIL(AC) to the ball

ΔVM –6 6 % 2

being tested, and then measuring current, I(VIH(AC)), and I(VIL(AC)), respectively.

(EQ 1)

IH AC()VIL AC()–

RTT EFF()

-------------------------------------------------------------

IH AC()()IVIL AC()()–

2. Measure voltage (VM) at tested ball with no load.

(EQ 2)

2 VM×

⎛⎞

ΔVM

3. IT device minimum values are derated by six percent when device operates between –40°C and 0°C (T

----------------- -

⎝⎠

VDDQ

1–

100×=

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Page 90

1Gb: x4, x8, x16 DDR2 SDRAM

Input Electrical Characteristics and Operating Conditions

Table 24: Input DC Logic Levels

All voltages referenced to VSS

Parameter Symbol Min Max Units

Input HIGH (logic 1) voltage Input LOW (logic 0) voltage

Table 25: Input AC Logic Levels

All voltages referenced to VSS

Parameter Symbol Min Max Units

Input HIGH (logic 1) voltage (-5E/-37E) Input HIGH (logic 1) voltage (-3/-3E/-25/-25E) Input LOW (logic 0) voltage (-5E/-37E) Input LOW (logic 0) voltage (-3/-3E/-25/-25E)

Figure 68: Single-Ended Input Signal Levels

1,150mV

IH(DC)VREF(DC) + 125 VDDQ + 300 mV

IL(DC) –300 VREF(DC) - 125 mV

IH(AC)VREF(DC) + 250 – mV

IH(AC)VREF(DC) + 200 – mV

IL(AC)–VREF(DC) - 250 mV

IL(AC)–VREF(DC) - 200 mV

VIH(AC)

1,025mV

936mV 918mV 900mV 882mV 864mV

775mV

650mV

Notes: 1. Numbers in diagram reflect nominal values.

IH(DC)

REF + AC Noise

REF + DC Error

REF - DC Error

VREF - AC Noise

VIL(DC)

IL(AC)

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Page 91

1Gb: x4, x8, x16 DDR2 SDRAM

Input Electrical Characteristics and Operating Conditions

Table 26: Differential Input Logic Levels

All voltages referenced to VSS

Parameter Symbol Min Max Units Notes

IN(DC)–300 VDDQ + 300 mV 1

DC input signal voltage DC differential input voltage AC differential input voltage AC differential cross-point voltage Input midpoint voltage

Notes: 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK,

CK#, DQS, DQS#, LDQS, LDQS#, UDQS, UDQS#, and RDQS, RDQS#.

2. V is the true input (such as CK, DQS, LDQS, UDQS) level and VCP is the complementary input (such as CK#, DQS#, LDQS#, UDQS#). The minimum value is equal to V ential input signal levels are shown in Figure 69.

3. V is the true input (such as CK, DQS, LDQS, UDQS, RDQS) level and V input (such as CK#, DQS#, LDQS#, UDQS#, RDQS#). The minimum value is equal to VIH(AC) VIL(AC), as shown in Table 25 on page 90.

4. The typical value of V and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross, as shown in Figure 69.

5. V the true input (CK, DQS) level and VCP is the complementary input (CK#, DQS#). VMP(DC) is expected to be approximately 0.5 x VDDQ.

ID(DC) specifies the input differential voltage | VTR - VCP | required for switching, where VTR

ID(AC) specifies the input differential voltage | VTR - VCP | required for switching, where VTR

MP(DC) specifies the input differential common mode voltage (VTR + VCP)/2 where VTR is

V V

ID(DC) 250 VDDQ + 600 mV 2

ID(AC) 500 VDDQ + 600 mV 3

IX(AC) 0.50 x VDDQ - 175 0.50 x VDDQ + 175 mV 4

Vmp(dc) 850 950 mV 5

IH(DC) - VIL(DC). Differ-

CP is the complementary

IX(AC) is expected to be about 0.5 x VDDQ of the transmitting device

Figure 69: Differential Input Signal Levels

2.1V

@ V

DDQ = 1.8V

CP8

1.075V

0.9V

0.725 V

- 0.30V

Notes: 1. This provides a minimum of 850mV to a maximum of 950mV and is expected to be VDDQ/2.

2. TR and CP must cross in this region.

3. TR and CP must meet at least V

4. TR and CP must have a minimum 500mV peak-to-peak swing.

5. TR and CP may not be more positive than V

6. For AC operation, all DC clock requirements must also be satisfied.

7. Numbers in diagram reflect nominal values (V

8. TR represents the CK, DQS, RDQS, LDQS, and UDQS signals; CP represents CK#, DQS#, RDQS#, LDQS#, and UDQS# signals.

IN(DC) MIN

VIX(AC)

VID(DC)

VIN(DC) MAX

VMP(DC)

ID(DC) MIN when static and is centered around VMP(DC).

DDQ + 0.3V or more negative than VSS - 0.3V.

DDQ = 1.8V).

ID(AC)

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Page 92

1Gb: x4, x8, x16 DDR2 SDRAM

Input Electrical Characteristics and Operating Conditions

Table 27: AC Input Test Conditions

Parameter Symbol Min Max Units Notes

RS See Note 2 1, 2, 7,

Input setup timing measurement reference level BA2–BA0, A0–A12 A0–A13 (A12 x16) A0–A13 A0–A14, CS#, RAS#, CAS#, WE#, ODT, DM, UDM, LDM, and CKE

Input hold timing measurement reference level BA2–BA0, A0–A12 A0–A13 (A12 x16) A0–A13 A0–A14, CS#, RAS#, CAS#, WE#, ODT, DM, UDM, LDM, and CKE

Input timing measurement reference level (single-ended) DQS for x4, x8; UDQS, LDQS for x16

Input timing measurement reference level (differential) CK, CK# for x4, x8, x16 DQS, DQS# for x4, x8; RDQS, RDQS# for x8 UDQS, UDQS#, LDQS, LDQS# for x16

Notes: 1. All voltages referenced to VSS.

2. Input waveform setup timing ( VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test, as shown in Figure 78 on page 107.

3. Input waveform hold (

IHb) timing is referenced from the input signal crossing at the VIL(DC) level for a rising signal and VIH(DC) for a falling signal applied to the device under test, as shown in Figure 78 on page 107.

4. Input waveform setup timing ( referenced from the crossing of DQS, UDQS, or LDQS through the VREF level applied to the device under test, as shown in Figure 80 on page 108.

5. Input waveform setup timing ( enabled is referenced from the cross-poin t of DQS/DQS#, UDQS/UDQS#, or LDQS/LDQS#, as shown in Figure 79 on page 107.

6. Input waveform timing is referenced to the crossing point level (V (VTR and VCP) applied to the device under test, where VTR is the “true” input signal and VCP is the complementary input signal, as shown in Figure 81 on page 108.

7. See “Input Slew Rate Derating” on page 93.

8. The slew rate for single-ended inputs is measured from DC-level to AC-level, (V

IH(AC) on the rising edge and VIL(AC) to VIH(DC) on the falling edge. For signals referenced

REF, the valid intersection is where the “tangent” line intersects VREF, as shown in

to V Figures 71, 73, 75, and 77.

9. The slew rate for differentially ended inputs is measured from twice the DC-level to twice the AC-level: 2 x V

IL(DC) to 2 x VIH(AC) on the rising edge and 2 x VIL(AC) to 2 x VIH(DC) on the

falling edge). For example, the CK/CK# would be –250mV to +500mV for CK rising edge and would be +250mV to –500mV for CK falling edge.

RH See Note 3 1, 3, 7,

Vref(dc) V

DDQ x 0.49 VDDQ x 0.51 V 1, 4, 7,

RD VIX(AC) V 1, 5, 6,

7, 9

ISb) is referenced from the input si gnal crossing at the

DS) and hold timing (tDH) for single-ended data strobe is

DS) and hold timing (tDH) when differential data strobe is

IX) of two input signals

IL(DC) to

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Page 93

Input Slew Rate Derating

1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

For all input signals, the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet value, respectively. Example:

IS, the nominal slew rate for a rising signal, is defined as the slew rate between the last

crossing of V

REF(DC) and the first crossing of VIH(AC) MIN. Setup nominal slew rate (

for a falling signal is defined as the slew rate between the last crossing of V the first crossing of V

IS (base) and tIH (base) value to the ΔtIS and ΔtIH derating

IS (total setup time) = tIS (base) + ΔtIS.

IL(AC) MAX.

IS)

REF(DC) and

If the actual signal is always earlier than the nominal slew rate line between shaded “V

REF(DC) to AC region,” use nominal slew rate for derating value (Figure 70 on page 95).

If the actual signal is later than the nominal slew rate line anywhere between shaded “V

REF(DC) to AC region,” the slew rate of a tangent line to the actual signal from the AC

level to DC level is used for derating value (see Figure 71 on page 96).

IH, the nominal slew rate for a rising signal, is defined as the slew rate between the last

crossing of V

IL(DC) MAX and the first crossing of VREF(DC).

falling signal, is defined as the slew rate between the last crossing of V the first crossing of V

REF(DC).

IH, nominal slew rate for a

IH(DC) MIN and

If the actual signal is always later than the nominal slew rate line between shaded “ DC to V

REF(DC) region,” use nominal slew rate for derating value (Figure72 on page 97).

If the actual signal is earlier than the nominal slew rate line anywhere between shaded “DC to V level to V

REF(DC)) region,” the slew rate of a tangent line to the actual signal from the DC

REF(DC) level is used for the derating value (Figure 73 on page 98).

Although the total setup time might be negative for slow slew rates (a valid input signal will not have reached V input signal is still required to complete the transition and reach V

IH(AC)/VIL(AC) at the time of the rising clock transition), a valid

IH(AC)/VIL(AC).

For slew rates in between the values listed in Tables28 and 29, the derating values may obtained by linear interpolation.

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Page 94

1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

Table 28: DDR2-400/533 Setup and Hold Time Derating Values (

CK, CK# Differential Slew Rate

Command/

Address Slew

Rate (V/ns)

4.0 +187 +94 +217 +124 +247 +154 ps

3.5 +179 +89 +209 +119 +239 +149 ps

3.0 +167 +83 +197 +113 +227 +143 ps

2.5 +150 +75 +180 +105 +210 +135 ps

2.0 +125 +45 +155 +75 +185 +105 ps

1.5 +83 +21 +113 +51 +143 +81 ps

1.0 0 0 +30 +30 +60 +60 ps

0.9 –11 –14 +19 +16 +49 +46 ps

0.8 –25 –31 +5 –1 +35 +29 ps

0.7 –43 –54 –13 –24 +17 +6 ps

0.6 –67 –83 –37 –53 –7 –23 ps

0.5 –110 –125 –80 –95 –50 –65 ps

0.4 –175 –188 –145 –158 –115 –128 ps

0.3 –285 –292 –255 –262 –225 –232 ps

0.25 –350 –375 –320 –345 –290 –315 ps

0.2 –525 –500 –495 –470 –465 –440 ps

0.15 –800 –708 –770 –678 –740 –648 ps

0.1 –1,450 –1,125 –1,420 –1,095 –1,390 –1,065 ps

2.0 V/ns 1.5 V/ns 1.0 V/ns

ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH

IS and tIH)

Units

Table 29: DDR2-667 Setup and Hold Time Derating Values (

CK, CK# Differential Slew Rate

Command/

Address Slew

Rate (V/ns)

4.0 +150 +94 +180 +124 +210 +154 ps

3.5 +143 +89 +173 +119 +203 +149 ps

3.0 +133 +83 +163 +113 +193 +143 ps

2.5 +120 +75 +150 +105 +180 +135 ps

2.0 +100 +45 +160 +75 +160 +105 ps

1.5 +67 +21 +97 +51 +127 +81 ps

1.0 0 0 +30 +30 +60 +60 ps

0.9 –5 –14 +25 +16 +55 +46 ps

0.8 –13 –31 +17 –1 +47 +29 ps

0.7 –22 –54 +8 –24 +38 +6 ps

0.6 –34 –83 –4 –53 +36 –23 ps

0.5 –60 –125 –30 –95 0 –65 ps

0.4 –100 –188 –70 –158 –40 –128 ps

0.3 –168 –292 –138 –262 –108 –232 ps

0.25 –200 –375 –170 –345 –140 –315 ps

0.2 –325 –500 –295 –470 –265 –440 ps

0.15 –517 –708 –487 –678 –457 –648 ps

0.1 –1,000 –1,125 –970 –1,095 –940 –1,065 ps

2.0 V/ns 1.5 V/ns 1.0 V/ns

ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH

IS and tIH)

Units

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Page 95

Figure 70: Nominal Slew Rate for tIS

CK#

1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

VDDQ

IH(AC) MIN

VIH(DC) MIN

REF(DC)

IL(DC) MAX

IL(AC) MAX

VSS

Setup slew rate falling signal

REF

to AC

region

Nominal slew rate

REF

to AC

region

ΔTF

REF

(DC)

- VIL(AC) MAX TF

ΔTR

Setup slew rate rising signal

VIH(AC) MIN -

REF

(DC)

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Page 96

Figure 71: Tangent Line for tIS

CK#

1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

IH(AC) MIN

IH(DC) MIN

REF(DC)

IL(DC) MAX

IL(AC) MAX

VDDQ

VSS

REF

to AC

region

Nominal line

ΔTF

Tangent line

Nominal line

Setup slew rate rising signal

ΔTR

tangent line [VIH(AC) MIN - V

ΔTR

Tangent line

REF(DC

REF

to AC

region

)]

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Page 97

Figure 72: Nominal Slew Rate for tIH

CK#

1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

VDDQ

IH(AC) MIN

IH(DC) MIN

REF(DC)

IL(DC) MAX

IL(AC) MAX

VSS

DC to V region

REF

Nominal slew rate

DC to V

REF

region

ΔTR

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ΔTF

Page 98

Figure 73: Tangent Line for tIH

CK#

VDDQ

IH(AC) MIN

IH(DC) MIN

REF(DC)

IL(DC) MAX

DC to V region

REF

1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

Tangent line

Nominal line

Tangent line

DC to V region

Nominal line

REF

IL(AC) MAX

VSS

Hold slew rate rising signal

tangent line [VREF(DC) - VIL(DC) MAX]

ΔTR

Hold slew rate falling signal

ΔTF

tangent line [VIH(DC) MIN - VREF(DC)]

ΔTF

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1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

Table 30: DDR2-400/533 tDS, tDH Derating Values with Differential Strobe

Notes: 1–7; all units in ps

DQS, DQS# Differential Slew Rate

DQ Slew Rate

(V/ns)

2.0125451254512545––––––––––––

1.5 8321832183219533 – – – – – – – – – –

1.000000012122424––––––––

0.9 – – –11 –14 –11 –14 1 –2 13 10 25 22 – – – – – –

0.8 – – – – –25 –31 –13 –19 –1 –7 11 5 23 17 – – – –

0.7 –––––––31–42–19–30–7–185–6176––

0.6 – – – – – – – – –43 –59 –31 –47 –19 –35 –7 –23 5 –11

0.5 – – – – – – – – – – –74 –89 –62 –77 –50 –65 –38 –53

0.4 – – – – – – – – – – – – –127 –140 –115 –128 –103 –116

4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns

ΔtDSΔtDHΔtDSΔtDHΔtDSΔtDHΔtDSΔtDHΔtDSΔtDHΔtDSΔtDHΔtDSΔtDHΔtDSΔtDHΔtDSΔtD

Notes: 1. For all input signals, the total tDS and tDH required is calculated by adding the data sheet

value to the derating value listed in Table 30.

DS nominal slew rate for a rising signal is defined as the slew rate between the last crossing

2. of VREF(DC) and the first crossing of VIH(AC) MIN. tDS nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V

REF(DC) and the first crossing of

VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between shaded “VREF(DC) to AC region ,” use no mi nal slew rate for derating value (see Figure 74). If the actual signal is later than the nominal slew rate line anywhere between shaded

REF(DC) to AC region,” the slew rate of a tangent line to the actual signal from the AC

“V level to DC level is used for derating value (see Figure 75).

DH nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC) MAX and the first crossing of VREF(DC). tDH nominal slew rate for a falling signal is defined as th e slew ra te betw een the la st cross ing of V IH(DC) MIN and the first crossing

REF (DC). If the actual signal is always later than the nominal slew rate line between

of V shaded “DC level to VREF(DC) region,” use nominal slew rate for derating value (see Figure 76). If the actual signal is earlier than the nominal slew rate line anywhere between shaded “DC to V

REF(DC) region,” the slew rate of a tangent line to the actual signal from the

DC level to VREF(DC) level is used for derating value (see Figure 77).

4. Although the total setup time might be negative for slow slew rates (a valid input signal will not have reached V

IH(AC)/VIL(AC) at the time of the rising clock transition), a valid input

signal is still required to complete the transition and reach VIH(AC)/VIL(AC).

5. For slew rates between the values listed in this table, the derating values may be obtained by linear interpolation.

6. These values are typically not subject to production test. They are verified by design and characterization.

7. Single-ended DQS requires special derating. The values in Table 32 are the DQS singleended slew rate derating with DQS referenced at V

DSb and tDHb. Table 33 provides the VREF-based fully derated values for the DQ (tDSa and

DHa) for DDR2-667. Table34 provides the VREF-based fully derated values for the DQ (tDSa

and

DHa) for DDR2-533. Table35 provides the VREF-based fully derated values for the DQ

DSa and tDHa) for DDR2-400.

(

REF and DQ referenced at the logic levels

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Page 100

1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

Table 31: DDR2-667 tDS, tDH Derating Values with Differential Strobe

Notes: 1–7; all units in ps

DQS, DQS# Differential Slew Rate

DQ Slew Rate

(V/ns)

2.0 100 63 100 63 100 63 112 75 124 87 136 99 148 111 160 123 172 135

1.5 67 42 67 42 67 42 79 54 91 66 103 78 115 90 127 102 139 114

1.0 0 0 0 0 0 0 121224243636484860607272

0.9 –5–14–5–14–5–147 –219103122433455466758

0.8 –13 –31 –13 –31 –13 –31 –1 –19 11 –7 23 5 35 17 47 29 59 41

0.7 –22 –54 –22 –54 –22 –54 –10 –42 2 –30 14 –18 26 –6 38 6 50 18

0.6 –34 –83 –34 –83 –34 –83 –22 –71 –10 –59 2 –47 14 –35 26 –23 38 –11

0.5 –60 –125 –60 –125 –60 –125 –48 –113 –36 –101 –24 –89 –12 –77 0 –65 12 –53

0.4 –100 –188 –100 –188 –100 –188 –88 –176 –76 –164 –64 –152 –52 –140 –40 –128 –28 –116

2.8 V/ns 2.4 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns

ΔtDSΔtDHΔtDSΔtDHΔtDSΔtDHΔtDSΔtDHΔtDSΔtDHΔtDSΔtDHΔtDSΔtDHΔtDSΔtDHΔtDSΔtD

Notes: 1. For all input signals the total tDS and tDH required is calculated by adding the data sheet

value to the derating value listed in Table 31.