The KP1500 series are monolithic integrated
circuits that provide all the active functions for a
step-down DC/DC converter, capable of driving a
3A load without additional transistor component.
Requiring a minimum number of external
component, the board space can be saved easily.
The external shutdown function can be controlled
by TTL logic level and then come into standby
mode. The internal compensation makes feedback
control have good line and load regulation without
external design. Regarding protected function,
thermal shutdown is to prevent over temperature
operating from damage, and current limit is against
over current operating of the output switch. The
KP1500 series operates at a switching frequency of
150Khz thus allowing smaller sized filter
components than what would be needed with lower
frequency switching regulators. Other features
include a guaranteed +4% tolerance on output
voltage under specified input voltage and output
load conditions, and +15% on the oscillator
frequency. The output version included fixed 3.3V,
5V, 12V, and an adjustable type. The packages are
available in a standard 5-lead TO-220(T) package
and a 5-lead TO-263(U).
Pin Assignments
( Top View )
Features
- 3.3V, 5V, 12V and adjustable output versions
- Adjustable version output voltage range, 1.23V to
5A Low Dropout Positive Adjustable or Fixed-Mode Regulator
Features
1.4V maximum dropout at full load current
•
Built-in thermal shutdown
•
•
Output current limiting
Adjustable output voltage or fixed 1.5V, 1.8V, 2.5V,
•
3.3V, 5.0V
•
Fast transient response
Good noise rejection
•
•
Package : TO252, TO263, TO220
General Description
AP1084 is a low dropout positive adjustable or fixedmode regulator with minimum of 5.0A output current
capability. The product is specifically designed to
provide well-regulated supply for low voltage IC
applications such as high-speed bus termination and
low current 3.3V logic supply. AP1084 is also well
suited for other applications such as VGA cards.
AP1084 is guaranteed to have lower than 1.4V
dropout at full load current making it ideal to provide
well-regulated outputs of 1.25 to 3.3V with 4.7 to
12V input supply.
1A Low Dropout Positive Adjustable or Fixed-Mode Regulator
Features
- 1.4V maximum dropout at full load current
- Fast transient response
- Output current limiting
- Built-in thermal shutdown
- Packages: SOT223, TO263, TO252, TO220,
SOT89
- Good noise rejection
- 3-Terminal Adjustable or Fixed 1.5V, 1.8V, 1.9V,
2.5V, 3.3V, 5.0V
Applications
- PC peripheral
- Communication
General Description
AP1117 is a low dropout positive adjustable or
fixed-mode regulator with minimum of 1A output
current capability. The product is specifically
designed to provide well-regulated supply for low
voltage IC applications such as high-speed bus
termination and low current 3.3V logic supply.
AP1117 is also well suited for other applications
such as VGA cards. AP1117 is guaranteed to have
lower than 1.4V dropout at full load current making
it ideal to provide well-regulated outputs of 1.25 to
5.0 with 6.4V to 12V input supply.
Ordering Information
AP 1117 X XX X X
AP1117
Low Dropout Regulator
Typical Circuit
5V
Tab is Vout
( 5V/3.3V fixed output )
Vin
Vout
GND
C1
100uF
PackageVout
E : SOT223-3L
K : TO263-3L
D : TO252-3L
T : TO220-3L
Y : SOT89-3L
The EN29LV040A is a 4-Megabit, electrically erasable, read/write non-volatile flash memory,
organized as 524,288 bytes. Any byte can be programmed typically in 8µs. The EN29LV040A
features 3.0V voltage read and write operation, with access times as fast as 45ns to eliminate the
need for WAIT states in high-performance microprocessor systems.
The EN29LV040A has separate Output Enable (OE), Chip Enable (CE), and Write Enable (WE)
controls, which eliminate bus contention issues. This device is designe d to allow eith er sing le
Sector or full chip erase operation, where each Sector can be individually protected against
program/erase operations or temporarily unprotected to erase or program. The device can sustain a
minimum of 100K program/erase cycles on each Sector.
CONNECTION DIAGRAMS
EN29LV040A
TABLE 1. PIN DESCRIPTION
Pin Name Function
A0-A18 Addresses
DQ0-DQ7 8 Data Inputs/Outputs
WE# Write Enable
CE# Chip Enable
OE# Output Enable
Vcc Supply Voltage
Vss Ground
FIGURE 1. LOGIC DIAGRAM
EN29LV040A
A0 - A18
CE#
OE#
WE#
DQ0 – DQ7
Philips SemiconductorsProduct specification
2 × 6 W stereo power amplifierTDA1517; TDA1517P
FEATURES
• Requires very few external components
• High output power
• Fixed gain
• Good ripple rejection
GENERAL DESCRIPTION
The TDA1517 is an integrated class-B dual output
amplifier in a plastic single in-linemedium powerpackage
with fin (SIL9MPF) and a plastic heat-dissipating dual
in-line package (HDIP18). The device is primarily
developed for multi-media applications.
• Mute/standby switch
• AC and DC short-circuit safe to ground and V
P
• Thermally protected
• Reverse polarity safe
• Capability to handle high energy on outputs (VP=0V)
channel separation40−−dB
closed loop voltage gain192021dB
noise output voltage (RMS value)−50−µV
crystal temperature−−150°C
ORDERING INFORMATION
TYPE
NUMBER
NAMEDESCRIPTIONVERSION
PACKAGE
TDA1517SIL9MPFplastic single in-line medium power package with fin; 9 leadsSOT110-1
TDA1517PHDIP18plastic heat-dissipating dual in-line package; 18 leadsSOT398-1
Philips SemiconductorsProduct specification
2 × 6 W stereo power amplifierTDA1517; TDA1517P
PINNING
SYMBOLPINDESCRIPTION
−INV11non-inverting input 1
SGND2signal ground
SVRR3supply voltage ripple rejection output
OUT14output 1
PGND5power ground
OUT26output 2
V
P
M/SS8mute/standby switch input
−INV29non-inverting input 2
7supply voltage
dbook, halfpage
INV1
SGND
SVRR
OUT1
PGND
OUT2
V
M/SS
INV2
1
2
3
4
5
TDA1517
6
7
P
8
9
MLC352
Fig.2 Pin configuration for SOT110-1.
FUNCTIONAL DESCRIPTION
The TDA1517 contains two identical amplifiers with
differential input stages.The gain ofeach amplifier is fixed
at 20 dB. A special feature of the device is the
mute/standby switch which has the following features:
• Low standby current (<100 µA)
• Low mute/standby switching current
• Mute condition.
(low cost supply switch)
dbook, halfpage
Pins 10 to 18 should be connected to GND or floating.
INV1
SGND
SVRR
OUT1
PGND
OUT2
V
M/SS
INV2
1
2
3
4
5
TDA1517P
6
7
P
8
9
18
17
16
15
14
13
12
11
10
MLC353
Fig.3 Pin configuration for SOT398-1.
数字控制音频处理芯片
SM9613
.
2
共 12 页
2-wire Serial EEPROM 32K/64K
AF24BC32/64
FEATURES:
• I nternally organized as 4096 x 8 (32K),
8192 x 8 (64K)
• Low-voltage and standard-voltage
operation : 1.8 to 5.5 V
Aplus Flash Technology’s AF24BC32/64 provides 32K/64K of serial electrically erasable and
programmable read-only memor y (EEPRO M). The wide Vdd range allows for low-voltage
operation down to 1.8V. The device, fabricated using traditional CMOS EEPROM technology, is
optimized for many industrial and commer cial applications where low-voltage and low-power
operation is essential. The AF24BC32/64 is available in 8-pin PDIP, 8- lead JEDEC SOIC, 8lead TSSOP
interface.
Figure 1. Pin Configurations
8-pin PDIP/TSSOP/SOIC/MSOP
A0
A1 WP
A2
GND 4
1
2
3
8-lead MSOP (AF24BC32)
and
8
7
6
5
Vcc
SCL
SDA
• Self-timed write cycle (5ms max)
• Bi- dir ectional data transfer protocol
• Write prot ect pin for hardware data
protection
• 32- byte page write modes
• Allows f o r par tial page writes
• 8- lead PDIP, 8-lead JEDEC SOIC, and
8-lead TSSOP, 8-lead MSOP
(AF24BC32) Packages
packages and is accessed via a 2-wire serial
Pin Name Function
A0 – A2 Address inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
GND Ground
Vcc Power Supply
• Multistandard true synchronous demodulation with
active carrier regeneration: very linear demodulation,
good intermodulation figures, reduced harmonics, and
excellent pulse response
• Gated phase detector for L and L-accent standard
• Fully integrated VIF Voltage Controlled Oscillator
(VCO), alignment-free, frequencies switchable for all
negative and positive modulated standards via I2C-bus
• Digital acquisition help, VIF frequencies of 33.4, 33.9,
38.0, 38.9, 45.75, and 58.75 MHz
• 4 MHz reference frequency input: signal from
Phase-Locked Loop (PLL) tuning system or operating
as crystal oscillator
• VIF Automatic Gain Control (AGC) detector for gain
control, operating as peak sync detector for negative
modulated signals and as a peak white detector for
positive modulated signals
• External AGC setting via pin OP1
• Precise fully digital Automatic Frequency Control(AFC)
detector with 4-bit digital-to-analog converter, AFC bits
readable via I2C-bus
• TakeOver Point (TOP) adjustable via I2C-bus or
alternatively with potentiometer
• Fully integrated sound carrier trap for 4.5, 5.5, 6.0,
and 6.5 MHz, controlled by FM-PLL oscillator
• Sound IF (SIF) input for single reference Quasi Split
Sound (QSS) mode, PLL controlled
TDA9885; TDA9886
• SIF-AGC for gain controlled SIF amplifier, single
reference QSS mixer able to operate in high
performance single reference QSS mode and in
intercarrier mode, switchable via I
• AM demodulator without extra reference circuit
• Alignment-free selective FM-PLLdemodulator with high
linearity and low noise
• I2C-bus control for all functions
• I2C-bus transceiver with pin programmable Module
Address (MAD)
• Four I2C-bus addresses via MAD.
2GENERAL DESCRIPTION
The TDA9885 is an alignment-free multistandard
(PAL and NTSC) vision and sound IF signal PLL
demodulator for negative modulation only and
FM processing.
The TDA9886 is an alignment-free multistandard
(PAL, SECAM and NTSC) vision and sound IF signal PLL
demodulator for positive and negative modulation,
including sound AM and FM processing.
3APPLICATIONS
• TV, VTR, PC and STB applications.
2
C-bus
4ORDERING INFORMATION
TYPE NUMBER
NAMEDESCRIPTIONVERSION
TDA9885T/V3SO24plastic small outline package; 24 leads; body width 7.5 mmSOT137-1
TDA9885TS/V3SSOP24plastic shrink small outline package; 24 leads; body width 5.3 mmSOT340-1
TDA9885HN/V3HVQFN32plastic, heatsink very thin quad flat package; no leads; 32 terminals;
body 5 × 5 × 0.85 mm
TDA9886T/V3SO24plastic small outline package; 24 leads; body width 7.5 mmSOT137-1
TDA9886TS/V3SSOP24plastic shrink small outline package; 24 leads; body width 5.3 mmSOT340-1
PACKAGE
SOT617-1
Philips SemiconductorsProduct specification
I2C-buscontrolledsingleand multistandard
TDA9885; TDA9886
alignment-free IF-PLL demodulators
7PINNING
PIN
SYMBOL
VIF11130VIF differential input 1
VIF22231VIF differential input 2
n.c.−−32not connected
OP1331output port 1; open-collector
FMPLL442FM-PLL for loop filter
DEEM553de-emphasis output for capacitor
AFD664AF decoupling input for capacitor
DGND775digital ground
n.c.−−6not connected
AUD887audio output
TOP998tuner AGC TakeOver Point (TOP)for resistor adjustment
SDA10109I
SCL111110I
SIOMAD121211sound intercarrier output and MAD select with resistor
n.c.−−12not connected
n.c.131313not connected
n.c.−−14not connected
TAGC141415tuner AGC output
REF1515164 MHz crystal or reference signal input
VAGC16−−VIF-AGC for capacitor
n.c.−1617not connected
CVBS171718composite video output
n.c.−−19not connected
AGND181820analog ground
VPLL191921VIF-PLL for loop filter
V
P
AFC212123AFC output
OP2222224output port 2; open-collector
n.c.−−25not connected
SIF1232326SIF differential input 1 and MAD select with resistor
SIF2242427SIF differential input 2 and MAD select with resistor
n.c.−−28not connected
n.c.−−29not connected
TDA9886T
TDA9886TS
202022supply voltage
TDA9885T
TDA9885TS
TDA9885HN
2
C-bus data input and output
2
C-bus clock input
DESCRIPTION
SHANGHAI JINXIN
ELECTRONICS LTD.
1. SCOPE.
This specification applies to VHF and UHF tuner model
UVL7605VMW
1 AGC VHF/UHF AGC Terminal
2 VT Tuning Voltage monitor
3 AS Address Select
4 SCL Serial Clock Line
5 SDA Serial Data Line
6 +B 5V supply voltage
7 BP Internal connection to pin 6
9 BT Tuning Voltage Supply
10 IF1 IF Output (balanced)
11 IF2 IF Output (balanced)
12 U /V ANT VHF/UHFANT Terminal
10. STANDRAD TEST CONDITIONS
Unless otherwise specified, the tests shall be carried out at the temperature
SPECIFICATION
UVL7605VMW
of 25℃±2℃and relative humidity of 65%±15%
11.ELECTRICAL CHARATERISTICS
11.1 Power gain
Min
VHF L 32 35 dB
VHF H 32 35 dB
UHF 32 35 dB
11.2 Gain variation
Min
VHF L 8.0 dB
VHF H 8.0 dB
UHF 8.0 dB
11.3 Noise figure
Typ Max Unit
Typ Max Unit
Min Typ Max Unit
VHF L 5.0 9.0 dB
VHF H 5.0 9.0 dB
HF 5.0 9.0 dB
UTC 78DXX LINEAR INTEGRATED CIRCUIT
3-TERMINAL 0.5A POSITIVE
VOLTAGE REGULATOR
DESCRIPTION
The UTC 78DXX family is monolithic fixed voltage
regulator integrated circuit .They are suitable for
applications that required supply current up to 0.5 A.
R8
R7
R10
1
TO-252
INPUT
1
OUTPUT
3
FEATURE
*Output current up to 0.5 A
*Fixed output voltage of 5V, 6V, 8V, 9V, 12V,
15V ,18V and 24V available
*Thermal overload shutdown protection
*Short circuit current limiting
*Output transistor SOA protection
EQUIVALENT CIRCUIT
R13R17R9
T10
R14
R15
Z1
R16
T8T9
T11
T4
T15
R1R2R4C1
T1T2
1:Input 2:GND 3:Output
Z2
T12
T14
R19
R18
T5
T13
T6
R5
R6
T7
T3
R12
R11
R3
GND
2
UTC UNISONIC TECHNOLOGIES CO. LTD
Philips SemiconductorsProduct specification
Dual 4-channel analog multiplexer,
demultiplexer
FEATURES
• Wide analog input voltage range from −5 V to +5 V
• Low ON-resistance:
–80Ω (typical) at VCC− VEE= 4.5 V
–70Ω (typical) at V
–60Ω (typical) at VCC− VEE= 9.0 V
• Logic level translation: to enable 5 V logic to
communicate with ±5 V analog signals
• Typical “break before make” built in
• Complies with JEDEC standard no. 7A
• ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 °C to +85 °C and−40 °C to+125 °C.
APPLICATIONS
• Analog multiplexing and demultiplexing
• Digital multiplexing and demultiplexing
• Signal gating.
− VEE= 6.0 V
CC
74HC4052; 74HCT4052
DESCRIPTION
The 74HC4052 and 74HCT4052 are high-speed Si-gate
CMOS devices and are pin compatible with the
HEF4052B. They arespecified in compliance with JEDEC
standard no. 7A.
The 74HC4052 and 74HCT4052 are dual 4-channel
analog multiplexers ordemultiplexers with common select
logic. Each multiplexer has four independent
inputs/outputs (pins nY0 to nY3) and a common
input/output (pin nZ). The common channel select logics
include two digital select inputs (pins S0 and S1) and an
active LOW enable input (pin E). When pin E = LOW, one
of the four switches isselected (low-impedance ON-state)
with pins S0 and S1. When pin E = HIGH, allswitches are
in thehigh-impedance OFF-state, independent of pinsS0
and S1.
VCC and GND are the supply voltage pins for the digital
control inputs (pins S0, S1, and E). The VCC to GND
ranges are 2.0 V to 10.0 V for 74HC4052 and
4.5 V to 5.5 V for 74HCT4052. The analog inputs/outputs
(pins nY0 to nY3 and nZ) can swing between VCC as a
positive limit and VEE as a negative limit. VCC− VEE may
not exceed 10.0 V.
FUNCTION TABLE
ES1S0
LLLnY0 and nZ
LLHnY1 and nZ
LHLnY2 and nZ
LHHnY3 and nZ
HXXnone
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care.
INPUT
For operation as a digitalmultiplexer/demultiplexer, VEEis
connected to GND (typically ground).
(1)
CHANNEL BETWEEN
Philips SemiconductorsProduct specification
Dual 4-channel analog multiplexer,
demultiplexer
PINNING
PINSYMBOLDESCRIPTION
12Y0independent input or output
22Y2independent input or output
32Zcommon input or output
42Y3independent input or output
52Y1independent input or output
6Eenable input (active LOW)
7V
8GNDground (0 V)
9S1select logic input
10S0select logic input
111Y3independent input or output
121Y0independent input or output
131Zcommon input or output
141Y1independent input or output
151Y2independent input or output
16V
EE
CC
74HC4052; 74HCT4052
negative supply voltage
positive supply voltage
handbook, halfpage
2Y0
2Y2
2Z
2Y3
2Y1
V
EE
GND
1
2
3
4
4052
5
6
E
7
8
MNB039
16
V
15
1Y2
14
1Y1
13
1Z
12
1Y0
11
1Y3
10
S0
9
S1
Fig.1Pin configuration DIP16, SO16 and
(T)SSOP16.Fig.2 Pin configuration DHVQFN16.
CC
1
4052
V
CC
8
2Y0
(1)
GND
V
16
9
S1
CC
S0
001aac117
terminal 1
index area
215
2Y21Y2
314
2Z1Y1
413
2Y31Z
512
2Y11Y0
611
E1Y3
710
V
EE
Transparent top view
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
PPLICATION
A
Cost Effective, Large Screen LCD
TVs
Portable / Handheld LCD TVs
Small Screen Video Displays
EATURES
F
Faroudja DCDi – Edge™
Integrated Triple ADC
Digital Input Port
Scaling Engine
Image Enhancement
Digital Output
OSD Controller
Embedded Microprocessor
VBI Slicer
JTAG Support
ACKAGE
P
208 PQFP
PRELIMINARY PRODUCT BRIEF
FLI8125
ESCRIPTION
D
The FLI8125 is a highly integrated cost effective mixed signal solution for LCD
TV and Digital Video applications. Capable of meeting global broadcast market
requirements, the FLI8125 incorporates a multi-standard video decoder, highspeed triple 8-bit Analog-to-Digital Converter (ADC), and front end switching.
The integrated VBI Slicer adds Closed Captioning (CC) and Teletext service
support, and the integrated microprocessor enables full system control without
external devices.
The FLI8125 can capture and process both video and RGB graphics streams.
The multi-standard video decoder is capable of accepting NTSC, PAL or
SECAM and other sub-formats. The integrated ADC accepts both analog RGB
and YPrPb inputs.
Interlaced video signals are converted into progressive scan signals using a
memory-less deinterlacing technique. Progressive scan signals are then
passed to the Faroudja DCDi – Edge suite for further image processing.
Faroudja DCDi – Edge incorporates Faroudja’s patented and Emmy award
winning Edge Correction technology eliminating objectionable staircasing on
diagonal lines; Horizontal Enhancement technology is used to make an image
look crisper and more realistic; Adaptive Contrast and Color (ACC) enables
dynamic contrast enhancement and color saturation correction; and Active
Color Management-II (ACM-II) enables color correction for subtle changes in
color that can dramatically improve the image (e.g., flesh tone, green stretch,
etc.). A fully programmable 3x3 matrix provides color space conversion and
global color correction technology. Programmable Color Look Up Tables
(CLUT) provides gamma correction of the output signal. Combined, these
features facilitate accurate color reproduction that enables use of the full
dynamic range on any fixed pixel display device.
I/O Legend: A = Analog, I = Input, O = Output, P = Power, G= Ground
Table 1: Analog Input Port
Pin Name No. I/O Description
VDD18_AB 158 AP Analog Power (1.8V) for A & B Channels. Must be bypassed with 0.1uF capacitor to the
NC 159 No Connection. Leave this pin open for normal operation.
GND18_C 160 AG Analog Ground (1.8V Return) for C channel. Must be directly connected to the analog system
VDD18_C 161 AP Analog Power (1.8V) for C Channel. Must be bypassed with 0.1uF capacitor to the analog
ADC_TEST 162 O Analog Front End Test O/P. Leave this Pin open. Used for factory testing purpose only.
AVDD_ADC 163 AP Analog Power (3.3V) for ADC. Must be bypassed with 0.1uF capacitor to the analog system
AGND 164 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
AGND 165 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
SV1P 166 AI Positive analog sync input for channel 1.
GNDS 167 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
A1P 168 AI Positive analog input ‘A’ for channel 1.
GNDS 169 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
B1P 170 AI Positive analog input ‘B’ for channel 1.
GNDS 171 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
C1P 172 AI Positive analog input ‘C’ for channel 1.
AVDD_A 173 AP Analog Power (3.3V) for ADC of Channel-A. Must be bypassed with 0.1uF capacitor to the
AN 174 AI Negative analog input ‘A’ for channels 1 through 4.
AGND 175 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
SV2P 176 AI Positive analog sync input for channel 2.
GNDS 177 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
A2P 178 AI Positive analog input ‘A’ for channel 2.
GNDS 179 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
B2P 180 AI Positive analog input ‘B’ for channel 2.
GNDS 181 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
C2P 182 AI Positive analog input ‘C’ for channel 2.
AVDD_B 183 AP Analog Power (3.3V) for ADC of Channel-B. Must be bypassed with 0.1uF capacitor to the
BN 184 AI Negative analog input ‘B’ for channels 1 through 4.
AGND 185 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
SV3P 186 AI Positive analog sync input for channel 3.
analog system ground plane.
ground plane on board.
system ground plane.
ground plane.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
analog system ground plane.
This acts as the return Path for the Sources connected to Channel-A Inputs. This has to be AC
coupled using a series 20 Ohm resistor and 0.1uF Capacitor network to Analog Ground Plane
on board.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
analog system ground plane.
This acts as the return Path for the Sources connected to Channel-B Inputs. This has to be AC
coupled using a series 20 Ohm resistor and 0.1uF Capacitor network to Analog Ground Plane
on board.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
GENESIS MICROCHIP FLI8125 Preliminary Datasheet
Pin Name No. I/O Description
GNDS 187 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
A3P 188 AI Positive analog input ‘A’ for channel 3.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
GNDS 189 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
B3P 190 AI Positive analog input ‘B’ for channel 3.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
GNDS 191 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
C3P 192 AI Positive analog input ‘C’ for channel 3.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
AVDD_C 193 AP Analog Power (3.3V) for ADC of Channel-C. Must be bypassed with 0.1uF capacitor to the
analog system ground plane.
CN 194 AI Negative analog input ‘C’ for channels 1 through 4.
This acts as the return Path for the Sources connected to Channel-C Inputs. This has to be
AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network to Analog Ground
Plane on board.
AGND 195 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
SV4P 196 AI Positive analog sync input for channel 4.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
GNDS 197 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
A4P 198 AI Positive analog input ‘A’ for channel 4.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
GNDS 199 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
B4P 200 AI Positive analog input ‘B’ for channel 4.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
GNDS 201 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
C4P 202 AI Positive analog input ‘C’ for channel 4.
The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network.
AVDD_SC 203 AP Analog Power (3.3V) for ADC of SYNC Channel. Must be bypassed with 0.1uF capacitor to
the analog system ground plane.
SVN 204 AI Negative analog sync input for channels 1 through 4.
This acts as the return Path for the Sources connected to SV Channel Inputs. This has to be
AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network to Analog Ground
Plane on board.
VO_GND 205 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
VOUT2 206 AO Analog VOUT signal
This is the Analog Video Output from the Decoder in the Composite Video format. This can be
amplified and be fed to any video display device.
VDD18_SC 207 AP Analog Power (1.8V) for SYNC Channel. Must be bypassed with 0.1uF capacitor to the analog
system ground plane.
GND18_SC 208 AG Analog Ground (1.8V Return) for SYNC channel. Must be directly connected to the analog
system ground plane on board.
Table 2: Low Bandwidth ADC Input Port
Pin Name No I/O Description
VDDA33_LBADC 1 AP Analog Power (3.3V) for Low Bandwidth ADC Block. Must be bypassed with 0.1uF capacitor.
LBADC_IN1 2 AI Low Bandwidth Analog Input-1. The Input signal connected to this Pin, must be bypassed with
LBADC_IN2 3 AI Low Bandwidth Analog Input-2. The Input signal connected to this Pin, must be bypassed with
LBADC_IN3 4 AI Low Bandwidth Analog Input-3. The Input signal connected to this Pin, must be bypassed with
LBADC_IN4 5 AI Low Bandwidth Analog Input-4. The Input signal connected to this Pin, must be bypassed with
LBADC_IN5 6 AI Low Bandwidth Analog Input-5. The Input signal connected to this Pin, must be bypassed with
LBADC_IN6 7 AI Low Bandwidth Analog Input-6. The Input signal connected to this Pin, must be bypassed with
a 0.1uF capacitor and could be in the range of 0V to 3.3V (peak to peak).
a 0.1uF capacitor and could be in the range of 0V to 3.3V (peak to peak).
a 0.1uF capacitor and could be in the range of 0V to 3.3V (peak to peak).
a 0.1uF capacitor and could be in the range of 0V to 3.3V (peak to peak).
a 0.1uF capacitor and could be in the range of 0V to 3.3V (peak to peak).
GENESIS MICROCHIP FLI8125 Preliminary Datasheet
Pin Name No I/O Description
a 0.1uF capacitor and could be in the range of 0V to 3.3V (peak to peak).
LBADC_RTN 8 AG This Pin provides the Return Path for LBADC inputs. Must be directly connected to the analog
system ground plane on board.
VSSA33_LBADC 9 AG Analog Ground for Low Bandwidth ADC Block. Must be directly connected to the analog
system ground plane on board.
Table 3: RCLK PLL Pins
Pin Name No I/O Description
GND_RPLL 11 DG Digital GND for ADC clocking circuit. Must be directly connected to the digital system ground
VDD_RPLL_18 12 DP Digital power (1.8V) for ADC digital logic. Must be bypassed with capacitor to Ground Plane.
VBUFC_RPLL 13 O Test Output. Leave this Pin Open. This is reserved for Factory Testing Purpose.
AGND_RPLL 14 AG Analog ground for the Reference DDS PLL. Must be directly connected to the analog system
XTAL 15 AO Crystal oscillator output.
TCLK 16 AI Reference clock (TCLK) from the 14.3MHz crystal oscillator.
AVDD_RPLL_33 17 AP Analog Power (3.3V) for RCLK PLL. Must be bypassed with 0.1uF capacitor.
plane.
ground plane.
Table 4: Digital Video Input Port
Pin Name No I/O Description
VID_CLK_1 153 I Video port data clock input meant for Video Input – 1. Up to 75Mhz
VIDIN_HS 122 I When Video Input – 1 is in BT656 Mode, this Pin acts as Horizontal Sync Input for Video
VIDIN_VS 121 I When Video Input – 1 is in BT656 Mode, this Pin acts as Vertical Sync Input for Video Input
Input – 2.
OR when Video Input – 1 is in 16 Bit Mode this Pin acts as Horizontal Sync Input for Video
Input – 1.
OR this Pin acts as Horizontal Sync Input for 24 Bit Video Input
– 2.
OR when Video Input – 1 is in 16 Bit Mode this Pin acts as Vertical Sync Input for Video
Input – 1.
OR this Pin acts as Vertical Sync Input for 24 Bit Video Input
IO Input YUV data in 8-bit BT656 of Video Input – 1
[Bi-Directional, 5V-tolerant]
OR Input Y Data in case of 16 Bit Video Input (CCIR601) of Video Input – 1
OR Input Red Data in case of 24 Bit Video Input
IO Input Pr / Pb Data in case of 16 Bit Video Input (CCIR601) of Video Input – 1
OR Input Green Data in case of 24 Bit Video Input
IO Input Blue Data in case of 24 Bit Video Input
OR Video Input – 2 in 8-bit with Embedded Sync / Separate Sync Sync in which case
VID_DATA_IN_16 acts as the LSB of the 8-bit Video input and VID_DATA_IN_23 acts as
the MSB of the 8-bit Video input.
GENESIS MICROCHIP FLI8125 Preliminary Datasheet
Pin Name No I/O Description
VID_CLK2 118 I Video port data clock input meant for Video Input – 2. Up to 75Mhz
VID_DE/FLD 115 I Video Active Signal Input or the Field Signal Input from external Digital Video Source.
[Input, 5V-tolerant]
Note: In case of Multiple Digital Video Input Sources, only one source could be in 8-Bit
with embedded Sync (BT656 mode) format.
Table 5: System Interface
Pin Name No I/O Description
RESETn 10 I Hardware Reset (active low) [Schmitt trigger, 5v-tolerant]
TEST 20 I For normal mode of operation connect this Pin to Ground.
GPIO15 21 IO This pin is available as a general-purpose input/output port. Also it is optionally
HSYNC2
VSYNC2 23 I Vertical Sync signal Input-2. Used when Analog RGB component signal carries separate
HOST_SCLK 24 IO Host input clock or 186 UART Data In or JTAG clock signal.
HOST_SDATA 25 IO Host input data or 186 UART Data Out or JTAG mode signal.
DDC_SCLK 26 IO
DDC_SDATA 27 IO
MSTR_SCLK 30 O Clock signal from Master Serial 2 Wire Interface Controller
MSTR_SDATA 31 IO Data signal meant for Master Serial 2 Wire interface Controller
TCK 34 IO This Pin accepts the Input Clock signal in case of Boundary Scan Mode.
TDI 35 IO This Pin accepts the Input Data signal in case of Boundary Scan Mode.
TMS 36 IO This Pin accepts the Input Test Mode Select signal in case of Boundary Scan Mode.
TRST 37 IO This Pin accepts the Boundary Scan Reset signal in case of Boundary Scan Mode.
GPIO6/IRin 38 IO Input from Infra Red Decoder can be connected to this Pin. When not used, this pin is
GPIO7/IRQin 41 IO Input Interrupt Request signal can be connected to this Pin. When not used, this pin is
GPIO8/IRQout 42 IO This Pin will give out the Interrupt Signal to interrupt external Micro. When not used, this
GPIO9/SIPC_SCLK 43 IO This Pin accepts the Clock signal from External Serial 2 Wire interface Bus if FLI8125 is
GPIO10/SIPC_SDATA/
A18
GPIO11/PWM0 47 IO This Pin can be programmed to give out Pulse Width Modulated Output Pulses for
GPIO12/PWM1 48 IO This Pin can be programmed to give out Pulse Width Modulated Output Pulses for
GPIO13/PWM2 51 IO This Pin can be programmed to give out Pulse Width Modulated Output Pulses for
GPIO14/PWM3/
SCART16
TDO 55 O This Pin provides the Output Data in case of Boundary Scan Mode.
HSYNC1 156 I Horizontal Sync signal Input-1. Used when Analog RGB component signal carries
22 I Horizontal Sync signal Input-2. Used when Analog RGB component signal carries
44 IO This Pin acts as the Data I/O signal when used with External Serial 2 Wire interface Bus if
52 IO This Pin can be programmed to give out Pulse Width Modulated Output Pulses for
Connect to ground with 0.01uF (or larger) capacitor.
programmable to give out the external chip select signal meant for external SRAM.
Refer to note below.
DDC2Bi clock for VGA Port [internal 10KΩ pull-up resistor]
DDC2Bi data for VGA Port [internal 10KΩ pull-up resistor]
available as General Purpose Input/output Port.
available as General Purpose Input/output Port.
pin is available as General Purpose Input/output Port.
programmed to be in Slave mode. When not used, this pin is available as General
Purpose Input/output Port.
FLI8125 is programmed to be in Slave mode. Or this Pin is programmable to give out
Address # 18 from the Internal Micro when used with 512K External Memory. When not
used, this pin is available as General Purpose Input/output Port.
external use. When not used, this pin is available as General Purpose Input/output Port.
external use. When not used, this pin is available as General Purpose Input/output Port.
external use. When not used, this pin is available as General Purpose Input/output Port.
external use. Or it can be programmed to sense the Fast Blank Input signal from a
SCART I/P source. When not used, this pin is available as General Purpose Input/output
Port.
GENESIS MICROCHIP FLI8125 Preliminary Datasheet
Pin Name No I/O Description
VSYNC1 157 I Vertical Sync signal Input-1. Used when Analog RGB component signal carries separate
101 O Clock Output meant for External OSD Controller
102 O Horizontal Sync Output meant for External OSD Controller
XOSD_CLK 103 O Vertical Sync Output meant for External OSD Controller
XOSD_HS 104 O Field Signal Output meant for External OSD Controller
PD20/B4/GPIO0
PD21/B5/GPIO1
PD22/B6/GPIO2
PD23/B7/GPIO3
86
87
88
89
separate HSYNC signal.
VSYNC signal.
IO These Pins provide the Panel Data as shown in the TTL Display Interface Table below.
These are available as General Purpose Input / Output Pins when not used as Panel
Data.
Table 6: LVDS Display Interface
Pin Name No I/O Description
PBIAS 53 O Panel Bias Control (backlight enable) [Tri-state output, 5V- tolerant]
PPWR 54 O Panel Power Control [Tri-state output, 5V- tolerant]
AVDD_LV_33 56 DP Digital Power for LVDS Block. Connect to digital 3.3V supply.
VCO_LV 57 O Reserved. Output for Testing Purpose only at Factory.
AVSS_LV 58 G Ground for LVDS outputs.
AVDD_OUT_LV_33 59 DP Digital Power for LVDS outputs. Connect to digital 3.3V supply.
CH3P_LV_E 60 O
CH3N_LV_E 61 O
CLKP_LV_E 62 O
CLKN_LV_E 63 O
CH2P_LV_E 64 O
CH2N_LV_E 65 O
CH1P_LV_E 66 O
CH1N_LV_E 67 O
CH0P_LV_E 68 O
CH0N_LV_E 69 O
AVSS_OUT_LV 70 G Ground for LVDS outputs.
AVDD_OUT_LV_33 71 DP Digital Power for LVDS outputs. Connect to digital 3.3V supply.
CH3P_LV_O 72 O
CH3N_LV_O 73 O
CLKP_LV_O 74 O
CLKN_LV_O 75 O
CH2P_LV_O 76 O
CH2N_LV_O 77 O
CH1P_LV_O 78 O
CH1N_LV_O 79 O
CH0P_LV_O 80 O
CH0N_LV_O 81 O
AVSS_OUT_LV 82 G Ground for LVDS outputs.
AVDD_OUT_LV_33 83 DP Digital Power for LVDS outputs. Connect to digital 3.3V supply.
These form the Differential Data Output for Channel – 3 (Even).
These form the Differential Clock Output Even Channel.
These form the Differential Data Output for Channel – 2 (Even).
These form the Differential Data Output for Channel – 1 (Even).
These form the Differential Data Output for Channel – 0 (Even).
These form the Differential Data Output for Channel – 3 (Odd).
These form the Differential Clock Output Odd Channel.
These form the Differential Data Output for Channel – 2 (Odd).
These form the Differential Data Output for Channel – 1 (Odd).
These form the Differential Data Output for Channel – 0 (Odd).
GENESIS MICROCHIP FLI8125 Preliminary Datasheet
Table 7: TTL Display Interface
Pin Name No I/O Description
For 8-bit panels For 6-bit panels
PBIAS 53 O Panel Bias Control (backlight enable) [Tri-state output, 5V- tolerant]
PPWR 54 O Panel Power Control [Tri-state output, 5V- tolerant]
AVDD_LV_33 56 DP Digital Power for TTL Block. Connect to digital 3.3V supply.
VCO_LV 57 O Reserved. Output for Testing Purpose only at Factory.
AVSS_LV 58 G Ground for TTL outputs.
AVDD_OUT_LV_33 59 DP Digital Power for TTL outputs. Connect to digital 3.3V supply.
R0 60 O Red channel bit 0 (Even) Not used.
R1 61 O Red channel bit 1 (Even) Not used.
R2 62 O Red channel bit 2 (Even) Red channel bit 0 (Even)
R3 63 O Red channel bit 3 (Even) Red channel bit 1 (Even)
R4 64 O Red channel bit 4 (Even) Red channel bit 2 (Even)
R5 65 O Red channel bit 5 (Even) Red channel bit 3 (Even)
R6 66 O Red channel bit 6 (Even) Red channel bit 4 (Even)
R7 67 O Red channel bit 7 (Even) Red channel bit 5 (Even)
G0 68 O Green channel bit 0 (Even) Not used.
G1 69 O Green channel bit 1 (Even) Not used.
AVSS_OUT_LV 70 G Ground for TTL outputs.
AVDD_OUT_LV_33 71 DP Digital Power for TTL outputs. Connect to digital 3.3V supply.
G2 72 O Green channel bit 2 (Even) Green channel bit 0 (Even)
G3 73 O Green channel bit 3 (Even) Green channel bit 1 (Even)
G4 74 O Green channel bit 4 (Even) Green channel bit 2 (Even)
G5 75 O Green channel bit 5 (Even) Green channel bit 3 (Even)
G6 76 O Green channel bit 6 (Even) Green channel bit 4 (Even)
G7 77 O Green channel bit 7 (Even) Green channel bit 5 (Even)
B0 78 O Blue channel bit 0 (Even) Not used.
B1 79 O Blue channel bit 1 (Even) Not used.
B2 80 O Blue channel bit 2 (Even) Blue channel bit 0 (Even)
B3 81 O Blue channel bit 3 (Even) Blue channel bit 1 (Even)
AVSS_OUT_LV 82 G Ground for TTL outputs.
AVDD_OUT_LV_33 83 DP Digital Power for TTL outputs. Connect to digital 3.3V supply.
PD20/B4 86 O Blue channel bit 4 (Even) Blue channel bit 2 (Even)
PD21/B5 87 O Blue channel bit 5 (Even) Blue channel bit 3 (Even)
PD22/B6 88 O Blue channel bit 6 (Even) Blue channel bit 4 (Even)
PD23/B7 89 O Blue channel bit 7 (Even) Blue channel bit 5 (Even)
DEN 90 O Display Data Enable
DHS 91 O Display Horizontal Sync.
DVS 92 O Display Vertical Sync.
DCLK 93 O Display Pixel Clock
PD24 115 O Red channel bit 0 (Odd) Not used.
PD25 114 O Red channel bit 1 (Odd) Not used.
PD26 113 O Red channel bit 2 (Odd) Red channel bit 0 (Odd)
PD27 112 O Red channel bit 3 (Odd) Red channel bit 1 (Odd)
PD28 111 O Red channel bit 4 (Odd) Red channel bit 2 (Odd)
PD29 110 O Red channel bit 5 (Odd) Red channel bit 3 (Odd)
PD30 109 O Red channel bit 6 (Odd) Red channel bit 4 (Odd)
PD31 108 O Red channel bit 7 (Odd) Red channel bit 5 (Odd)
PD32 107 O Green channel bit 0 (Odd) Not used.
GENESIS MICROCHIP FLI8125 Preliminary Datasheet
Pin Name No I/O Description
For 8-bit panels For 6-bit panels
PD33 106 O Green channel bit 1 (Odd) Not used.
PD34 105 O Green channel bit 2 (Odd) Green channel bit 0 (Odd)
PD35 104 O Green channel bit 3 (Odd) Green channel bit 1 (Odd)
PD36 103 O Green channel bit 4 (Odd) Green channel bit 2 (Odd)
PD37 102 O Green channel bit 5 (Odd) Green channel bit 3 (Odd)
PD38 101 O Green channel bit 6 (Odd) Green channel bit 4 (Odd)
PD39 123 O Green channel bit 7 (Odd) Green channel bit 5 (Odd)
PD40 124 O Blue channel bit 0 (Odd) Not used.
PD41 125 O Blue channel bit 1 (Odd) Not used.
PD42 128 O Blue channel bit 2 (Odd) Blue channel bit 0 (Odd)
PD43 129 O Blue channel bit 3 (Odd) Blue channel bit 1 (Odd)
PD44 130 O Blue channel bit 4 (Odd) Blue channel bit 2 (Odd)
PD45 131 O Blue channel bit 5 (Odd) Blue channel bit 3 (Odd)
PD46 132 O Blue channel bit 6 (Odd) Blue channel bit 4 (Odd)
PD47 118 O Blue channel bit 7 (Odd) Blue channel bit 5 (Odd)
Note: In case of 24 Bit TTL Panels the RGB Odd Channel Outputs will not be used. In that case they can be
made available for other purposes as Address & Data from On-Chip Micro or Digital Video Input Data.
Table 8: Parallel/Serial ROM Interface
Pin Name No I/O Description
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
ROM_OEN 118 O External PROM data Output Enable.
ROM_SDI/
ROM_WEN
ROM_SCSN/
ROM_CSN
95
O 256K x8 PROM Address. These pins also have bootstrap functionality.
97 O External PROM data Write Enable (for In-System-Programming of FLASH) or Serial Data
94 O External PROM data Chip Select or Serial PROM Chip Select (ROM_SCSN) for SPI ROM
For serial SPI ROM interface:
- ROM_ADDR17 will be Serial Clock (ROM_SCLK)
- ROM_ADDR16 will be Serial Data Output (ROM_SDO)
For 512K X 8 PROM, Address Signal A18 is available thru Pin # 44 which is GPIO10.
IO External PROM data input.
Input (SDI) for SPI ROM interface.
interface.
GENESIS MICROCHIP FLI8125 Preliminary Datasheet
Table 9: Digital Power and Ground
Pin Name No I/O Description
RVDD_3.3 32
116
154
CVDD_1.8 18
119
126
133
143
CRVSS 19
117
120
127
134
144
155
P Ring VDD. Connect to digital 3.3V.
49
98
P Core VDD. Connect to digital 1.8V.
28
39
45
84
G Chip ground for core and ring.
29
33
40
46
50
85
99
Table 10: JTAG Boundary Scan
Pin Name No I/O Description
TCK 34 I JTAG Boundary Scan TCK signal
TDO 55 O JTAG Boundary Scan TDO signal
TDI 35 I JTAG Boundary Scan TDI signal. Pad has internal 50K pull-up resistor.
TMS 36 I JTAG Boundary Scan RST signal. Pad has internal 50K pull-up resistor.
TRST 37 I JTAG Boundary Scan TMS signal. Pad has internal 50K pull-up resistor.
AP9435M
Advanced Power
Electronics Corp.
▼
▼ Simple Drive Requirement
▼ ▼
▼
▼ Low On-resistance
▼ ▼
▼
▼ Fast Switching
▼ ▼
D
D
D
SO-8
D
P-CHANNEL ENHANCEMENT MODE
POWER MOSFET
G
S
S
S
Description
The Advanced Power MOSFETs from APEC provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and cost-effectiveness.
The SO-8 package is universally preferred for all commercial-industrial
surface mount applications and suited for low voltage applications
such as DC/DC converters.
BV
R
DS(ON)
I
D
G
DSS
-30V
50mΩ
-5.3A
D
S
Absolute Maximum Ratings
SymbolUnits
V
DS
V
GS
=25℃A
I
D@TA
ID@TA=70℃A
I
DM
PD@TA=25℃W
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Continuous Drain Current
Pulsed Drain Current
Total Power Dissipation2.5
Linear Derating Factor0.02
T
STG
T
J
Storage Temperature Range
Operating Junction Temperature Range-55 to 150
Parameter
3
3
1
Rating
-30
± 20
-5.3
-4.7
-20
-55 to 150
V
V
A
W/℃
℃
℃
Thermal Data
SymbolValueUnit
Rthj-ambThermal Resistance Junction-ambient
Parameter
3
Max.50℃/W
S
ilicore
4 CHANNEL DRIVER MOTOR DRIVER D5954
DESCRIPTION
The D5954 is a 4 channel
driver for optical disc motor
driver. Dual channel current
feedback type drivers are built
in, in addition to dual channel
motor drivers
Outline Drawing
FEATURE
Wide dynamic range. (4.0V (typ.) at PreVcc=12V,PVcc=5V,RL=8Ω)
Separating Vcc into Pre+Power of sled motor, Power of loading motor and Power
of actuator ,can make better power efficiency, by low supply voltage drive.
Level shift circuit built in.
Thermal-shut-down circuit built in
Stand-by mode built in
BLOCK DIAGRAM
Silicore
r
D5954
PIN DESCRIPTION
No Symbol Function NO. SymbolFunction
1 VINFC Input for focus driver 15VOTK+
2 CECerr1 16VOTK- Inverting output for tracking
3 CECerr2
VINSL+ Non inverting input for
4
5 VINSL- Inverting input for OP-amp19PGND GND for power block
6 VOSL Output of OP-amp 20VNFTK Feedback for tracking driver
7 VNFFC Feedback for focus driver 21PVcc2
8 Vcc
9 PVcc1
10 PGND GND for power block 24 CTKerr2
11 VOSL- Inverting output for sled 25 CTKerr1
12 VOSL+
13 VOFC- Inverting output for focus 27BIAS Input for reference voltage
14 VOFC+
Connection with capacitor
for error amplifier
OP-amp
Vcc for pre-driver block
and power block of sled
Vcc for power block of
loading
Non inverting output for
sled
Non inverting output fo
focus
17OLD+
18VOLD-Inverting output for loading
22PreGND GND for pre-drive block
23VINLDInput for loading driver
26VINTKInput for tracking driver
28STBY Input for stand-by control
Non inverting output for
tracking
Non inverting output for
loading
Vcc for power block of
actuator
Connection with capacitor
for error amplifier
ABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
Characteristic Symbol Value Unit
Supply voltage Vcc 13.5 V
Power dissipation PD 1.7* W
Operating temperature Topr -35~85
Storage Temperature Tstg -40~150
* On less than 3%(percentage occupied by copper foil), 70×70mm2, t=1.6mm, glass
epoxy mounting. Reduce power by 13.6mW for each degree above 25°C
RN401, RN404, RN406 to be very close to CN402 snd
placed enroute on the trace to avoid stub on the
LVDS lines and also to have a very small stub on the
digital lines
KEYBOARD2
SCART-1-IN_PIN8/EIAJ1
SCART-2-IN_PIN8/EIAJ2
EIAJ3
FOR LDR( OPTION)
GPIO'S USED
JTAG_TCK
JTAG_TDI
JTAG_TMS
JTAG_RST
DIGITAL VIDEO INPUT HS
DIGITAL VIDEO INPUT VS
IR DECODING
STDBY / IRQIN
MUTE / IRQOUT
SIPSCL
SIPSDA
PWM0-PANEL BACKLIGHT
PWM1- LED1
PWM2- LED2
PWM3- SCART-1-IN-FB/EIAJ SENSE
CHIP SELECT FOR FLASH/SRAM
FOR ROM ADDRESS/16-bit INPUT
FOR ROM ADDRESS/16-bit INPUT
FOR ROM ADDRESS/16-bit INPUT
OR ROM ADDRESS/16-bit INPUT
F
FOR ROM ADDRESS/16-bit INPUT
FOR ROM ADDRESS/16-bit INPUT
FOR ROM ADDRESS/16-bit INPUT