Daewoo DSC3270 Schematic

TSC130BEF0

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Caution

: In this Manual, some parts can be changed for improving, their performance without notice in the parts list. So, if you need the latest parts information,please refer to PPL(Parts Price List) in Service Information Center (http://svc.dwe.co.kr).

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2. Specifications

PIN Signal Designation Matching Value

1 Audio Out (linked with 3)

2 Audio In (linked with 6)

3 Audio Out (linked with 1)

4 Audio Earth

5 Blue Earth

6 Audio in (linked with 2)

7 Blue in

8 Slow (Function) Switching

9 Green Earth

10 NC

11 Green In

12 NC

13 Red Earth

14 Rapid(Blanking) Switching Earth

15 Red In, C In

16 Rapid(Blanking) switching

0.5Vrms, Imp < 1 k (RF 60% MOD)

0.5Vrms, Imp < 10 k

0.5Vrms, Imp < 1 k (RF 60% MOD)

0.5Vrms, Imp < 10 k (RF 60% MOD)

0.7Vpp 2dB, Imp 75

TV : 0-2V, PERI : 9.5 - 12V, Imp > 10 k

0.7Vpp 2dB, Imp 75

Logic 0 : 0 - 0.4V, Logic 1 : 1 - 3V, Imp 75

17 Video Earth

18 Rapid Blanking Earth

19 Video Out

20 Video In, Y In

21 Common Earth

1Vpp 2dB, Imp 75

3. Circuit Block Diagram

5. Alignment Instructions

4-1. User Remocon RV-22D

TV..........................TXT

VOLUME........VOLUME

DOWN DOWN (CURSOR LEFT)

MENU.................MENU

POWER...........POWER

PR.......................PAGE

NUMBER NUMBER 0-9 0-9

TV..............................TXT

PR UP...............PAGE UP

VOLUME UP (CURSOR RIGHT)

NORMAL.................Not used

AV............................Not used

....

VOLUME UP

SLEEP............Not used

Not used.........CANCEL

Not used.............HOLD

RECALL.......SUBP AGE

STILL..............REVEAL

Not used.....................R

Not used....................G

TXT...................................TV

SOUND MODE.......Not used

MUTE..........................MUTE

Not used........................SIZE

ZOOM.....................Not used

EFFECT..................Not used

Not used..............................C

Not used..............................Y

678

4-6-3 VERTICAL SIZE

* The VERTICAL CENTER adjustment has to be done in advance.

1) Apply a RETMA PATTERN Signal.

2) Set the TV to Normal I mode.

3) Adjust the VERTICAL SIZE of the picture with the select V.size by volume UP/DOWN keys.

4-6-4 VERTICAL S-CORRECTION ( Fixed : Adjust if need be )

1) Apply a CROSSHATCH PATTERN Signal.

2) Adjust the S-CORRECTION to obtain the same distance between

horizontal lines with the S.Curve by volume UP/DOWN keys.

4-6-5 HORIZONTAL CENTER

1) Apply a RETMA PATTERN Signal.

2) Adjust picture centering with the select H.Center by volume UP/DOWN keys.

Alignment Instructions

4-7. EW 4-7-1 WIDTH

1) Apply a RETMA PATTERN Signal.

2) Adjust the horizontal width to make a perfect circle with the select H.Width

by volume UP/DOWN keys.

4-7-2 PARA

1) Apply a CROSSHATCH PATTERN Signal.

2) Adjust the vertical line to straight with the select E.W Para by volume UP/DOWN keys.

4-7-3 CORNER ( Fixed : Adjust if need be )

1) Apply a CROSSHATCH PATTERN Signal.

2) Adjust the vertical line to straight with the select EW.Cor T by volume

UP/DOWN keys.

4-7-4 SYMMETRY ( Fixed : Adjust if need be )

1) Apply a CROSSHATCH PATTERN Signal.

2) Turn R451 to the maximum left.

3) Adjust the symmetrical balance to be suitable with the select EW Sym by volume UP/DOWN keys.

Alignment Instructions

4-8. WHITE BALANCE 4-8-1 RGB Reference R

4-8-2 Beam Reference LOW ( 288, 301 : 10Cd/ ) HIGH ( 288, 301 : 10Cd/ )

4-8-3 Adjust G, B Gain with select Menu G,B of BIAS, DRIVE of select Menu so that R, G, B Bars are on the center position of the analog meter. If R Analog meter is not on center, control the Brightness +/- of user Remocon so as R Analog meter to be on the center position.

4-9. SUB BRIGHT 4-9-1 Pattern : Retma

4-9-2 Adjust the SUB BRIGHT with the select Sub Bri by volume UP/DOWN keys. so that only H-Center parts of picture can be seen.

4-10. DOUBLE TEXT CENTER 4-10-1 Pattern : Pattern RED

4-10-2 Select Menu

4-10-3 Select DT in SVC menu time to see the Double Text Picture. ( Left : RF Picture, Right : Text Picture )

4-10-4 Change the Double Text control keys volume UP/DOWN keys so that the left edge of text picture concur with the right edge of RF picture.

5. IC description

5-1. ST92195 (1) General Description

1.1 INTRODUCTION

The ST92195 microcnontoller is developed and manufac-

tured by STMicroelecrtonics using a proprietary n-well HCMOS process. Its performance derives from the use of

a flexible 256-register programming model for ultra-fast context switching and real-time event response. The intel-

ligent onchip peripherals offload the ST9 core from I/O and data management processing tasks allowing critical

application tasks to get the maximum use off core resources. The ST92195 MCU supports low power con-

sumption and low voltage operation for power-efficient and low-cost embedded systems.

1.1.1 ST9+Core

The advanced Core consists of the Central Processing

Unit (CPU), the Register File and the Interrupt controller. The general-purpose registers can be used as accumula-

tor, Index register, or address pointers. Adjacent register pairs make up 16-bit registers for addressing or 16-bit

processing. Although the ST9 has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/

stores, and memory/register and memory/memory exchanges. Two basic memory spaces are available :

Program Memory and the Register File, Which includes the control and status registers of the on-chip peripherals.

1.1.2 Power Saving Modes

To optimize performance versus power consumption, a

range of operating modes can be dynamically selected.

Run Mode.

CPU and peripherals running at the maximum clock speed delivered by the phase Locked Loop(PLL) of the

Clock Control Unit(CCU).

Wait For Interrupt Mode.

rupt(WFI) instruction suspends program execution until

an interrupt request is acknowledged. During WFI, the CPU clock is halted while the peripheral and interrupt

controller keep running at a frequency programmable via the CCU. In this mode, the power consumption of the

device can be reduced by more than 95%(LP WFI).

Wait For Interrupt Mode.

rupt(WFI) instruction, and if the Watchdog is not enable, the CPU and its peripherals stop operation and the I/O

This is the full speed execution mode with

The Wait For Inter-

ports enter high impedance mode. A reset is necessary to exit from Halt mode.

1.1.3 I/O Ports

Up to 28 I/O lines are dedicated to digital Input/Output.

These lines are grouped into up to five I/O Ports and can be configureed on a bit basis under software control to pro-

vide timing, status signals, timer and output, analog inputs, external interrupts and serial or parallel I/O.

1.1.4 TV Peripherals

A set of on-chip peripherals form a complete system for TV

set and VCR applications:

- Voltage Synthesis

- VPS/WSS Slicer

- Teletext Slicer

- Teletext Display RAM

- OSD

1.1.5 On Screen Display

The human interface is provided by the On Screen Display

module, this can produce up to 26 lines of up to 80 characters from a ROM defined 512 character set. The character

resolution is 10x10 dot. Four character sizes are supported. Serial attributes allow the user to select foreground

and background. Parallel attributes can be used to select additional foreground and background colors and underline

on a character by character basis.

1.1.6 Teletext and Display RAM

The internal 8k Teletext and Display storage RAM can be used to store Teletext pages as well as Display parame-

ters.

1.1.7 Teletext, VPS and WSS Data Slicers

The three on-board data slicers using a single external crystal are used to extract the Teletext, VPS and WSS

information from the video signal. Hardware Hamming decoding is provided.

1.1.8 Voltage Synthesis Tuning Control

14-bit Voltage Synthesis using the PWM (Pulse Width

Modulation)/BRM (Bit Rate Modulation) technique can be used to genetate tuning voltages for TV set applications.

The tuning voltage is output on one of two separate output pins.

IC description

1.1.9 PWM Output

Control of TV settings is able to be made with up to eight

8-bit PWM outputs, with a frequency maximum of 23,437Hz at 8-bit resolution(INTCLK=12 MHz). Low reso-

lutions with higher frequency operation can be programmed.

1.1.10 Serial Peripheral Interface (SPI)

The SPI bus is used to communicate with external

devices via the SPI, or bus communication standards. The SPI uses one or two lines for serial data and a

synchronous clock signal.

I C

1.1.11 Standard Timer (STIM)

The Standard Timer includes a programmable 16-bit down counter and an associated 8-bit prescaler with Sin-

gle and Continuous counting modes.

1.1.12 Analog/Digital Converter (ADC)

In addition there is a 3 channel Analog to Digital Converter with integral sample and hold, fast 5.7us conver-

sion timer and 6-bit guaranteed resolution.

(2) Feature

to operating temperature range

0 CO70 C Up to 24 MHz Operation @5V 10%

Minimum instruction cycle time : 375ns at 16MHz internal clock

64K Bytes ROM 256 Bytes RAM of Register file(accumulator or index

registers) 256 Bytes of on-chip static RAM

8K Bytes of TDSRAM(Teletext and Display RAM) 56-lead Shrink DIP package

28 fully programmable I/O pins Serial Peripheral Interface

Flexible Clock controller for OSD, Data Slicer and Core clocks running from one single low frequency external

crystal. Enhanced Display Controller with 26 rows of 40/80

characters

- Serial and Parallel attributes

- 10x10 dot Matrix, 512 ROM characters, definable by user

- 4/3 and 16/9 supported

- Rounding, fringe, double width, double height, scrolling, cursor, full background colour,

semitransparent mode and reduced intensity colour supported

Teletext unit, including Data slicer, Acquisition Unit and up to 8K Bytes RAM for Data Storage

VPS and Wode Screen Signalling slicer Integrated Sync Extractor and Sync Controller

14-bit Voltage Synthesis for tuning reference voltage Up to 6 external interrupts plus 1 non-maskable inter-

rupt 8x8-bit programmable PWM outputs with 5V open-

drain or push-pull capability 16-bit Watchdog timer with 8-bit prescale

16-bit standard timer with 8-bit prescaler usable as a Watchdog timer

3-channel Analog-to-Digital converter ; 6-bit guaranteed

Rich instruction set and 14-Addressing modes Versatile Development Tools, including Assembler,

Linker, C-compiler, Archiver, Source Level Debugger and Hardware Emulators with Real-Time Operating

System available from third parties Piggyback board available for prototyping

(3) Block Diagram

IC description

(4) PIN DESCRIPTION

RESET Reset (input, active low). The ST9+ is initialised

by the Reset signal. With the deactivation of RESET, program execution begins from the Program memory location pointed to by the vector contained in program memory locations 00h and 01h. R/G/B Red/Green/Blue. Video color analog DAC out- puts

FB Fast Blanking. Video analog DAC output. VOD Main power supply voltage(5V 10%, digital) WSCF, WSCR Analog pins for the VPS/WPP slicer line

PLL. MCFM Analog pin for the display pixel frequency multiplier. OSCIN, OSCOUT Oscillator (input and output). These pins connect a parallel-resonant crystal(24MHz maximum), or an external source to the on-chip clock oscillator and buffer. OSCIN is the input of the oscilltor inverter and internal clock generator; OSCOUT is the

HYNC/CSYNC Horizontal/Composite sync. Horizontal or composite video synchronisation input to OSD. Positive or negativety. PXFM Analog pin for the Display Pixel Frequency Multiplier AVDD Analog VDD of PLL. This pin must be tied to VDD externally to the ST92195.

GND Digital circuit ground. AGND Analog circuit ground(must be tied externally to

digital GND). CVBS1 Composite video input signal for the Teletext slicer and sync extraction. CVBS2 Composite video input signal for the VPS/WSS slicer. Pin AC coupled. AVDD1, AVDD2 Analog power supplies(must be tied externally to AVDD).

TXCF Analog pin for the VPS/WSS line PLL. CVBSO, JTDO, JTCK Test pins : leave floating.

output of the oscillator inverter. VSYNC Vertical Sync. Vertical video synchronisation input to OSD. Positive or negative polarity.

Figure 2. Pin Description

JTMS, TEST0 Test pins : must be tied to AVDD2. JTRST0 Test pin : must be tied to GND.

5-2. VPS 3215C(Video Processor)

(1) Description

The VPC 3215C is a high-quality, single-chip video front- end, which is targeted for 4:3 and 16:9, 100/120Hz TV sets. It can be conbined with other members of the DIGIT3000 IC family (such as CIP 3250A, DDP 3300A, TPU 3040) and/or it can be used with 3rd-party products.

(2) Features

- all-digital video processing

- high-performance adaptive 4H comb filter Y/C separator with adjustable vertical peaking

- multi-standard color decoder PAL/NTSC/SECAM

(3) Block Diagram

IC description

including all substandards

- 1 composite, 1 S-VHS input, 1 composite output

- integrated high-quality A/D converters and associated clamp and AGC circuits

- multi-standard sync processing

- linearhorizontal scaling (0.25... 4), as well as non-linear horizontal scaling panorama vision

- PAL + preprocessing (VPC 3215)

- submicron CMOS technology

(4) Pin Descriptions

Pin 1 - Ground, Analog Front-End GND Pin 2 - Ground, Analog Front-End GND Pin 3 - CCU 5 MHz Clock Output CLK5 This pin provides a clock frequency for the TV microcon- troller, e.g. a CCU 3000 controller, It is also used by the DDP 3300A display controller as a standby clock. Pin 4 - Standby Supply Voltage V In standby mode, only the clock oscillator is active, GND should be ground reference. Please activate RESQ before powering-up other supplies Pins 6 and 5-XTAL1 Crystal Input

STDBY

These pins are connected to an 20.25MHz crystal oscilla- tor which is digitally tuned by integrated shunt capaci- tances. The CLK20 and CLK5 clock signals are derived from this oscillator. An external clock can be fed into XTAL1. In this case, clock frequency adjustment must be switched off. Pin 7 - Ground, Analog Front-End GND Pin 9 - Ground, Output Pad Circuitry GND

Pin 10 - Interlace Output, INTLC This pin supplies the interlace information, 0 indicates first field, 1 indicates second field.

IC description

Pin 12 - Vertical Sync Pulse, VS This pin supplies the vertical sync signal. Pin 13 - Front Sync Pulse, FSY This pin supplies the front sync information. Pin 14 - Main Sync/Horizontal Sync Pulse MSY/HS This pin supplies the horizontal sync pulse information in line-locked mode. In DIGIT3000 mode, this pin is the main sync input. Pin 15 - Helper Line Output, Helper This signal indicated a helper line in PAL + mode. Pin 16 - Horizontal Clamp Pulse, HC This signal canbe used to clamp an external video signal, that is synchronous to the input signal. The timing is pro- grammable. Pin 17 - Active Video Output, AVO This pin indicates the active video output data. The signal is clocked with the LLC1 clock. Pin 18 - Double Output Clock, LLC2 Pin 19 - Output Clock, LLC1 This is the clock reference for the luma, chroma, and sta- tus outputs. Pin 26 - Ground, Output Pad Circuitry GND

Pin 20 to 25,28,29 - Luma Output Y0-Y7 These output pins carry the digital luminance data. The data are clocked with the LLC1 clock. Pin 30 - Main Clock Output CLK20 This is the 20.25MHz main clock output. Pin 31 - Supply Voltage, Digital Circuitry V Pin 34 - Ground, Digital Circuitry GND Pin 35 - Ground, Output Pad Circuitry GND Pin 36 - Supply Voltage, Output Pad Supply V

SUPD

SUPP

Pin 38 to 43,46,47 - Chroma Outputs C0-C7 These outputs carry the digital CrCb chrominance data. The data are clocked with the LL1 clock. The data are sampled at half the clock rate and multiplexed. The CrCb multiplex is reset for each TV line. Pin 48 to 50 - Picture Bus Priority PR0-PR2 The Picture Bus Priority lines carry the digital priority selection signals. The priority interface allows digital switching of up to 8 sources to the back-end processor. Switching for different sources is prioritized and can be on a per pixel basis. Pin 51 - Ground, Output Pad Circuitry GND

Pin 52 - VGAV-Input. This pin is connected to the vertical sync signal of a VGA signal. Pin 53 - Front-End/Back-End Data FPDAT This pininterfaces to theDDP 3300A back-endprocessor. The information for the deflection drives and for the white drive control,i.e. thebeam current limiter, is transmittedby this pin. Pin 54 - Reset Input RESQ A low level on this pin resets the VPC 32xx.

Pin 55 - Bus Data SDA The pin connects to the bus data line.

IC Pin 57 - Test Input TEST This pinenables factory test modes. For normal operation, it must be connected to ground. Pin 59 - Ground, Analog Front-End GND Pins 62,61,60,58 - Video 1-4 These are the analog video inputs. A CVBS or S-VHS luma signal is converted using the luma (Video 1) AD con- verter. The VIN1 input can alsobe switched to the chroma (Video 2) ADC. The input signal must be AC-coupled. Pin 63 - Chroma Input CIN This pin is connected to the S-VHS chroma signal. A resis- tive divider is used to bias the input signal to the middle of the converter input range. CIN can only be connected to the chroma (Video 2) A/D converter. The signal must be AC-coupled. Pin 64 - Analog Video Output, VOUT The analog video signal that is selected for the main (luma, CVBS)ADC is output at thispin. Anemitter follower is required at this pin. Pin 65 - Ground, Analog Shield Front-End GND Pin 66 - Supply Voltage, Analog Front-End V Pin 67 - Signal GND for Analog Input ISGND This is the high quality ground reference for the video input signals. Pin 68 - Reference Voltage Top VRT Via thispin, the referencevoltage for the A/D converters is decoupled. The pin is connected with 10uF/47nF to the Signal Ground Pin.

5-3. CIP3250A (Component Interface Processor) (1) Description

The CIP 3250A is a new CMOS IC that contains on a sin- gle chip the entire circuitry to interface analog YUV/RGB/ Fast Blank to a digital YUV system. The Fast Blank signal is used to control a soft mixer between the digitized RGB and an external digital YUV source. The CIP supports var- ious output formats such as YUV 4:1:1/4:2:2 or RGB 4:4:4.

Together with the DIGIT 3000 (e.g. VPC 32xxA) or DIGIT 2000 (e.g. DTI 2250), an interface to a TV-scanrate con- version circuit and/or multi-media frame buffer can be obtained.

(2) Feature

- analog input for RGB or YUV and Fast Blank

- triple 8 bit analog to digital converters for RGB/YUV with internal programmable clamping

- single 6 bit analog to digital converter for Fast Blank singnal

IC description

- digital matrix RGB => YUV (Y, B-Y, R-Y)

- luma contrast and brightness correction for signals from analog input

- color saturation and hue correction for signals from analog input

- digital input for DIGIT 2000 or DIGIT 3000 formats

- digital interpolation to 4:4:4 format

- high quality soft mixer controlled by Fast Blank signal

- programmable delays to match digital YUV in and analog RGB/YUV

- variable low pass filters for YUV output

- digital output in DIGIT 2000 and DIGIT 3000 formats, as well as RGB 4:4:4

- bus interface

- clock frequency 13.5...20.25 MHz

(3) Block Diagram

IC description

(4) Pin Description

Pin 1 - STANDBY Input Via this input pin, the standby mode of the CIP 3250A is enabled. A high level voltage switches all outputs to tristate mode, and power consumption is signigicantly reduced. When the IC IS returned to active mode, a reset is generated internally. Connect to VSS if not used.

Pins2to9-B7toB0Blue Output In a stand alone application, where the CIP 3250A serces as an A/D-converter, these are the output for the digital Blue signal (pure binary) or the digital U signal (2scom- plement). Leave vacant if not used.

Pin 10 to 17 - GL7 to GL0 Green/Luma Output At theseoutputs, thedigital luminancesignal isreceived in pure binary cided format for DIGIT 2000 and DIGIT 3000 applications. In a stand alone application, where the CIP 3250A serves as an A/D-converter, these are the outputs for the digital Green signal(pure binary) or the digital luma signal(pure binary). Leave vacant if not used.

Pin 18 - PVSS Output Pin Ground This isthe common groundconnection of all output stages and must be connected to ground. Note : All ground pins of the chip (i.e. 18,52,58,60,62,64,66 and68) must be connected together low resistive. The layout of the PCB must take into consid- eration the need for a low-noise ground.

Pin 19 - PVDD Output Pin Supply + 5V/+3.3V This pin supplies all output stages and must be connected to a positive supply voltage. Note : The layout of the PCB must take into consideration the needfor a low-noisesupply. A bypass capacitor has to be connected between ground and PVDD

Pins 20 to 27 - RC7 to RC0 Red/Chroma Output These are the outputs for the digital chroma signal in the DIGIT 3000 system, where U and V are multiplexed byte- wise. In a DIGIT 2000 system, RC3 to RC0 and RC7 to RC4 carry the halfbyte(nibble) multiplex format. In a stand alone application, where the CIP 3250A serces as an AD- converter, these are the outputs for the digital Red sig-

nal(pure binary) or the digital chroma V signal (2s compo- nent). Leave vacant if not used.

Pin 29 - AVI Active Video Input In a DIGIT 2000 application, this input can be connected to ground. In a DIGIT 3000 application, this input expects the DIGIT 3000 AVI signal. In a stand alone application, this inputexpects the VSYNC vertical syncpulse. Connect ground if not used.

Pin 30 - FSY Front Sync Input In a DIGIT 2000 application, this input pin expects the DIGIT 2000 SKEW protocol. In a DIGIT 3000 application, this inputexpects the DIGIT3000 FSY protocol. In a stand alone application, this unput expects the HSYNC horizon- tal sync pulse. Connect to ground if not used.

Pin 31 to 32 - SDA and SCL of -Bus These pins connect to the bus, which takes over the

control of the CIP 3250A via the internal registers. The SDA pin is the data input/output, and the SCL pin is the

clock input/output of bus control interface. All registers

are writerable(except address hex27) and readable.

Pin 33 to 35 - PRIO0 to PRIO2 Priority Bus These pins connect to the Priority Bus of a DIGIT 3000 application. The Picture Bus Priority lines carry the digital priority selection signals. The priority interface allows digi- tal switching of up to 8 sources to the backend processor. Switching for different sources is prioritized andcan be on a perpixel basis. In all otherapplications, they must not be connected.

Pin 36 to 43 - C0 to C7 Chroma Input These are the inputs for the digital chroma signal which can be received in binary offset or 2s complement coded format. In a DIGIT 2000(4:1:1) system, C3 to C0 take the halfbyte (nibble) multiplex format. C7 to C4 have to be connected to ground. Within the DIGIT 3000(4:2:2) sys- tem, Uand V aremultiplexed bytewise. Connect to ground if not used.

IC description

Pin 44 to 51 - L0 to L7 Luma Input These are the inputs for the digitalluma signal which must be in pure binary coded format. Connect to ground if not used.

Pin 52 - DVSS Digital Ground This is the common ground connectionof all digital stages and must be connected to ground. Note : All ground pins of the chip(i.e. 18, 52, 58, 60, 62, 64, 66, and 68) must be connected together low resistive. The layout of the PCB must take into consideration the need for a low-noise ground.

Pin 53 - DVDD Digital Supply +5V This pin supplies all digital stages and must be connected to a positive supply voltage. Note : The layout of the PCB must take into consideration the needfor a low-noisesupply. A bypasscapacitor has to be connected between ground and DVDD.

Pin 54 - CLK Main Clock Input This is the input for the clock signal. The frequency and vary in the range from 13.5MHz to 20.25MHz.

Pin 55 - RESQ Input A low signal at this input pingenerates a reset. The low-to- high transition of this signal should occur when the supply voltage is stable(power-on reset).

66, and 68) must be connected together low resistive. The layout of the PCB must take into consideration the need for a low-noise ground.

Pin 59 - ADREF Connect External Capacitor This pinshould be connectedto ground over a 10uF and a 100nF capacitor in parallel.

Pin 60 - SUBSTRATE This is connected to the platform which carries the die and must be cvonnected to the ground. Note : All ground pins of the chip(i.e. 18,52,58,60,62,64,66, and 68) must be connected together low resistive. The layout of the PCB must take into consideration the need for a low-noise ground.

Pin 61 - FB Analog Fast Blank Input This input takes the DC-coupled analog Fast Blank signal. The amplitude is 1.0V maximum at 75 Ohms. Connect to ground if not used.

Pin 62 - GNDFB Analod Ground This is the ground pin for the AD converter of the Fast Blank signal and has to be connected to ground. Note : All ground pins of the chip (i.e. 18,52,58,60,62,64, 62,64,66 and 68) must be connected together low resis- tive. The layout of the PCB must take into consideration the need for a low-noise ground.

Pin 56 - TMODE Input This pin is for test purposes only and must be connected to ground in normal operation.

Pin 57 - AVDD Analog Supply +5V This is the supply voltage pin for the A/D converters and must be connected to a positive supply voltage. Note : The layout of the PCB must take into consideration the needfor a low-noisesupply. A bypasscapacitor has to be connected between ground and AVDD.

Pin 58 - AVSS Analog Ground This is the ground pin for the A/D converters and must be connected to ground. Note : All ground pins of the chip (i.e. 18,52,58,60,62,64,

Pin 63 - BU Analog Blue/U Chroma Input The inputpin takesthe AC-coupledanalog compont signal Blue or U Chroma. The amplitude is 1.0V maximum at 75 Ohms and a coupling capacitor of 220 nF. Internally, the DC-offset of the input signal is adjusted via the program- mable internal clamping circuit. Connect to ground if not used.

Pin 64 - GNDBU Analog Ground This is the ground pin for the A/D converter of the Blue or U Chroma signal and must be connected to ground. Note : All ground pins of the chip(i.e. 18,52,58,60,62,64,66, and 68) must be connected together low resistive. The layout of the PCB must take into consideration the need for a low-noise ground.

IC description

Pin 65 - GY Analog Green/Luma Input This input pin takes the AC-coupled analog compinent sig- nal Green or Luma. The amplitude is 1.0V maximum at 75 Ohms and a couplign capacitor of 220nF. Internally, the DC-offset of the input signal is adjusted via the program- mable internal clamping circuit. Connect to ground if not used.

Pin 66 - GNDGY Analog Ground This is the ground pin for the A/D converter of the Green or Luma signal and must be connected to ground. Note : All ground pins of the chip(i.e. 18,52,58,60,62,64, 66, and 68) must be connected together low rresistive. The layout of the PCB must take into consideration the need for a low-noise ground.

Pin 67 - RV Analog Red/V Chroma Input This input pin takes the AC-coupled analog component signal Red or V Chroma. The amplitude is 1.0V maximum at 75ohms and a coupling capacitor of 220nF. Internally, the DC-offset of the input signal is adjusted via the pro- grammable internal clamping circuit. Connect to ground if not used.

Pin 68 - GNDRY Analog Ground This isthe ground pin for theA/D converter ofthe Red or V Chroma signal and must be connected to ground. Note : All ground pins of the chip (i.e. 18,52,58,62,64,66, and 68) must be connected together low resistive. Thelay- out of the PCB must take into consideration the need for a low-noise ground.

IC description

5-4. MSM5412222 ( 262, 214-Word X 12-Bit Field Memory )

(1) DESCRIPTION

The OKI MSM541222 is a high performance 3-Mbit, 256K x 12-bit, Field Memory. It is especially designed for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and Multi-media systems. MSM541222 is a FRAM for wide or low or low end use in general commodity TVs and VTRs exclusively. MSM5412222 is not designed for high end use in medical systems, professional graphics systems which require long term picture storage, data storage systems and others. Two or more MSM541222s can be cascaded directly without any delay devices between them. ( Cascading provides larger storage depth or a longer delay ).

Each of the 12-bit planes has separate serial write and read ports. These employ independent control clocks to support asynchronous read and write operations. Different clock rates are also supported, which allow alternate data rates between write and read data streams.

The MSM5412222 provides high speed FIFO, First-In First-Out, operation without external refreshing: MSM5412222 refreshes its DRAM storage cells automatically, so that it appears fully static to the users. Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and / or write control clock can be halted high or low for any duration as long as the power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic.

The MSM5412222s function is simple, and similar to a digital delay device whose delay-bit-length is easily set by reset timing. The delay length, and the number of read delay clocks between write and read, is determined by externally controlled write and read reset timings.

Additional SRAM serial registers, or line buffers for the initial access of 256 x 12-bit enable high speed first-bit- access with no clock delay just after the write of read reset timings.

Additionally, the MSM5412222 has a write mask function or input enable function (IE), and read-data skipping function or output enable function (OE). The differences between write enable (WE) and input enable (IE), and between read enable (RE) and output enable (OE) are that WE and RE can stop serial write / read address increments, but IE and OE cannot stop the increment, when write / read clocking is continuously applied to MSM5412222. The input enable (IE) function allows the user to write into selected locations of the memeory only, leaving the reset of the memory contents unchanged. This facilitates data processing to display a  picture in picture on a TV screen.

The MSM5412222 is similar in operation and functionality to OKI 1-Mbit Field Memory MSM514222B and 2-Mbit Field Memory MSM518222. Three MSM514222Bs or one MSM514222B plus one MSM518222 can be replaced simply by one MSM5412222.

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